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/**
********************************************************************************
* Copyright (c) 2021 Robert Bosch GmbH and others.
*
* This program and the accompanying materials are made
* available under the terms of the Eclipse Public License 2.0
* which is available at https://www.eclipse.org/legal/epl-2.0/
*
* SPDX-License-Identifier: EPL-2.0
*
* Contributors:
* Robert Bosch GmbH - initial API and implementation
********************************************************************************
*/
package org.eclipse.app4mc.amalthea.validations.sim.tests
import java.util.stream.Collectors
import org.eclipse.app4mc.amalthea.model.ISR
import org.eclipse.app4mc.amalthea.model.InterruptController
import org.eclipse.app4mc.amalthea.model.Label
import org.eclipse.app4mc.amalthea.model.LabelAccessEnum
import org.eclipse.app4mc.amalthea.model.Memory
import org.eclipse.app4mc.amalthea.model.OperatingSystem
import org.eclipse.app4mc.amalthea.model.PeriodicStimulus
import org.eclipse.app4mc.amalthea.model.ProcessingUnit
import org.eclipse.app4mc.amalthea.model.ProcessingUnitDefinition
import org.eclipse.app4mc.amalthea.model.Runnable
import org.eclipse.app4mc.amalthea.model.Task
import org.eclipse.app4mc.amalthea.model.TaskScheduler
import org.eclipse.app4mc.amalthea.model.builder.AmaltheaBuilder
import org.eclipse.app4mc.amalthea.model.builder.HardwareBuilder
import org.eclipse.app4mc.amalthea.model.builder.MappingBuilder
import org.eclipse.app4mc.amalthea.model.builder.OperatingSystemBuilder
import org.eclipse.app4mc.amalthea.model.builder.SoftwareBuilder
import org.eclipse.app4mc.amalthea.model.builder.StimuliBuilder
import org.eclipse.app4mc.amalthea.model.io.AmaltheaWriter
import org.eclipse.app4mc.amalthea.model.util.FactoryUtil
import org.eclipse.app4mc.amalthea.validations.sim.SimOsProfile
import org.eclipse.app4mc.amalthea.validations.sim.os.SimOsSchedulerAllocation
import org.eclipse.app4mc.validation.core.Severity
import org.eclipse.app4mc.validation.util.ValidationExecutor
import org.junit.Test
import static org.junit.Assert.assertTrue
class SimOsModelTests {
extension AmaltheaBuilder b1 = new AmaltheaBuilder
extension SoftwareBuilder b2 = new SoftwareBuilder
extension OperatingSystemBuilder b3 = new OperatingSystemBuilder
extension HardwareBuilder b4 = new HardwareBuilder
extension MappingBuilder b5 = new MappingBuilder
extension StimuliBuilder b6 = new StimuliBuilder
val executor = new ValidationExecutor(SimOsProfile)
private def createValidTestModel(){
val model =
amalthea [
stimuliModel[
periodicStimulus[
name="periodicStimulus"
offset= FactoryUtil.createTime("100 ms")
recurrence = FactoryUtil.createTime("10 ms")
]
]
softwareModel [
task [
name = "Task_valid"
activityGraph [
runnableCall[runnable = _find(Runnable, "R_1")]
labelAccess[
data = _find(Label, "label")
access = LabelAccessEnum.WRITE
]
]
stimuli += _find(PeriodicStimulus, "periodicStimulus")
]
isr [
name = "ISR_valid"
activityGraph[
runnableCall[runnable = _find(Runnable, "R_1")]
labelAccess[
data = _find(Label, "label")
access = LabelAccessEnum.WRITE
]
]
stimuli += _find(PeriodicStimulus, "periodicStimulus")
]
]
hardwareModel [
definition_ProcessingUnit [ name = "CoreDef" ]
structure [
name = "System"
module_Memory[
name="Memory"
]
module_ProcessingUnit [
name = "Core"
definition = _find(ProcessingUnitDefinition, "CoreDef")
access[
destination = _find(Memory, "Memory")
]
]
]
]
osModel [
operatingSystem [ name = "OS"
taskScheduler [ name = "Scheduler" ]
interruptController [name = "InterruptController"]
]
]
mappingModel [
taskAllocation [
task = _find(Task, "Task_valid")
scheduler = _find(TaskScheduler, "Scheduler")
]
isrAllocation [
isr = _find(ISR, "ISR_valid")
controller = _find(InterruptController, "InterruptController")
]
schedulerAllocation [
scheduler = _find(TaskScheduler, "Scheduler")
responsibility += _find(ProcessingUnit, "Core")
]
schedulerAllocation [
scheduler = _find(InterruptController, "InterruptController")
responsibility += _find(ProcessingUnit, "Core")
]
]
];
AmaltheaWriter.writeToFileNamed(model, "test-data/os/SimOsTestsModel.amxmi")
return model;
}
@Test
def void test_SimOsProcessingUnitAllocation() {
val model = createValidTestModel();
//add a schedulers with issues
model._find(OperatingSystem, "OS").taskScheduler[ name = "Scheduler_ambiguousMapping"]
model._find(OperatingSystem, "OS").taskScheduler[ name = "Scheduler_missingMapping" ]
//add isr controllers with issues
model._find(OperatingSystem, "OS").interruptController[ name = "InterruptController_ambiguousMapping"]
model._find(OperatingSystem, "OS").interruptController[ name = "InterruptController_missingMapping" ]
//add two mapping for "ambiguous" scheduler
model.mappingModel.schedulerAllocation[
scheduler = _find(TaskScheduler, "Scheduler_ambiguousMapping")
]
model.mappingModel.schedulerAllocation[
scheduler = _find(TaskScheduler, "Scheduler_ambiguousMapping")
]
//add two mapping for "ambiguous" interrupt controller
model.mappingModel.schedulerAllocation[
scheduler = _find(InterruptController, "InterruptController_ambiguousMapping")
]
model.mappingModel.schedulerAllocation[
scheduler = _find(InterruptController, "InterruptController_ambiguousMapping")
]
executor.validate(model)
executor.results
val errors = executor.results.stream.filter[it.severityLevel == Severity.ERROR].map[it.message].collect(Collectors.toList)
assertTrue(errors.size == 4)
// from missing scheduler allocation
assertTrue(errors.contains(SimOsSchedulerAllocation.MESSAGE_NO_SCHEDULER_ALLOCATION));
// from double scheduler allocation
assertTrue(errors.contains(SimOsSchedulerAllocation.MESSAGE_MANY_SCHEDULER_ALLOCATIONS));
// from missing interrupt controller allocation
assertTrue(errors.contains(SimOsSchedulerAllocation.MESSAGE_NO_INTERRUPT_CONTROLLER_ALLOCATION));
// from double scheduler allocation
assertTrue(errors.contains(SimOsSchedulerAllocation.MESSAGE_MANY_INTERRUPT_CONTROLLER_ALLOCATIONS));
}
}