Website build build-and-publish-website-6409
diff --git a/404.html b/404.html
index ac6581d..a551898 100644
--- a/404.html
+++ b/404.html
@@ -198,6 +198,10 @@
   </ul>
   
   <ul>
+    <li><a href="https://www.eclipse.org/app4mc/documentation/">Documentation</a><span class="lead">(Tue, May 8, 2018)</span></li>
+  </ul>
+  
+  <ul>
     <li><a href="https://www.eclipse.org/app4mc/news/2018-04-30_release_0.9.0/">APP4MC - Release 0.9.0 published</a><span class="lead">(Mon, Apr 30, 2018)</span></li>
   </ul>
   
@@ -298,10 +302,6 @@
   </ul>
   
   <ul>
-    <li><a href="https://www.eclipse.org/app4mc/documentation/">Documentation</a><span class="lead">(Fri, Jul 17, 2015)</span></li>
-  </ul>
-  
-  <ul>
     <li><a href="https://www.eclipse.org/app4mc/news/2015-06-11_project_proposal_posted/">APP4MC project proposal posted</a><span class="lead">(Thu, Jun 11, 2015)</span></li>
   </ul>
   
diff --git a/documentation/index.html b/documentation/index.html
index 2aa7483..65e548a 100644
--- a/documentation/index.html
+++ b/documentation/index.html
@@ -205,14 +205,16 @@
 
 <hr />
 
-<p><a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.3/index.html" target="_blank">APP4MC 0.8.3 - Online Help</a> (opens in new tab)</p>
+<p><a href="https://www.eclipse.org/app4mc/help/app4mc-0.9.0/index.html" target="_blank">APP4MC 0.9.0 - Online Help</a> (opens in new tab)</p>
 
-<p><a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.3-help.zip">APP4MC 0.8.3 - Help</a> (zip archive)</p>
+<p><a href="https://www.eclipse.org/app4mc/help/app4mc-0.9.0-help.zip">APP4MC 0.9.0 - Help</a> (zip archive)</p>
 
 <p><br></p>
 
 <h4 id="previous-versions">Previous versions:</h4>
 
+<p>APP4MC 0.8.3 - <a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.3/index.html">online</a> - <a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.3-help.zip">zip</a></p>
+
 <p>APP4MC 0.8.2 - <a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.2/index.html">online</a> - <a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.2-help.zip">zip</a></p>
 
 <p>APP4MC 0.8.1 - <a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.1/index.html">online</a> - <a href="https://www.eclipse.org/app4mc/help/app4mc-0.8.1-help.zip">zip</a></p>
diff --git a/help/app4mc-0.9.0-help.zip b/help/app4mc-0.9.0-help.zip
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index 0000000..fa5e588
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diff --git a/help/app4mc-0.9.0/css/frames.css b/help/app4mc-0.9.0/css/frames.css
new file mode 100644
index 0000000..2988b4d
--- /dev/null
+++ b/help/app4mc-0.9.0/css/frames.css
@@ -0,0 +1,43 @@
+
+body{
+    margin: 0;
+    padding: 0;
+    border: 0;
+    overflow: hidden;
+    height: 100%; 
+    max-height: 100%; 
+}
+
+#framecontent{
+    position: fixed;
+    top: 0;
+    bottom: 0; 
+    left: 0;
+    width: 350px; /*Width of frame div*/
+    height: 100%;
+    overflow: scroll;
+    background: #eee;
+    color: black;
+}
+
+#maincontent{
+    position: fixed;
+    top: 0; 
+    left: 350px; /*Set left value to WidthOfFrameDiv*/
+    right: 0;
+    bottom: 0;
+    overflow-y: scroll;
+    overflow-x: hidden;
+    background: #fff;
+}
+
+.innertube{
+    margin: 10px; /*Margins for inner DIV inside each DIV (to provide padding)*/
+}
+
+article {
+    border: 1px solid #000000;
+    margin: -8px -8px 13px -8px;
+    padding: 8px 14px;
+    box-shadow: 0 4px 3px #aaa;
+}
diff --git a/help/app4mc-0.9.0/css/help.css b/help/app4mc-0.9.0/css/help.css
new file mode 100644
index 0000000..6a251c8
--- /dev/null
+++ b/help/app4mc-0.9.0/css/help.css
@@ -0,0 +1,143 @@
+
+/* Additional styles */
+
+h1 {
+    font-size: 36px;
+    line-height: 40px;
+    text-align: center;
+    
+    color: #015A20;
+    margin: 40px 0;
+    padding: 10px;
+}
+
+h2 {
+    font-size: 30px;
+    line-height: 40px;
+    border-bottom: solid 1px #666;
+}
+
+h3 {
+    font-size: 24px;
+    line-height: 40px;
+}
+
+h4 {
+    font-size: 18px;
+    line-height: 20px;
+    font-style: italic;
+}
+
+
+body {
+	font-family: Helvetica,Arial,sans-serif;
+	line-height: 1.3;
+}
+
+
+/* styling of code listings and code snippets */
+
+pre, code {
+    background-color: #f7f7f9;
+    border: 1px solid #e1e1e8;
+}
+
+pre {
+	padding: 10px;
+	word-break: break-all;
+	word-wrap: break-word;
+	white-space: pre-wrap;
+	border-radius: 5px;
+}
+
+code {
+	vertical-align: 5%;
+	padding: 1px 3px 0px;
+    color: #d14;
+	border-radius: 2px;
+}
+
+pre code {
+	padding: 0px;
+    color: inherit;
+    background-color: transparent;
+    border: 0;
+}
+
+
+/* styling of tables: minimal, classic */
+
+td, th {
+	padding: 6px 6px 6px 6px;
+} 
+
+
+table.minimal td {
+	border-top: solid black 1px;
+} 
+
+
+table.classic {
+	border: solid black 1px;
+	border-collapse: collapse;
+}
+
+table.classic th, table.classic td {
+	border: solid black 1px;
+}
+
+
+/* borders and scaling (used for images) */
+
+img.gray {
+	background: #dddddd;
+	padding: 5px;
+	margin: 10px;
+}
+
+
+img.scale {
+	max-width: 100%;
+	height: auto;
+}
+
+
+img.gray_scale {
+	background: #dddddd;
+	padding: 5px;
+	margin: 10px;
+ 
+	max-width: 100%;
+	height:auto;
+}
+
+
+img.shadow {
+	box-shadow: 0px 0px 5px 8px #ccc;
+	margin: 10px;
+}
+
+
+/* not applicable (because border=0 is added by default) */
+
+img.dotted {
+	border-width: 2;
+	border-color: gray;
+	border-style: dotted;
+}
+
+
+.validation-rule {
+    border-style: solid;
+    border-width: thin;
+    margin-left: 1.5cm;
+	margin-right: 1.5cm;
+}
+
+.validation-rule:before {
+	font-weight: normal;
+	font-size: larger;
+	line-height: 200%;
+	margin-left: -0.75cm;
+    content: "\26A0  VALIDATION RULES";
+}
diff --git a/help/app4mc-0.9.0/css/toc-icons.png b/help/app4mc-0.9.0/css/toc-icons.png
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diff --git a/help/app4mc-0.9.0/css/toc-style.css b/help/app4mc-0.9.0/css/toc-style.css
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+++ b/help/app4mc-0.9.0/css/toc-style.css
@@ -0,0 +1,128 @@
+
+/*    Table of contents tree    */
+
+
+
+/* --- basic toc-tree settings --- */
+
+.toc-tree
+{
+	user-select: none;
+	font-family: Helvetica, Arial, Sans-serif;
+	font-style: normal;
+	font-size: 14px;
+	line-height: 120%;
+}
+
+.toc-tree ul,
+.toc-tree li
+{
+	padding: 0;
+	margin: 4px 0;
+	list-style: none;
+	white-space: nowrap;
+}
+
+.toc-tree input
+{
+	position: absolute;
+	opacity: 0;
+}
+
+.toc-tree label,
+.toc-tree label::before,
+.toc-tree a
+{
+	display: inline-block;
+	height: 16px;
+	line-height: 16px;,
+	vertical-align: middle;
+}
+
+/* --- link decoration --- */
+
+.toc-tree a,
+.toc-tree a:visited
+{
+	text-decoration: none;
+	color: #0000aa;
+}
+
+.toc-tree a:hover
+{
+	text-decoration: underline;
+}
+
+/* --- indented sub tree --- */
+
+.toc-tree input + label + ul
+{
+	margin: 0 0 0 22px;
+}
+
+/* --- hidden sub tree --- */
+
+.toc-tree input ~ ul
+{
+	display: none;
+}
+
+/* --- visible sub tree --- */
+
+.toc-tree input:checked ~ ul
+{
+	display: block;
+}
+
+/* --- cursor --- */
+
+.toc-tree input,
+.toc-tree label,
+.toc-tree label::before
+{
+	cursor: pointer;
+}
+
+.toc-tree label.leaf,
+.toc-tree label.leaf::before
+{
+	cursor: default;
+}
+
+/* --- icons definition --- */
+
+.toc-tree label,
+.toc-tree label::before
+{
+	background: url("toc-icons.png") no-repeat;
+}
+
+/* --- document icon --- */
+
+.toc-tree label
+{
+	background-position: 18px 0;
+}
+
+/* --- plus / minus icon (for expandable nodes)--- */
+
+.toc-tree label::before
+{
+	content: "";
+	width: 16px;
+	margin: 0 22px 0 0;
+	vertical-align: middle;
+	background-position: 0 -32px;
+}
+
+.toc-tree input:checked + label::before
+{
+	background-position: 0 -16px;
+}
+
+/* --- empty icon (for leaf nodes) --- */
+
+.toc-tree label.leaf::before
+{
+	background-position: 0 -48px;
+}
diff --git a/help/app4mc-0.9.0/docs/amalthea_hardware_model.pdf b/help/app4mc-0.9.0/docs/amalthea_hardware_model.pdf
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+<!DOCTYPE html>
+
+<!--
+ ! Copyright (c) 2018 Robert Bosch GmbH and others.
+ ! All rights reserved. This program and the accompanying materials 
+ ! are made available under the terms of the Eclipse Public License v1.0
+ ! which accompanies this distribution, and is available at
+ ! http://www.eclipse.org/legal/epl-v10.html
+ -->
+
+<html lang="en">
+
+<head>
+  <meta charset="UTF-8">
+  <title>APP4MC Documentation</title>
+  <link rel="stylesheet" href="css/help.css" type="text/css">
+  <link rel="stylesheet" href="css/frames.css" type="text/css">
+  <link rel="stylesheet" href="css/toc-style.css" type="text/css">
+</head>
+
+<body>
+
+  <div id="framecontent">
+    <div class="innertube">
+
+<!--  - - - - - - - -   Table of contents   - - - - - - - -  -->
+<div class="toc-tree">
+<ul>
+<li><label class="leaf"><a href="#section1">Introduction to APP4MC</a></label></li>
+<li><input type="checkbox" id="toc2" /><label for="toc2"><a href="#section2">User Guide</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.1" /><label for="toc2.1"><a href="#section2.1">Introduction</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.1.1">Steps to create a new AMALTHEA model</a></label></li>
+<li><input type="checkbox" id="toc2.1.2" /><label for="toc2.1.2"><a href="#section2.1.2">AMALTHEA Editor</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.1.2.1">Show types of model elements</a></label></li>
+<li><label class="leaf"><a href="#section2.1.2.2">Search for model elements</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.1.3">AMALTHEA Examples</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2" /><label for="toc2.2"><a href="#section2.2">Concepts</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.2.1" /><label for="toc2.2.1"><a href="#section2.2.1">Hardware</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.1.1">Structural Modeling of Heterogeneous Platforms</a></label></li>
+<li><label class="leaf"><a href="#section2.2.1.2">Recipe and Feature concept: An outlook of an upcoming approach</a></label></li>
+<li><label class="leaf"><a href="#section2.2.1.3">General Hardware Model Overview</a></label></li>
+<li><label class="leaf"><a href="#section2.2.1.4">Current implementation with features and the connection to the SW Model</a></label></li>
+<li><label class="leaf"><a href="#section2.2.1.5">Interpretation of latencies in the model</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2.2" /><label for="toc2.2.2"><a href="#section2.2.2">Software (development)</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.2.1">Runnables</a></label></li>
+<li><label class="leaf"><a href="#section2.2.2.2">Process Prototypes</a></label></li>
+<li><label class="leaf"><a href="#section2.2.2.3">Constraints</a></label></li>
+<li><label class="leaf"><a href="#section2.2.2.4">Activations</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2.3" /><label for="toc2.2.3"><a href="#section2.2.3">Software (runtime)</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.2.3.1" /><label for="toc2.2.3.1"><a href="#section2.2.3.1">Processes (Tasks or ISRs)</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.3.1.1">Runnables</a></label></li>
+<li><label class="leaf"><a href="#section2.2.3.1.2">Labels</a></label></li>
+<li><label class="leaf"><a href="#section2.2.3.1.3">Semaphore</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.2.3.2">Stimulation</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2.4" /><label for="toc2.2.4"><a href="#section2.2.4">General Concepts</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.4.1">Grouping of elements (Tags, Tag groups)</a></label></li>
+<li><label class="leaf"><a href="#section2.2.4.2">Custom Properties</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2.5" /><label for="toc2.2.5"><a href="#section2.2.5">Scheduling</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.5.1">Scheduler to Core assignment</a></label></li>
+<li><label class="leaf"><a href="#section2.2.5.2">Task to Scheduler assignment</a></label></li>
+<li><label class="leaf"><a href="#section2.2.5.3">Scheduler hierarchies</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2.6" /><label for="toc2.2.6"><a href="#section2.2.6">Communication via channels</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.6.1">Channel</a></label></li>
+<li><input type="checkbox" id="toc2.2.6.2" /><label for="toc2.2.6.2"><a href="#section2.2.6.2">Channel Access</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.6.2.1">Sending</a></label></li>
+<li><label class="leaf"><a href="#section2.2.6.2.2">Receiving</a></label></li>
+<li><label class="leaf"><a href="#section2.2.6.2.3">Common Read Policies: Last, New, and AllNew</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.2.6.3">Transmission Policy</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.2.7" /><label for="toc2.2.7"><a href="#section2.2.7">Memory Sections</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.2.7.1">Virtual Memory Section</a></label></li>
+<li><label class="leaf"><a href="#section2.2.7.2">Physical Memory Section</a></label></li>
+<li><label class="leaf"><a href="#section2.2.7.3">Modeling Memory Section information in AMALTHEA</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.3" /><label for="toc2.3"><a href="#section2.3">Examples</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.3.1" /><label for="toc2.3.1"><a href="#section2.3.1">Modeling Example 1</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.1.1">General information</a></label></li>
+<li><label class="leaf"><a href="#section2.3.1.2">Hardware Model</a></label></li>
+<li><label class="leaf"><a href="#section2.3.1.3">Operating System Model</a></label></li>
+<li><input type="checkbox" id="toc2.3.1.4" /><label for="toc2.3.1.4"><a href="#section2.3.1.4">Mapping Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.1.4.1">Executable Allocation</a></label></li>
+<li><label class="leaf"><a href="#section2.3.1.4.2">Core Allocation</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.3.1.5" /><label for="toc2.3.1.5"><a href="#section2.3.1.5">Software Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.1.5.1">Tasks</a></label></li>
+<li><label class="leaf"><a href="#section2.3.1.5.2">Runnables</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.3.1.6">Stimuli Model</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.3.2" /><label for="toc2.3.2"><a href="#section2.3.2">Modeling Example 2</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.2.1">General information</a></label></li>
+<li><label class="leaf"><a href="#section2.3.2.2">Hardware Model</a></label></li>
+<li><label class="leaf"><a href="#section2.3.2.3">Operating System Model</a></label></li>
+<li><input type="checkbox" id="toc2.3.2.4" /><label for="toc2.3.2.4"><a href="#section2.3.2.4">Mapping Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.2.4.1">Executable Allocation</a></label></li>
+<li><label class="leaf"><a href="#section2.3.2.4.2">Core Allocation</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.3.2.5" /><label for="toc2.3.2.5"><a href="#section2.3.2.5">Software Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.2.5.1">Tasks</a></label></li>
+<li><label class="leaf"><a href="#section2.3.2.5.2">Runnables</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.3.2.6">Stimulation Model</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.3.3">Modeling Example "Purely Periodic without Communication"</a></label></li>
+<li><label class="leaf"><a href="#section2.3.4">Modeling Example "Client-Server without Reply"</a></label></li>
+<li><label class="leaf"><a href="#section2.3.5">Modeling Example "State Machine"</a></label></li>
+<li><label class="leaf"><a href="#section2.3.6">Modeling Example "Feedback Loop"</a></label></li>
+<li><label class="leaf"><a href="#section2.3.7">Modeling Example "State Machine Feedback Loop"</a></label></li>
+<li><input type="checkbox" id="toc2.3.8" /><label for="toc2.3.8"><a href="#section2.3.8">Modeling Examples "Scheduler"</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.8.1">Hierarchical Scheduler</a></label></li>
+<li><label class="leaf"><a href="#section2.3.8.2">Partitioned_FPP Scheduler</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.3.9" /><label for="toc2.3.9"><a href="#section2.3.9">Democar Example</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.3.9.1">Origin</a></label></li>
+<li><label class="leaf"><a href="#section2.3.9.2">Files</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.3.10">HwModel Example</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.4" /><label for="toc2.4"><a href="#section2.4">Tutorials</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.4.1">Task creation example</a></label></li>
+<li><label class="leaf"><a href="#section2.4.2">Mapping example 1</a></label></li>
+<li><label class="leaf"><a href="#section2.4.3">Mapping example 2</a></label></li>
+<li><label class="leaf"><a href="#section2.4.4">Task Visualizer Example</a></label></li>
+<li><label class="leaf"><a href="#section2.4.5">AMALTHEA Trace Database (ATDB) Import Example</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.5" /><label for="toc2.5"><a href="#section2.5">Editors / Viewers</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.5.1">AMALTHEA Trace Database Metrics Viewer</a></label></li>
+<li><input type="checkbox" id="toc2.5.2" /><label for="toc2.5.2"><a href="#section2.5.2">Sirius Viewer</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.5.2.1">Activate capabilities for project</a></label></li>
+<li><input type="checkbox" id="toc2.5.2.2" /><label for="toc2.5.2.2"><a href="#section2.5.2.2">Available Diagrams</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.5.2.2.1" /><label for="toc2.5.2.2.1"><a href="#section2.5.2.2.1">Task View</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.5.2.2.1.1">Communication Layer</a></label></li>
+<li><label class="leaf"><a href="#section2.5.2.2.1.2">Label Layer</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.5.2.2.2">Label View</a></label></li>
+<li><label class="leaf"><a href="#section2.5.2.2.3">EventChain View</a></label></li>
+<li><label class="leaf"><a href="#section2.5.2.2.4">Tasks View</a></label></li>
+<li><label class="leaf"><a href="#section2.5.2.2.5">Mapping View</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.6" /><label for="toc2.6"><a href="#section2.6">Model Validation</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.6.1">Usage of Check-based Validation</a></label></li>
+<li><input type="checkbox" id="toc2.6.2" /><label for="toc2.6.2"><a href="#section2.6.2">Available Validations</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.6.2.1">Basic Check Validator</a></label></li>
+<li><label class="leaf"><a href="#section2.6.2.2">ConstraintsModel Check Validator</a></label></li>
+<li><label class="leaf"><a href="#section2.6.2.3">MappingModel Check Validator</a></label></li>
+<li><label class="leaf"><a href="#section2.6.2.4">EventModel Check Validator</a></label></li>
+<li><label class="leaf"><a href="#section2.6.2.5">HardwareModel Check Validator</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.7" /><label for="toc2.7"><a href="#section2.7">Model Migration</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.7.1" /><label for="toc2.7.1"><a href="#section2.7.1">AMALTHEA Model Migration</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.7.1.1">Why model migration is required ?</a></label></li>
+<li><label class="leaf"><a href="#section2.7.1.2">AMALTHEA model migration</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.7.2">Supported versions for model Migration</a></label></li>
+<li><input type="checkbox" id="toc2.7.3" /><label for="toc2.7.3"><a href="#section2.7.3">Pre-requisites for AMALTHEA model migration</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.7.3.1">VM arguments</a></label></li>
+<li><label class="leaf"><a href="#section2.7.3.2">Linked files in eclipse project (virtual files)</a></label></li>
+<li><input type="checkbox" id="toc2.7.3.3" /><label for="toc2.7.3.3"><a href="#section2.7.3.3">Usage of UUID's instead of URI fragments inside AMALTHEA models</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.7.3.3.1">How to identify if Xpath like URI fragments are used in AMALTHEA model files</a></label></li>
+<li><label class="leaf"><a href="#section2.7.3.3.2">How to identify if UUID's are used in AMALTHEA model files</a></label></li>
+<li><label class="leaf"><a href="#section2.7.3.3.3">Update AMALTHEA models to use UUID's instead of Xpath like URI fragments</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.7.4">How to invoke AMALTHEA model migration</a></label></li>
+<li><label class="leaf"><a href="#section2.7.5">Additional details</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.8" /><label for="toc2.8"><a href="#section2.8">Partitioning</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.8.1">Usage of Partitioning</a></label></li>
+<li><input type="checkbox" id="toc2.8.2" /><label for="toc2.8.2"><a href="#section2.8.2">Pre-Partitioning</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.8.2.1">Label Access Analysis</a></label></li>
+<li><label class="leaf"><a href="#section2.8.2.2">Cycle Elimination</a></label></li>
+<li><label class="leaf"><a href="#section2.8.2.3">Activation Partitioning</a></label></li>
+<li><label class="leaf"><a href="#section2.8.2.4">Independent Graph Partitioning</a></label></li>
+<li><label class="leaf"><a href="#section2.8.2.5">Tag Partitioning</a></label></li>
+<li><label class="leaf"><a href="#section2.8.2.6">ASIL-level Partitioning</a></label></li>
+<li><label class="leaf"><a href="#section2.8.2.7">Consideration of Runnable Pairing Constraints</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.8.3" /><label for="toc2.8.3"><a href="#section2.8.3">Partitioning Algorithms</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.8.3.1">Critical Path Partitioning (CPP)</a></label></li>
+<li><label class="leaf"><a href="#section2.8.3.2">Earliest Start Schedule Partitioning (ESSP)</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.8.4" /><label for="toc2.8.4"><a href="#section2.8.4">Further Features</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.8.4.1">Applet Generation</a></label></li>
+<li><label class="leaf"><a href="#section2.8.4.2">Dependency Alternative</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.8.5" /><label for="toc2.8.5"><a href="#section2.8.5">Partitioning Examples</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.8.5.1">Algorithm Comparison</a></label></li>
+<li><label class="leaf"><a href="#section2.8.5.2">Workflow Example</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.8.6">Plugin dependencies</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.9" /><label for="toc2.9"><a href="#section2.9">Mapping</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.9.1">Concept</a></label></li>
+<li><input type="checkbox" id="toc2.9.2" /><label for="toc2.9.2"><a href="#section2.9.2">Implementation</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.9.2.1">Task generation</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.2">Mapping Strategy 1: Heuristic DFG load balancing</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.3">Mapping Strategy 2: ILP based load balancing</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.4">Mapping Strategy 3: Minimizing Energy Consumption</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.5">Configuration and Preferences</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.6">Enabling verbose logging</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.7">Specifying the output location</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.8">Selecting a mapping algorithm</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.9">Configuring Mathematical Solver</a></label></li>
+<li><label class="leaf"><a href="#section2.9.2.10">Generating a mapping</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.10" /><label for="toc2.10"><a href="#section2.10">Model Checker</a></label>
+<ul>
+<li><input type="checkbox" id="toc2.10.1" /><label for="toc2.10.1"><a href="#section2.10.1">Model Description</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.10.1.1">Model Specifications</a></label></li>
+<li><label class="leaf"><a href="#section2.10.1.2">Specifications Severity</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.10.2">Solving Model Checker issues</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc2.11" /><label for="toc2.11"><a href="#section2.11">Multicore Wizard</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.11.1">Flow Configuration</a></label></li>
+<li><label class="leaf"><a href="#section2.11.2">Partitioning Configuration</a></label></li>
+<li><input type="checkbox" id="toc2.11.3" /><label for="toc2.11.3"><a href="#section2.11.3">Mapping Configuration</a></label>
+<ul>
+<li><label class="leaf"><a href="#section2.11.3.1">ILP-based mapping</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section2.11.4">Summary</a></label></li>
+<li><label class="leaf"><a href="#section2.11.5">Finish</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3" /><label for="toc3"><a href="#section3">Data Models</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.1" /><label for="toc3.1"><a href="#section3.1">Data Model Overview</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.1.1">AMALTHEA System Model</a></label></li>
+<li><label class="leaf"><a href="#section3.1.2">AMALTHEA Trace Model</a></label></li>
+<li><label class="leaf"><a href="#section3.1.3">Structure of the model</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.2" /><label for="toc3.2"><a href="#section3.2">Common Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.2.1">Common Elements</a></label></li>
+<li><label class="leaf"><a href="#section3.2.2">Tags</a></label></li>
+<li><label class="leaf"><a href="#section3.2.3">Classifiers</a></label></li>
+<li><label class="leaf"><a href="#section3.2.4">Custom Properties</a></label></li>
+<li><label class="leaf"><a href="#section3.2.5">Time (and Time Unit)</a></label></li>
+<li><label class="leaf"><a href="#section3.2.6">Frequency (and Frequency Unit)</a></label></li>
+<li><label class="leaf"><a href="#section3.2.7">Data Size (and Data Size Unit)</a></label></li>
+<li><label class="leaf"><a href="#section3.2.8">Data Rate (and Data Rate Unit)</a></label></li>
+<li><input type="checkbox" id="toc3.2.9" /><label for="toc3.2.9"><a href="#section3.2.9">Deviation</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.2.9.1">Boundaries</a></label></li>
+<li><label class="leaf"><a href="#section3.2.9.2">Uniform Distribution</a></label></li>
+<li><label class="leaf"><a href="#section3.2.9.3">Gaussian/Normal Distribution</a></label></li>
+<li><label class="leaf"><a href="#section3.2.9.4">Beta Distribution</a></label></li>
+<li><label class="leaf"><a href="#section3.2.9.5">Weibull Distribution</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.2.10">Statistic Elements</a></label></li>
+<li><label class="leaf"><a href="#section3.2.11">Instructions</a></label></li>
+<li><label class="leaf"><a href="#section3.2.12">Needs</a></label></li>
+<li><label class="leaf"><a href="#section3.2.13">Counters</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.3" /><label for="toc3.3"><a href="#section3.3">Components Model</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.3.1" /><label for="toc3.3.1"><a href="#section3.3.1">Components Model Elements</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.3.1.1">Component</a></label></li>
+<li><label class="leaf"><a href="#section3.3.1.2">System and Composite</a></label></li>
+<li><label class="leaf"><a href="#section3.3.1.3">ComponentInstance and Connector</a></label></li>
+<li><label class="leaf"><a href="#section3.3.1.4">QualifiedPort</a></label></li>
+<li><label class="leaf"><a href="#section3.3.1.5">InterfacePort</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.3.2" /><label for="toc3.3.2"><a href="#section3.3.2">Example</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.3.2.1">Diagram</a></label></li>
+<li><label class="leaf"><a href="#section3.3.2.2">Model Editor</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.3.3">Franca IDL</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.4" /><label for="toc3.4"><a href="#section3.4">Configuration Model</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.4.1" /><label for="toc3.4.1"><a href="#section3.4.1">Event Configuration</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.4.1.1">Sample</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.5" /><label for="toc3.5"><a href="#section3.5">Constraints Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.5.1">Requirements</a></label></li>
+<li><label class="leaf"><a href="#section3.5.2">Runnable Sequencing Constraints</a></label></li>
+<li><label class="leaf"><a href="#section3.5.3">Data Age Constraints</a></label></li>
+<li><label class="leaf"><a href="#section3.5.4">Data Coherency Groups</a></label></li>
+<li><label class="leaf"><a href="#section3.5.5">Data Stability Groups</a></label></li>
+<li><label class="leaf"><a href="#section3.5.6">Event Chains</a></label></li>
+<li><input type="checkbox" id="toc3.5.7" /><label for="toc3.5.7"><a href="#section3.5.7">Timing Constraints</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.5.7.1">Synchronization Constraints</a></label></li>
+<li><label class="leaf"><a href="#section3.5.7.2">Repetition Constraint</a></label></li>
+<li><label class="leaf"><a href="#section3.5.7.3">Delay Constraint</a></label></li>
+<li><label class="leaf"><a href="#section3.5.7.4">Event Chain Latency Constraint</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.5.8" /><label for="toc3.5.8"><a href="#section3.5.8">Affinity Constraints</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.5.8.1">Data Affinity Constraints</a></label></li>
+<li><label class="leaf"><a href="#section3.5.8.2">Process Affinity Constraints</a></label></li>
+<li><label class="leaf"><a href="#section3.5.8.3">Runnable Affinity Constraints</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.5.9">Physical Section Constraints</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.6">Event Model</a></label></li>
+<li><input type="checkbox" id="toc3.7" /><label for="toc3.7"><a href="#section3.7">Hardware Model</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.7.1" /><label for="toc3.7.1"><a href="#section3.7.1">Class Diagrams</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.1.1">Hardware model elements</a></label></li>
+<li><label class="leaf"><a href="#section3.7.1.2">Hardware definitions and features</a></label></li>
+<li><label class="leaf"><a href="#section3.7.1.3">Hardware modules and access elements</a></label></li>
+<li><label class="leaf"><a href="#section3.7.1.4">Hardware paths and destinations</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.7.2" /><label for="toc3.7.2"><a href="#section3.7.2">Element description</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.2.1">HwModel</a></label></li>
+<li><input type="checkbox" id="toc3.7.2.2" /><label for="toc3.7.2.2"><a href="#section3.7.2.2">HwDefinition</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.2.2.1">ProcessingUnitDefinition</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.2.2">MemoryDefinition</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.2.3">CacheDefinition</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.2.4">ConnectionHandlerDefinition</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.7.2.3">HwStructure</a></label></li>
+<li><input type="checkbox" id="toc3.7.2.4" /><label for="toc3.7.2.4"><a href="#section3.7.2.4">HwDomain</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.2.4.1">FrequencyDomain</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.4.2">PowerDomain</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.7.2.5" /><label for="toc3.7.2.5"><a href="#section3.7.2.5">HwFeature</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.2.5.1">HwFeatureCategory</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.7.2.6" /><label for="toc3.7.2.6"><a href="#section3.7.2.6">HwModule</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.2.6.1">ProcessingUnit</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.6.2">Memory</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.6.3">Cache</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.6.4">ConnectionHandler</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.7.2.7">HwAccessElement</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.8">HwPort</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.9">HwConnection</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.10">HwAccessPath</a></label></li>
+<li><input type="checkbox" id="toc3.7.2.11" /><label for="toc3.7.2.11"><a href="#section3.7.2.11">HwLatency</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.7.2.11.1">LatencyConstant</a></label></li>
+<li><label class="leaf"><a href="#section3.7.2.11.2">LatencyDeviation</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.7.2.12">Enumerations</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.7.3">Additional Documents</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.8" /><label for="toc3.8"><a href="#section3.8">Mapping Model</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.8.1" /><label for="toc3.8.1"><a href="#section3.8.1">Overview</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.8.1.1">MappingModel</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.8.2" /><label for="toc3.8.2"><a href="#section3.8.2">Allocations</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.8.2.1">SchedulerAllocation</a></label></li>
+<li><label class="leaf"><a href="#section3.8.2.2">RunnableAllocation</a></label></li>
+<li><label class="leaf"><a href="#section3.8.2.3">TaskAllocation</a></label></li>
+<li><label class="leaf"><a href="#section3.8.2.4">ISRAllocation</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.8.3" /><label for="toc3.8.3"><a href="#section3.8.3">Mappings</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.8.3.1">MemoryMapping</a></label></li>
+<li><label class="leaf"><a href="#section3.8.3.2">PhysicalSectionMapping</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.9">Measurement Model</a></label></li>
+<li><input type="checkbox" id="toc3.10" /><label for="toc3.10"><a href="#section3.10">OS Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.10.1">Operating System</a></label></li>
+<li><input type="checkbox" id="toc3.10.2" /><label for="toc3.10.2"><a href="#section3.10.2">Scheduler</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.10.2.1" /><label for="toc3.10.2.1"><a href="#section3.10.2.1">Scheduling Algorithm</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.10.2.1.1">Further information</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.10.2.2">Scheduling Parameters</a></label></li>
+<li><label class="leaf"><a href="#section3.10.2.3">Scheduler Association</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.10.3" /><label for="toc3.10.3"><a href="#section3.10.3">Os Overhead</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.10.3.1">ISR Overhead</a></label></li>
+<li><label class="leaf"><a href="#section3.10.3.2">API Overhead</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.10.4">OS Data Consistency</a></label></li>
+<li><label class="leaf"><a href="#section3.10.5">Semaphore</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.11" /><label for="toc3.11"><a href="#section3.11">PropertyConstraints Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.11.1">Structure</a></label></li>
+<li><input type="checkbox" id="toc3.11.2" /><label for="toc3.11.2"><a href="#section3.11.2">CoreAllocationConstraint</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.11.2.1">RunnableAllocationConstraint</a></label></li>
+<li><label class="leaf"><a href="#section3.11.2.2">ProcessAllocationConstraint</a></label></li>
+<li><label class="leaf"><a href="#section3.11.2.3">ProcessPrototypeAllocationConstraint</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.11.3" /><label for="toc3.11.3"><a href="#section3.11.3">MemoryMappingConstraint</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.11.3.1">AbstractElementMappingConstraint</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.11.4">Classifications</a></label></li>
+<li><label class="leaf"><a href="#section3.11.5">Example</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.12" /><label for="toc3.12"><a href="#section3.12">Stimuli Model</a></label>
+<ul>
+<li><input type="checkbox" id="toc3.12.1" /><label for="toc3.12.1"><a href="#section3.12.1">Stimuli</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.12.1.1">Single</a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.2">Arrival Curves</a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.3">FixedPeriodic</a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.4">Periodic </a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.5">PeriodicSynthetic</a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.6">PeriodicBurst</a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.7">RelativePeriodic </a></label></li>
+<li><label class="leaf"><a href="#section3.12.1.8">VariableRateStimulus</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.12.2">Clocks</a></label></li>
+<li><label class="leaf"><a href="#section3.12.3">Mode label lists</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.13" /><label for="toc3.13"><a href="#section3.13">Software Model</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.13.1">Memory Information</a></label></li>
+<li><label class="leaf"><a href="#section3.13.2">Labels</a></label></li>
+<li><label class="leaf"><a href="#section3.13.3">Channels</a></label></li>
+<li><input type="checkbox" id="toc3.13.4" /><label for="toc3.13.4"><a href="#section3.13.4">Data Types</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.13.4.1">General Information</a></label></li>
+<li><label class="leaf"><a href="#section3.13.4.2">Sample</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.13.5">Activations</a></label></li>
+<li><label class="leaf"><a href="#section3.13.6">Runnables and Services</a></label></li>
+<li><label class="leaf"><a href="#section3.13.7">Runnables</a></label></li>
+<li><input type="checkbox" id="toc3.13.8" /><label for="toc3.13.8"><a href="#section3.13.8">Runnable Items</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.13.8.1">Groups</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.2">Calls and AUTOSAR communication</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.3">Label Access</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.4">Channel Access</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.5">Semaphore Access</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.6">Mode Label Access</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.7">Custom Event Trigger</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.8">Runnable Mode Switch</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.9">Runnable Probability Switch</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.10">Execution Need</a></label></li>
+<li><label class="leaf"><a href="#section3.13.8.11">Statistical Values</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.13.9">Tasks / ISR</a></label></li>
+<li><input type="checkbox" id="toc3.13.10" /><label for="toc3.13.10"><a href="#section3.13.10">The Call Graph</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.13.10.1">Mode Switch</a></label></li>
+<li><label class="leaf"><a href="#section3.13.10.2">Probability Switch</a></label></li>
+<li><label class="leaf"><a href="#section3.13.10.3">Call Sequence</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.13.11" /><label for="toc3.13.11"><a href="#section3.13.11">Call Sequence Content</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.13.11.1">Task Runnable Call</a></label></li>
+<li><label class="leaf"><a href="#section3.13.11.2">Enforced Migration</a></label></li>
+<li><label class="leaf"><a href="#section3.13.11.3">Inter Process Trigger</a></label></li>
+<li><label class="leaf"><a href="#section3.13.11.4">Schedule Point</a></label></li>
+<li><label class="leaf"><a href="#section3.13.11.5">Terminate Process</a></label></li>
+<li><label class="leaf"><a href="#section3.13.11.6">Wait/Clear/Set Event</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc3.13.12" /><label for="toc3.13.12"><a href="#section3.13.12">Modes</a></label>
+<ul>
+<li><label class="leaf"><a href="#section3.13.12.1">Modes and Mode Labels</a></label></li>
+<li><label class="leaf"><a href="#section3.13.12.2">Mode Changes</a></label></li>
+<li><label class="leaf"><a href="#section3.13.12.3">Mode Conditions</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section3.13.13">Process Prototypes</a></label></li>
+<li><label class="leaf"><a href="#section3.13.14">Process Chains</a></label></li>
+<li><label class="leaf"><a href="#section3.13.15">Custom Entities</a></label></li>
+<li><label class="leaf"><a href="#section3.13.16">Section</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4" /><label for="toc4"><a href="#section4">Developer Guide</a></label>
+<ul>
+<li><input type="checkbox" id="toc4.1" /><label for="toc4.1"><a href="#section4.1">Overview of Features and Plug-ins</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.1.1">Features</a></label></li>
+<li><label class="leaf"><a href="#section4.1.2">Plug-ins</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.2" /><label for="toc4.2"><a href="#section4.2">Model Validation</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.2.1">Understanding Check Catalogs</a></label></li>
+<li><label class="leaf"><a href="#section4.2.2">Adding own Validations</a></label></li>
+<li><input type="checkbox" id="toc4.2.3" /><label for="toc4.2.3"><a href="#section4.2.3">Plugin dependencies</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.2.3.1">Implementation</a></label></li>
+<li><label class="leaf"><a href="#section4.2.3.2">Plugin configuration</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.3" /><label for="toc4.3"><a href="#section4.3">Model Workflow</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.3.1">Introduction</a></label></li>
+<li><label class="leaf"><a href="#section4.3.2">General Structure</a></label></li>
+<li><input type="checkbox" id="toc4.3.3" /><label for="toc4.3.3"><a href="#section4.3.3">Available Basic Components</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.3.3.1">Model Reader</a></label></li>
+<li><label class="leaf"><a href="#section4.3.3.2">Model Writer</a></label></li>
+<li><label class="leaf"><a href="#section4.3.3.3">Add Schedule Points</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.3.4" /><label for="toc4.3.4"><a href="#section4.3.4">Other Components</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.3.4.1">Create Tasks</a></label></li>
+<li><label class="leaf"><a href="#section4.3.4.2">Generate Mapping</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.3.5" /><label for="toc4.3.5"><a href="#section4.3.5">EASE modules</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.3.5.1">Workflow Module</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.3.6" /><label for="toc4.3.6"><a href="#section4.3.6">MWE2 Workflow</a></label>
+<ul>
+<li><input type="checkbox" id="toc4.3.6.1" /><label for="toc4.3.6.1"><a href="#section4.3.6.1">MWE2 Components</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.3.6.1.1">Reader</a></label></li>
+<li><label class="leaf"><a href="#section4.3.6.1.2">Writer</a></label></li>
+<li><label class="leaf"><a href="#section4.3.6.1.3">Add Schedule Points</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section4.3.7">Current Limitations / Open Points</a></label></li>
+<li><label class="leaf"><a href="#section4.3.8">Overall Sample</a></label></li>
+<li><label class="leaf"><a href="#section4.3.9">Adding a new workflow component</a></label></li>
+<li><input type="checkbox" id="toc4.3.10" /><label for="toc4.3.10"><a href="#section4.3.10">Create project</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.3.10.1">Execute the new component in the available sample</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.4" /><label for="toc4.4"><a href="#section4.4">Model Migration</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.4.1">Technologies used</a></label></li>
+<li><label class="leaf"><a href="#section4.4.2">Framework for model migration</a></label></li>
+<li><input type="checkbox" id="toc4.4.3" /><label for="toc4.4.3"><a href="#section4.4.3">Components of Model Migration Framework</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.4.3.1">Model migration sequence</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section4.4.4">How to add custom Model Migration components</a></label></li>
+<li><input type="checkbox" id="toc4.4.5" /><label for="toc4.4.5"><a href="#section4.4.5">AMALTHEA meta model changes</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.4.5.1">Version ITEA 1.0.3 to ITEA 1.1.0</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.2">Version ITEA 1.1.0 to ITEA 1.1.1</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.3">Version ITEA 1.1.1 to App4MC 0.7.0</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.4">Version APP4MC 0.7.0 to App4MC 0.7.1</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.5">Version APP4MC 0.7.1 to APP4MC 0.7.2</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.6">Version APP4MC 0.7.2 to APP4MC 0.8.0</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.7">Version APP4MC 0.8.0 to APP4MC 0.8.1</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.8">Version APP4MC 0.8.1 to APP4MC 0.8.2</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.9">Version APP4MC 0.8.2 to APP4MC 0.8.3</a></label></li>
+<li><label class="leaf"><a href="#section4.4.5.10">Version APP4MC 0.8.3 to APP4MC 0.9.0</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.5" /><label for="toc4.5"><a href="#section4.5">Model Utilities</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.5.1">Overview</a></label></li>
+<li><input type="checkbox" id="toc4.5.2" /><label for="toc4.5.2"><a href="#section4.5.2">General Helper Classes</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.5.2.1">How to use util API of these classes</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section4.5.3">Common Utilities</a></label></li>
+<li><label class="leaf"><a href="#section4.5.4">Software Utilities</a></label></li>
+<li><label class="leaf"><a href="#section4.5.5">Runtime Utilities</a></label></li>
+<li><label class="leaf"><a href="#section4.5.6">Deployment Utilities</a></label></li>
+<li><label class="leaf"><a href="#section4.5.7">Hardware Utilities</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc4.6" /><label for="toc4.6"><a href="#section4.6">Model Details</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.6.1">Unique ID generation</a></label></li>
+<li><label class="leaf"><a href="#section4.6.2">Interfaces and base objects</a></label></li>
+<li><input type="checkbox" id="toc4.6.3" /><label for="toc4.6.3"><a href="#section4.6.3">Transient back pointers</a></label>
+<ul>
+<li><label class="leaf"><a href="#section4.6.3.1">Current back pointers</a></label></li>
+<li><label class="leaf"><a href="#section4.6.3.2">Implementation</a></label></li>
+<li><label class="leaf"><a href="#section4.6.3.3">User Interface</a></label></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section4.7">AMALTHEA Model XSD Schema</a></label></li>
+</ul>
+</li>
+<li><input type="checkbox" id="toc5" /><label for="toc5"><a href="#section5">Release Notes</a></label>
+<ul>
+<li><label class="leaf"><a href="#section5.1">Eclipse APP4MC 0.9.0 (Apr 2018)</a></label></li>
+<li><label class="leaf"><a href="#section5.2">Eclipse APP4MC 0.8.3 (Jan 2018)</a></label></li>
+<li><label class="leaf"><a href="#section5.3">Eclipse APP4MC 0.8.2 (Oct 2017)</a></label></li>
+<li><label class="leaf"><a href="#section5.4">Eclipse APP4MC 0.8.1 (Jul 2017)</a></label></li>
+<li><label class="leaf"><a href="#section5.5">Eclipse APP4MC 0.8.0 (Apr 2017)</a></label></li>
+<li><label class="leaf"><a href="#section5.6">Eclipse APP4MC 0.7.2 (Jan 2017)</a></label></li>
+<li><label class="leaf"><a href="#section5.7">Eclipse APP4MC 0.7.1 (Oct 2016)</a></label></li>
+<li><label class="leaf"><a href="#section5.8">Eclipse APP4MC 0.7.0 (Jul 2016)</a></label></li>
+<li><label class="leaf"><a href="#section5.9">AMALTHEA 1.1.1 (Oct 2015)</a></label></li>
+<li><label class="leaf"><a href="#section5.10">AMALTHEA 1.1.0 (Aug 2015)</a></label></li>
+</ul>
+</li>
+<li><label class="leaf"><a href="#section6">Roadmap</a></label></li>
+</ul>
+</div>
+<!--  - - - - - - - -   Table of contents   - - - - - - - -  -->
+
+    </div>
+  </div>
+
+  <div id="maincontent">
+    <div class="innertube">
+
+<!--  - - - - - - - - - -   Articles    - - - - - - - - - -  -->
+<article>
+<h1><a id="section1">1 </a>Introduction to APP4MC</h1>
+		<p>
+			<img src="images/app4mc-logo-g.png"/>
+		</p>
+		<p>The goal of the project is the development of a consistent, open, expandable tool platform for embedded software engineering. It is based on the model driven approach as basic engineering methodology. The main focus is the optimization of embedded multi-core systems.</p>
+		<p>Most functions in a modern car are controlled by embedded systems. Also more and more driver assistance functions are introduced. This implies a continuous increase of computing power accompanied by the request for reduction of energy and costs. To handle these requirements the multi-core technology permeates the control units in cars. This is today one of the biggest challenges for automotive systems. Existing applications can not realize immediate benefit from these multi-core ECUs because they are not designed to run on such architectures. In addition applications and systems have to be migrated into AUTOSAR compatible architectures. Both trends imply the necessity for new development environments which cater for these requirements.</p>
+		<p>The tool platform shall be capable to support all aspects of the development cycle. This addresses predominantly the automotive domain but is also applicable to telecommunication by extensions which deal with such systems in their native environment and integrated in a car.</p>
+		<p>Future extensions will add support for visualization tools, graphical editors. But not only design aspects will be supported but also verification and validation of the systems will be taken into account and support tools for optimal multi-core real-time scheduling and validation of timing requirements will be provided. In the course of this project not all of the above aspects will be addressed in the same depth. Some will be defined and some will be implemented on a prototype basis. But the basis platform and the overall architecture will be finalized as much as possible.</p>
+		<p>The result of the project is an open tool platform in different aspects. On the one hand it is published under the Eclipse Public License (EPL) and on the other hand it is open to be integrated with existing or new tools either on a company individual basis or with commercially available tools.</p>
+</article>
+
+
+<article>
+<h1><a id="section2">2 </a>User Guide</h1>
+
+
+<h2><a id="section2.1">2.1 </a>Introduction</h2>
+		<p>APP4MC comes with a predefined perspective available in the Eclipse menu under Window -&gt; Open Perspective -&gt; Other -&gt; APP4MC. This perspective consists of the following elements:</p>
+		<ul>
+			<li>AMALTHEA Model Explorer</li>
+			<li>Editor
+				<ul>
+					<li>Tree Editor showing the structure of the model content</li>
+					<li>Standard Properties Tab is used to work on elements attributes</li>
+				</ul>
+			</li>
+		</ul>
+		<p>The following screenshot is showing this perspective and its contained elements.</p>
+		<p>
+			<img src="images/user_guide_editor_structure.png"/>
+		</p>
+
+
+<h3><a id="section2.1.1">2.1.1 </a>Steps to create a new AMALTHEA model</h3>
+		<p>APP4MC provides a standard wizard to create a new AMALTHEA model from scratch.</p>
+		<p>
+			<strong>Step 1: Create a new general project</strong>
+		</p>
+		<blockquote>
+			<p>The scope of an AMALTHEA model is defined by its enclosing container (project or folder).
+				<br>      Therefore a project is required.
+			</p>
+			<p>      
+				<img src="images/user_guide_step1_create-project.png"/>
+			</p>
+		</blockquote>
+		<p>
+			<strong>Step 2: Create a new folder inside of the created project</strong>
+		</p>
+		<blockquote>
+			<p>It is recommended to create a folder ( 
+				<i>although a project is also a possible container</i> ).
+			</p>
+			<p>      
+				<img src="images/user_guide_step2_create-folder.png"/>
+			</p>
+		</blockquote>
+		<p>
+			<strong>Step 3: Create a new AMALTHEA model</strong>
+		</p>
+		<blockquote>
+			<p>In the context menu (right mouse button) an entry for a new AMALTHEA model can be found.</p>
+			<p>      
+				<img src="images/user_guide_step3_create-model.png"/>
+			</p>
+			<p>      Another starting point is 
+				<i>File</i> -&gt; 
+				<i>New</i> -&gt; 
+				<i>Other</i>
+			</p>
+			<p>      In the dialog you can select the parent folder and the file name.</p>
+		</blockquote>
+
+
+<h3><a id="section2.1.2">2.1.2 </a>AMALTHEA Editor</h3>
+		<p>The AMALTHEA Editor shows either the entire model that contains sub models or one of the sub models.
+			<br>The next screenshot shows the "New Child" menu with all its possibilities.  
+		</p>
+		<p>
+			<img class="gray" src="images/user_editor_with_central_model.png"/>
+		</p>
+		<p>In addition the AMALTHEA Editor has two commands available at the top right of the Editor.</p>
+		<p>
+			<img class="gray" src="images/user_guide_editor_commands.png"/>
+		</p>
+
+
+<h4><a id="section2.1.2.1"></a>Show types of model elements</h4>
+		<p>The Show types of elements button triggers the editor to show the direct type of the element in the tree editor using [element_type]. The following screenshot shows the toggle and the types marked with an underline.</p>
+		<p>
+			<img class="gray" src="images/user_guide_editor_showtypes.png"/>
+		</p>
+
+
+<h4><a id="section2.1.2.2"></a>Search for model elements</h4>
+		<p>The editor provides the possibility to filter model elements by using the available name attribute. This can be used for example to filter all elements in the model which has abs in their name. The search and result view is using the Eclipse search as result view.</p>
+		<p>
+			<img class="gray" src="images/user_guide_editor_search_input.png"/>
+		</p>
+		<p>The search result is using the Eclipse Search View.</p>
+		<p>
+			<img class="gray" src="images/user_guide_editor_search_result1.png"/>
+		</p>
+		<p>An additional option is to toggle the search results to group them by type as shown in the next screenshot.</p>
+		<p>
+			<img class="gray" src="images/user_guide_editor_search_result2.png"/>
+		</p>
+
+
+<h3><a id="section2.1.3">2.1.3 </a>AMALTHEA Examples</h3>
+		<p>The AMALTHEA tool platform comes with several examples. This section will describe how a new project based on these examples can be created. </p>
+		<p>
+			<strong>Step 1</strong>
+		</p>
+		<blockquote>
+			<p>Click the "new" icon in the top left corner and select "Example..." or use the right mouse button.</p>
+			<p>      
+				<img src="images/01-create-new-example.png"/>
+			</p>
+		</blockquote>
+		<p>
+			<strong>Step 2</strong>
+		</p>
+		<blockquote>
+			<p>The "New Example" wizard will pop up and shows several examples.
+				<br>      Select one examples and hit continue.
+			</p>
+			<p>      
+				<img src="images/02-select-democar-example.png"/>
+			</p>
+		</blockquote>
+		<p>
+			<strong>Step 3</strong>
+		</p>
+		<blockquote>
+			<p>You will see a summary of the example projects that will be created.
+				<br>      Click "Finish" to exit this dialog.
+			</p>
+			<p>      
+				<img src="images/03_democar-example-finish.png"/>
+			</p>
+			<p>      You can now open the editor to inspect the models.</p>
+		</blockquote>
+
+
+<h2><a id="section2.2">2.2 </a>Concepts</h2>
+
+
+<h3><a id="section2.2.1">2.2.1 </a>Hardware</h3>
+
+
+<h4><a id="section2.2.1.1"></a>Structural Modeling of Heterogeneous Platforms</h4>
+		<p>To master the rising demands of performance and power efficiency, hardware becomes more and more diverse with a wide spectrum of different cores and hardware accelerators. On the computation front, there is an emergence of specialized processing units that are designed to boost a specific kind of algorithm, like a cryptographic algorithm, or a specific math operation like "multiply and accumulate". As one result, the benefit of a given function from hardware units specialized in different kinds may lead to nonlinear effects between processing units in terms of execution performance of the algorithm: while one function may be processed twice as fast when changing the processing unit, another function may have no benefit at all from the same change. Furthermore the memory hierarchy in modern embedded microprocessor architectures becomes more complex due to multiple levels of caches, cache coherency support, and the extended use of DRAM. In addition to crossbars, modern SoCs connect different clusters of potentially different hardware components via a Network on Chip. Additionally, power and frequency scaling is supported by state of the art SoCs. All these characteristics of modern and performant SoCs (specialized processing units, complex memory hierarchy, network like interconnects and power and frequency scaling) were only partially supported by the former Amalthea hardware model. Therefore, to create models of modern heterogeneous systems, new concepts of representing hardware components in a flexible and easy way are necessary: Our approach supports modeling of manifold hierarchical structures and also domains for power and frequencies. Furthermore, explicit cache modules are available and the possibilities for modeling the whole memory subsystem are extended, the connection between hardware components can be modeled over different abstraction layers. Only with such an extended modeling approach, a more accurate estimation of the system performance of state of the art SoCs becomes feasible.</p>
+		<p>Our intention is allowing to create a hardware model once at the beginning of a development process. Ideally, the hardware model will be provided by the vendor. All performance relevant attributes regarding the different features of hardware components like a floating point unit or how hardware components are interconnected should be explicitly represented in the model. The main challenge for a hardware/software performance model is then to determine certain costs, e.g. the net execution time of a software functionality mapped to a processing unit. Costs such as execution time, in contrast to the hardware structure, may change during development time – either because the implementation details evolve from initial guess to real-world measurements, the implementation is changed, or the tooling is changed. Therefore, the inherent attributes of the hardware, e.g. latency of an access path, should be decoupled from the mapping or implementation dependent costs of executing functions. We know from experience that it is necessary to refine these costs constantly in the development process to increase accuracy of performance estimation. Refinement denotes incorporation of increasing knowledge about the system. Therefore, such a refinement should be possible in an efficient way and also support re-use of the hardware model. The corresponding concepts are detailed in the following section.</p>
+
+
+<h4><a id="section2.2.1.2"></a>Recipe and Feature concept: An outlook of an upcoming approach</h4>
+		<p>
+			<em>Disclaimer: Please note that the following describes work in progress – what we call "recipes" later is not yet part of the meta-model, and the concept of "features" is not final.</em>
+		</p>
+		<p>The main driver of the concept described here is separation of implementation dependent details from structural or somehow "solid" information about a hardware/software system. This follows the separation of concerns paradigm, mainly to reduce refinement effort, and foster model re-use: As knowledge about a system grows during development, e.g. by implementing or optimizing functionality as software, the system model should be updated and refined efficiently, while inherent details shall be kept constant and not modified depending on the implementation.</p>
+		<p>An example should clarify this approach: For timing simulation, we require the net execution time of a software function executed on the processing unit it is mapped onto. This cost of the execution depends on the implementation of the algorithm, for instance, as C++ code, and the tool chain producing the binary code that eventually is executed. In that sense, the 
+			<strong>execution needs</strong> of the algorithm (for instance, a certain number of "multiply and accumulate" operations for a matrix operation) are naturally fixed, as well as the 
+			<strong>features</strong> provided by the processing unit (for instance, a dedicated MAC unit requiring one tick for one operation, and a generic integer unit requiring 0.5 ticks per operation). However is implementation- and tool-chain-dependent how the actual execution needs of the algorithm are served by the execution units. Without changing the algorithm or the hardware, optimization of the implementation may make better use of the hardware, resulting in reduced execution time. The above naturally draws the lines for our modeling approach: Execution needs (on an algorithmic level) are inherent, as well as features of the hardware. Keeping these information constant in the model is the key for re-use; implementation dependent change of costs, such as lower execution time by an optimized implementation in C++ or better compiler options, change during development and are modeled as 
+			<strong>recipe</strong>. A "recipe" thus takes execution needs of software and features of the hardware as input and results in costs, such as the net execution time. Consequently, recipes are the main area of model refinement during development. The concept is illustrated below.
+		</p>
+		<p>
+			<img class="scale" src="images/user_recipe_concept.png"/>
+		</p>
+		<p>Note that flexibility is part of the design of this approach. Execution needs and features are not limited to a given set, and recipes can be almost arbitrary prescripts of computation. This allows to introduce new execution needs when required to favorable detail an algorithm. For instance, the execution need "convolution-VGG16" can be introduced to model a specific need for a deep learning algorithm. The feature "MAC" of the executing processing unit provides costs in ticks corresponding to perform a MAC operation. The recipe valid for the mapping then uses these two attributes to compute the net execution time of "convolution-VGG16" in ticks, for instance, by multiplying the costs of xyz MAC operations with a penalty factor of 0.8. Note that with this approach execution needs may be translated very differently into costs, using different features.</p>
+		<p>To further motivate this approach, we give some more benefits and examples of beneficial use of the model:</p>
+		<ul>
+			<li>Given execution needs of a software function that directly correspond the features of processing units, the optimal execution time may be computed (peak performance).</li>
+			<li>While net execution time is the prime example of execution needs, features, and recipes, the concept is not limited to "net execution time recipes", recipes for other performance numbers such as power consumption are possible.</li>
+			<li>Recipes can be attached at different "levels" in the model: At a processing unit and at a mapping. If present, the recipe at mapping level has precedence.</li>
+		</ul>
+
+
+<h4><a id="section2.2.1.3"></a>General Hardware Model Overview</h4>
+		<p>The design of the new hardware model is focusing on flexibility and variety to cover different kind of designs to cope with future extensions, and also to support different levels of abstraction. To reduce the complexity of the meta model for representing modern hardware architectures, as less elements as possible are introduced. For example, dependent of the abstraction level, a component called 
+			<em>ConnectionHandler</em> can express different kind of connection elements, e.g. a crossbar within a SoC or a CAN bus within an E/E-architecture. A simplified overview of the meta model to specify hardware as a model is shown below. The components 
+			<em>ConnectionHandler, ProcessingUnit, Memory</em> and 
+			<em>Cache</em> are referred in the following as basic components.
+		</p>
+		<p>
+			<img class="scale" src="images/user_hw_model_class_diagram.png"/>
+			<br>Class diagram of the hardware model
+		</p>
+		<p>The root element of a hardware model is always the 
+			<em>HwModel</em> class that contains all domains (power and frequency), definitions, and hardware features of the different component definitions. The hierarchy within the model is represented by the 
+			<em>HwStructure</em> class, with the ability to contain further 
+			<em>HwStructure</em> elements. Therewith arbitrary levels of hierarchy could be expressed. Red and blue classes in the figure are the definitions and the main components of a system like a memory or a core.
+		</p>
+		<p>The next figure shows the modeling of a processor. The 
+			<em>ProcessingUnitDefiniton</em>, which is created once, specifies a processing unit with general information (which can be a CPU, GPU, DSP or any kind of hardware accelerator). Using a definition that may be re-used supports quick modeling for multiple homogeneous components within a heterogeneous architecture. 
+			<em>ProcessingUnits</em> then represent the physical instances in the hardware model, referencing the 
+			<em>ProcessingUnitDefiniton</em> for generic information, supplemented only with instance specific information like the 
+			<em>FrequencyDomain</em>.
+		</p>
+		<p>
+			<img class="scale" src="images/user_hw_definition_example.png"/>
+			<br>Link between definitions and module instances (physical components)
+		</p>
+		<p>Yellow represents the power and frequency domains that are always created at the top level of the hardware model. It is possible to model different frequency or voltage values, e.g., when it is possible to set a systems into a power safe mode. All components that reference the domain are then supplied with the corresponding value of the domain.</p>
+		<p>All the green elements in the figure are related to communication (together with the blue base component 
+			<em>ConnectionHandler</em>). Green modeling elements represent ports, static connections, and the access elements for the 
+			<em>ProcessingUnits</em>. These 
+			<em>ProcessingUnits</em> are the master modules in the hardware model. The following example shows two 
+			<em>ProcessingUnits</em> that are connected via a 
+			<em>ConnectionHandler</em> to a 
+			<em>Memory</em>. There are two different possibilities to specify the access paths for 
+			<em>ProcessingUnits</em> like it is shown for ProcessingUnit_2 in figure�"[fig:Logical_and_static_connections]":#fig:Logical_and_static_connections. Every time a 
+			<em>HwAccessElement</em> is necessary to assign the destination e.g. a 
+			<em>Memory</em> component. This 
+			<em>HwAccessElement</em> can contain a latency or a data rate dependent on the use case. The second possibility is to create a 
+			<em>HwAccessPath</em> within the 
+			<em>HwAccessElement</em> which describes the detailed path to the destination by referencing all the 
+			<em>HwConnections</em> and 
+			<em>ConnectionHandlers</em>. It is even possible to reference a cache component within the 
+			<em>HwAccessPath</em> to express if the access is cached or non-cached. Furthermore it is possible to set addresses for these 
+			<em>HwAccessPath</em> to represent the whole address space of a 
+			<em>ProcessingUnit</em>. A typical approach would be starting with just latency or data rates for the communication between components and enhance the model over time to by switching to the 
+			<em>HwAccessPaths</em>.
+		</p>
+		<p>
+			<img class="scale" src="images/user_hw_access_paths.png"/>
+			<br>Access elements in the hardware model
+		</p>
+
+
+<h4><a id="section2.2.1.4"></a>Current implementation with features and the connection to the SW Model</h4>
+		<p>In the previous chapter the long time goal of the feature and recipe concept is explained. As an intermediate step before introducing the recipes we decided to connect the HwModel and SwModel by referencing to the name of the hardware 
+			<em>FeatureCategories</em> from the 
+			<em>ExecutionNeed</em> element in a Runnable. The following figure shows this connection between the grey Runnable item block and the white Features block. Due to the mapping (Task or Runnable to ProcessingUnit) the corresponding feature value can be extracted out of the ProcessingUnitDefinition.
+		</p>
+		<p>
+			<img class="scale" src="images/user_hw_feature_runnable_connection.png"/>
+		</p>
+		<p>An example based on the old hardware model is the "instruction per cycle" value (IPC). To model an IPC with the new approach a 
+			<em>HwFeatureCategory</em> is created with the name 
+			<em>Instructions</em>. Inside this category multiple IPC values can be created for different 
+			<em>ProcessingUnitDefinitions</em>.
+		</p>
+		<p>
+			<img class="scale" src="images/user_hw_feature_runnable_example.png"/>
+			<br>Execution needs example
+		</p>
+
+
+<h4><a id="section2.2.1.5"></a>Interpretation of latencies in the model</h4>
+		<p>In the model read and write access latencies are used. An alternative which is usually used in specifications or by measurements are request and response latencies. The following figure shows a typical communication between two components. The interpretation of a read and write latency for example at 
+			<em>ConnectionHandlers</em> is the following:
+		</p>
+		<p>
+			<img class="scale" src="images/user_hw_latencies.png"/>
+		</p>
+		<ul>
+			<li>
+				<strong>readLatency</strong> = requestLatency + response Latency
+			</li>
+		</ul>
+		<ul>
+			<li>
+				<strong>writeLatency</strong> = requestLatency
+			</li>
+		</ul>
+		<p>The access latency of a 
+			<em>Memory</em> component is always added to the read or write latency from the communication elements, independent if its one latency from an 
+			<em>HwAccessElement</em> or multiple latencies from a 
+			<em>HwAccessPath</em>.
+		</p>
+		<p>As example in case of using only read and write latencies:</p>
+		<ul>
+			<li>
+				<strong>totalReadLatency</strong> = readLatency (HwAccessElement) + accessLatency (Memory)
+			</li>
+		</ul>
+		<ul>
+			<li>
+				<strong>totalWriteLatency</strong> = writeLatency (HwAccessElement) + accessLatency (Memory)
+			</li>
+		</ul>
+		<p>An example in case of using an access element with a hardware access path:</p>
+		<p>
+			<em>n = Number of path elements</em>
+		</p>
+		<ul>
+			<li>
+				<strong>totalReadLatency</strong> =  Sum 1..n ( readLatency(p) ) + accessLatency (Memory)
+			</li>
+		</ul>
+		<ul>
+			<li>
+				<strong>totalWriteLatency</strong> = Sum 1..n ( writeLatency(p) )  + accessLatency (Memory)
+			</li>
+		</ul>
+		<p>PathElements could be 
+			<em>Caches</em>, 
+			<em>ConnectionHandlers</em> and 
+			<em>HwConnections</em>. In very special cases also a 
+			<em>ProcessingUnit</em> can be a 
+			<em>PathElement</em> the 
+			<em>ProcessingUnit</em> has no direct effect on the latency. In case the user want to express a latency it has to be annotated as 
+			<em>HwFeature</em>.
+		</p>
+
+
+<h3><a id="section2.2.2">2.2.2 </a>Software (development)</h3>
+		<p>The AMALTHEA System Model can also be used in early phases of the development process when only limited information about the resulting software is available.</p>
+
+
+<h4><a id="section2.2.2.1"></a>Runnables</h4>
+		<p>The 
+			<i>Runnable</i> element is the basic software unit that defines the behavior of the software in terms of runtime and communication. It can be described on different levels of abstraction: 
+		</p>
+		<ol>
+			<li>timing only (activation and runtime)</li>
+			<li>including communication (in general)</li>
+			<li>adding detailed call sequences</li>
+		</ol>
+		<p>To allow a more detailed simulation a description can also include statistical values like deviations or probabilities. This requires additional information that is typically derived from an already implemented function. The modeling of observed behavior is described in more detail in chapter 
+			<a href="#user-sw-runtime">Software (runtime)</a>.
+		</p>
+
+
+<h4><a id="section2.2.2.2"></a>Process Prototypes</h4>
+		<p>Process Prototypes are used to define the basic data of a task. This is another possibility to describe that a set of Runnables has a similar characteristic (e.g. they have the same periodic activation).
+			<br>A prototype can then be processed and checked by different algorithms. Finally a partitioning algorithm generates (one or more) tasks that are the runtime equivalents of the prototype.
+		</p>
+		<p>
+			<img src="images/process_prototypes.png"/>
+		</p>
+		<p>This processing can be guided by specifications that are provided by the function developers:</p>
+		<ul>
+			<li>The 
+				<strong>Order Specification</strong> is a predefined execution order that has to be guaranteed.
+			</li>
+			<li>An 
+				<strong>Access Specification</strong> defines exceptions from the standard write-before-read semantics.
+			</li>
+		</ul>
+
+
+<h4><a id="section2.2.2.3"></a>Constraints</h4>
+		<p>In addition the partitioning and mapping can be restricted by 
+			<i>Affinity Constraints</i> that enforce the pairing or separation of software elements and by 
+			<i>Property Constraints</i> that connect hardware capabilities and the corresponding software requirements.
+			<br>The 
+			<i>Timing Constraints</i> will typically be used to check if the resulting system fulfills all the requirements.
+		</p>
+
+
+<h4><a id="section2.2.2.4"></a>Activations</h4>
+		<p>Activations are used to specify the intended activation behavior of 
+			<i>Runnables</i> and 
+			<i>ProcessPrototypes</i>. Typically they are defined before the creation of tasks (and the runnable to task mappings). So this is a way to cluster runnables and to document when the runnables should be executed.
+		</p>
+		<p>
+			<img src="images/model__activations.png"/>
+		</p>
+		<p>The following activation patterns can be distinguished:</p>
+		<ul>
+			<li>Single: single activation</li>
+			<li>Periodic: periodic activation with a specific frequency</li>
+			<li>Sporadic: recurring activation without following a specific pattern</li>
+			<li>Event: activation triggered by a 
+				<i>TriggerEvent</i>
+			</li>
+			<li>Custom: custom activation (free textual description)</li>
+		</ul>
+		<p>To describe a specific (observed) behavior at runtime there are 
+			<i>Stimuli</i> in the AMALTHEA model. They can be created based on the information of the specified activations.
+		</p>
+
+
+<h3 id="user-sw-runtime"><a id="section2.2.3">2.2.3 </a>Software (runtime)</h3>
+		<p>During runtime, the dynamic behavior of the software can be observed. The following Gantt chart shows an excerpt of such a dynamic behavior.</p>
+		<p>
+			<img src="images/user_sw_runtime_gantt.png" style="width: 1000px"/>
+		</p>
+		<p>To model the observed behavior in the AMALTHEA model there are schedulable units (Processes) that contain the basic software units (Runnables) and stimuli that describe when the processes are executed. Statistical elements like distributions (Gauss, Weibull, ...) are also available in the model. They allow describing the variation of values if there are multiple occurrences.  </p>
+		<p>In the following sections, a high level description of the individual elements of a software description that define the dynamic behavior are presented.</p>
+
+
+<h4><a id="section2.2.3.1"></a>Processes (Tasks or ISRs)</h4>
+		<p>
+			<img src="images/user_sw_runtime_gantt_task.png" style="width: 1000px"/>
+		</p>
+		<p>Processes represent executable units that are managed by an operating system scheduler. A process is thus the smallest schedulable unit managed by the operating system. Each process also has its own name space and resources (including memory) protected against use from other processes. In general, two different kinds of processes can be distinguished: task and Interrupt Service Routine (ISR). Latter is a software routine called in case of an interrupt. ISRs have normally higher priority than tasks and can only be suspended by another ISR which presents a higher priority than the one running. In the Gantt chart above, a task called 'TASK_InputProcessing' can be seen. All elements that run within the context of a process are described in the following sections.</p>
+
+
+<h5><a id="section2.2.3.1.1"></a>Runnables</h5>
+		<p>
+			<img src="images/user_sw_runtime_gantt_runnable.png" style="width: 1000px"/>
+		</p>
+		<p>Runnables are basic software units. In general it can be said that a Runnable is comparable to a function. It runs within the context of a process and is described by a sequence of instructions. Those instructions can again represent different actions that define the dynamic behavior of the software. Following, such possible actions are listed:</p>
+		<ul>
+			<li>Semaphore Access: request/release of a semaphore</li>
+			<li>Label Access: reading/writing a data signal</li>
+			<li>Instructions: number of unspecified instructions to be executed</li>
+			<li>...</li>
+		</ul>
+		<p>
+			<img src="images/user_sw_new_runnable_iitem.png"/>
+		</p>
+		<p>In the following sections elements, that can be of concern within a runnable, are described in more detail.</p>
+
+
+<h5><a id="section2.2.3.1.2"></a>Labels</h5>
+		<p>
+			<img src="images/user_sw_runtime_gantt_signal.png" style="width: 1000px"/>
+		</p>
+		<p>Labels represent the system's view of data exchange. As a consequence, labels are used to represent communication in a flattened structure, with (at least) one label defined for each data element sent or received by a Runnable instance.</p>
+
+
+<h5><a id="section2.2.3.1.3"></a>Semaphore</h5>
+		<p>
+			<img src="images/user_sw_runtime_gantt_semaphore.png" style="width: 1000px"/>
+		</p>
+		<p>The main functionality of a semaphore is to control simultaneous use of a single resource by several entities, e.g. scheduling of requests, multiple access protection.</p>
+
+
+<h4><a id="section2.2.3.2"></a>Stimulation</h4>
+		<p>Before, we described the dynamic behavior of a specific process instance. In general however, a process is not only activated once but many times. The action of activating a process is called stimulation. The following stimulation patterns are typically used for specification:</p>
+		<ul>
+			<li>Single: single activation of a process</li>
+			<li>Periodic: periodic activation of a process with a specific frequency</li>
+			<li>VariableRate: periodic activations based on other events, like rotation speed</li>
+			<li>Event: activation triggered by a 
+				<i>TriggerEvent</i>
+			</li>
+			<li>InterProcess: activations based on an explicit inter-process trigger</li>
+		</ul>
+		<p>
+			<img src="images/model__stimuli.png"/>
+		</p>
+
+
+<h3><a id="section2.2.4">2.2.4 </a>General Concepts</h3>
+
+
+<h4><a id="section2.2.4.1"></a>Grouping of elements (Tags, Tag groups)</h4>
+		<p>It is possible to use 
+			<a href="#common-tags">Tags</a> for grouping elements of the model. Currently the following AMALTHEA objects are supporting Tags:
+		</p>
+		<ul>
+			<li>abstract class AbstractMemoryElement</li>
+			<li>abstract class Activation</li>
+			<li>class OsEvent</li>
+		</ul>
+		<ul>
+			<li>abstract class Event</li>
+		</ul>
+		<ul>
+			<li>abstract class Stimulus</li>
+		</ul>
+		<ul>
+			<li>abstract class HardwareTypeDescription</li>
+			<li>abstract class ComplexNode</li>
+			<li>class Quartz</li>
+		</ul>
+		<ul>
+			<li>class System</li>
+			<li>class Component</li>
+			<li>class ComponentInstance</li>
+			<li>class Connector</li>
+			<li>abstract class Port</li>
+		</ul>
+
+
+<h4><a id="section2.2.4.2"></a>Custom Properties</h4>
+		<p>The AMALTHEA model provides 
+			<a href="#common-custom-props">Custom Properties</a> to enhance the model in a generic way. These can be used for different kind of purpose:
+		</p>
+		<ul>
+			<li>Store attributes, which are relevant for your model, but not yet available at the elements</li>
+			<li>Processing information of algorithms can be stored in that way, e.g. to mark an element as already processed</li>
+		</ul>
+
+
+<h3><a id="section2.2.5">2.2.5 </a>Scheduling</h3>
+
+
+<h4><a id="section2.2.5.1"></a>Scheduler to Core assignment</h4>
+		<p>We distinguish between physical mapping and responsibility </p>
+		<ul>
+			<li>
+				<strong>Executing Core</strong> means a scheduler produces algorithmic overhead on a core
+			</li>
+			<li>
+				<strong>Responsibility</strong> means a scheduler controls the scheduling on core(s)
+			</li>
+		</ul>
+		<p>
+			<img src="images/user-scheduling-sched-allocation.png"/>
+		</p>
+
+
+<h4><a id="section2.2.5.2"></a>Task to Scheduler assignment</h4>
+		<p>Tasks have a core affinity and are assigned to a scheduler</p>
+		<ul>
+			<li>
+				<strong>Core Affinity</strong> Specifies the possible cores the task can run on. If only one core is specified, the task runs on this core. If multiple cores are specified, the task can migrate between the cores.
+			</li>
+			<li>
+				<strong>Scheduler</strong> specifies the unique allocation of the task to a scheduler.
+			</li>
+		</ul>
+		<p>The scheduling parameters are determined by the scheduling algorithm and are only valid for a specific task – scheduler combination. Therefore the parameters are specified in the TaskAllocation object.</p>
+		<p>
+			<img src="images/user-scheduling-task-allocation.png"/>
+		</p>
+
+
+<h4><a id="section2.2.5.3"></a>Scheduler hierarchies</h4>
+		<p>Schedulers can be arranged in a hierarchy. If set, the parent scheduler takes the initial decision and delegates to a child-scheduler.  If the child-scheduler is not a grouping of tasks, it can take scheduling decisions if permission is granted by the parent.
+			<br>The scheduling parameters are determined by the scheduling algorithm of the parent scheduler. Therefore the relevant parameters in the hierarchical context are specified in the (intermediate) SchedulerAssociation object.
+		</p>
+		<p>
+			<img src="images/user-scheduling-hierarchy.png"/>
+		</p>
+
+
+<h3><a id="section2.2.6">2.2.6 </a>Communication via channels</h3>
+
+
+<h4><a id="section2.2.6.1"></a>Channel</h4>
+		<p>Sender and receiver communicating via a channel by issuing send and receive operations on ports; read policy and transmission policy define communication details.</p>
+		<p>
+			<img src="images/user_channel.png"/>
+		</p>
+		<p>As basic thinking model, reading and writing to channels happens during runnable execution in distinct phases:</p>
+		<ul>
+			<li>Receiving phase: The specified receive operations are performed for every read port.</li>
+			<li>Computing phase: A specified time passes, modeling processing of input data.</li>
+			<li>Sending phase: The specified send operations are performed for every write port. </li>
+		</ul>
+		<p>A channel is specified by two attributes:</p>
+		<ul>
+			<li>
+				<strong>elementType</strong>: the type that is sent or received via connected ports.
+			</li>
+			<li>
+				<strong>defaultElements</strong>:  number of elements initially in the channel (at start-up).
+			</li>
+			<li>
+				<strong>maxElements</strong> (integer) denoting a buffer limit, that is, the channel depth.
+			</li>
+		</ul>
+		<p>In other words, no more than maxElements elements of the given type may be stored in the channel.</p>
+
+
+<h4><a id="section2.2.6.2"></a>Channel Access</h4>
+		<p>In the basic thinking model, all elements are stored as a sequential collection without buffer size limit (unlimited storage).</p>
+		<p>
+			<img src="images/user_channel_access.png"/>
+		</p>
+
+
+<h5><a id="section2.2.6.2.1"></a>Sending</h5>
+		<p>A runnable may send elements to a channel by issuing a send operations.
+			<br>The send operation has a single parameter:
+		</p>
+		<ul>
+			<li>elements (integer): Number of elements that are written.</li>
+		</ul>
+
+
+<h5><a id="section2.2.6.2.2"></a>Receiving</h5>
+		<p>A runnable may receive elements from a channel by issuing receive operations.
+			<br>The operation has multiple aspects:
+		</p>
+		<ul>
+			<li>
+				<strong>Port Type</strong>
+				<ul>
+					<li>A 
+						<strong>LIFO</strong> (last-in, first-out) port is chosen if processing the last written elements is the primary focus and thereby missing elements is tolerable.
+					</li>
+					<li>A 
+						<strong>FIFO</strong> (first-in, first-out) port is chosen if every written element needs to be handled, that is, loss of elements is not tolerable.
+					</li>
+				</ul>
+			</li>
+		</ul>
+		<blockquote>
+			<p>The port type defines the direction the receive operations take effect: accesses from LIFO ports are from top of the sequential collection, while accesses from FIFO ports are from bottom of the sequential collection.</p>
+		</blockquote>
+		<ul>
+			<li>
+				<strong>Receive Operation</strong>
+				<ul>
+					<li>
+						<strong>Read</strong> will received elements without modifying the channel 
+					</li>
+					<li>
+						<strong>Take</strong> will remove the received elements from the channel
+					</li>
+				</ul>
+			</li>
+		</ul>
+		<p>Each operation has two parameters and several attributes specifying the exact behavior:</p>
+		<ul>
+			<li>
+				<strong>elements</strong> (integer): Maximum number n of elements that are received.
+			</li>
+			<li>
+				<strong>elementIndex</strong> (integer): Position (index i) in channel at which the operation is effective. Zero is the default and denotes the oldest (FIFO port) or newest element (LIFO port) in the channel.
+			</li>
+		</ul>
+		<p>Receive operations then are written in function notation, that is Read(n, i) and Take(n, i). For convenience, the index may be left out for default value '0' (Take(n,0) == Take(n)). See next figure for examples which elements are denoted by receive operations for FIFO and LIFO ports.</p>
+		<p>
+			<img src="images/user_channel_operations.png"/>
+		</p>
+		<p>Additional attributes further define the receive operation:</p>
+		<ul>
+			<li>
+				<strong>lowerBound</strong> (integer): Specify the minimum number of elements returned by the operation. The value must be in the range [0,n], with n is the maximum number of elements that are received as specified as attribute of the receive operation. Default value is n.
+			</li>
+			<li>
+				<strong>dataMustBeNew</strong> (Boolean): Specify if the operation must only return elements that are not previously read by this port. Default value is false.
+			</li>
+		</ul>
+
+
+<h5><a id="section2.2.6.2.3"></a>Common Read Policies: Last, New, and AllNew</h5>
+		<p>As three specific read policies are frequently used, these are introduced in the following.</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Policy</th>
+				<th colspan="1" rowspan="1">Port Type</th>
+				<th colspan="1" rowspan="1">Operation</th>
+				<th colspan="1" rowspan="1">lower bound</th>
+				<th colspan="1" rowspan="1">must be new</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Last(x)</strong>
+				</td>
+				<td colspan="1" rowspan="1">LIFO</td>
+				<td colspan="1" rowspan="1"> Read(x,0)</td>
+				<td colspan="1" rowspan="1">x</td>
+				<td colspan="1" rowspan="1">false</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>New(x)</strong>
+				</td>
+				<td colspan="1" rowspan="1">LIFO</td>
+				<td colspan="1" rowspan="1">Read(x,0)</td>
+				<td colspan="1" rowspan="1">0</td>
+				<td colspan="1" rowspan="1">true</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>AllNew</strong>
+				</td>
+				<td colspan="1" rowspan="1">FIFO</td>
+				<td colspan="1" rowspan="1">Take(sizeOfChannel,0)</td>
+				<td colspan="1" rowspan="1">0</td>
+				<td colspan="1" rowspan="1">true</td>
+			</tr>
+		</table>
+		<p>An example of the different behavior of the New and Last policy is shown in the next figure. For demonstration purpose, in the example periodic triggering of the receiving runnables R1 and R2 and sporadic data writing by runnable S is assumed. Note that while New may be used on an empty channel, Last would lead to an error (dashed boxes).
+			<br>Left: Static connection between three runnables (S, R1, and R2). Right: Dynamic view of writing elements to channel over time (green arrows), runnable execution indicated as blue boxes, and the resulting received elements shown in square brackets.
+		</p>
+		<p>
+			<img src="images/user_channel_example.png"/>
+		</p>
+
+
+<h4><a id="section2.2.6.3"></a>Transmission Policy</h4>
+		<p>To further specify how elements are accessed by a runnable in terms of computing time, an optional transmission policy may specify details for each receive and send operation. The intention of the transmission policy is to reflect computing demand (time) depending on data.</p>
+		<p>The transmission policy consists of the following attributes:</p>
+		<ul>
+			<li>
+				<strong>chunkSize</strong>: Size of a part of an element, maximum is the element size.
+			</li>
+			<li>
+				<strong>chunkProcessingInstructions</strong> (integer): Number of instructions that will be executed to send / receive one chunk.
+			</li>
+			<li>
+				<strong>transmitRatio</strong> (float): Specify the ratio of each element that is actually transmitted by the runnable in percent. Value must be between [0, 1], default value is 1.0. 
+			</li>
+		</ul>
+		<p>Example for using transmission policy to detail the receiving phase of a runnable execution. Two elements are received, leading to transmission time as given in the formula. After the receiving phase, the runnable starts with the computing phase.</p>
+		<p>
+			<img src="images/user_channel_transmission_example.png"/>
+		</p>
+
+
+<h3><a id="section2.2.7">2.2.7 </a>Memory Sections</h3>
+		<p>
+			<b>Purpose</b>
+		</p>
+		<p>Memory Sections are used for the division of the memory (RAM/ROM) into different blocks and allocate the "software" memory elements (
+			<em>e.g. Labels</em>), code accordingly inside them.
+			<br>Each Memory Section has certain specific properties (
+			<em>e.g. faster access of the elements, storing constant values</em>). By default compiler vendors provide certain Memory Sections (
+			<em>e.g. .data, .text</em>) and additional Memory Sections can be created based on the project need by enhancing the linker configuration.
+		</p>
+		<p>
+			<b>Definition</b>
+		</p>
+		<p>A "Memory Section" is a region in memory (RAM/ROM) and is addressed with a specific name. There can exist multiple "Memory Sections" inside the same Memory (RAM/ROM) but with different names. Memory Section names should be unique across the Memory (RAM/ROM).</p>
+		<p>Memory Sections can be of two types: </p>
+		<ul>
+			<li>Virtual Memory Section</li>
+			<li>Physical Memory Section</li>
+		</ul>
+
+
+<h4><a id="section2.2.7.1"></a>Virtual Memory Section</h4>
+		<p>"Virtual Memory Sections" are defined as a part of data specification and are associated to the corresponding Memory Elements (e.g. Label's) during the development phase of the software. Intention behind associating "Virtual Memory Sections" to Memory elements like Label's is to control their allocation in specific Memory (e.g. Ram1 or Ram2) by linker. </p>
+		<p>As a part of linker configuration – It is possible to specify if a "Virtual Memory Section" 
+			<i>(e.g. mem.Sec1)</i> can be part of certain Memory 
+			<em>(e.g. Ram1/Ram2/SYSRAM but not Ram3)</em>.
+		</p>
+		<p>
+			<ins>
+				<em>Example:</em>
+			</ins> 
+		</p>
+		<p>Software should be built for ManyCore ECU – containing 3 Cores 
+			<em>(Core1, Core2, Core3)</em>. Following RAMs are associated to the Cores: Ram1 – Core1, Ram2 – Core2, Ram3 – Core3, and also there is SYSRAM.
+		</p>
+		<p>Virtual Memory Section : mem.sec1 
+			<em>(is defined as part of data specification)</em> is associated to Label1 and Label2.
+		</p>
+		<p>
+			<img class="scale" src="images/user_section_label_ref_to_memsection.png"/>
+		</p>
+		<p>In Linker configuration it is specified that mem.sec1 can be allocated only in Ram1 or Ram2.</p>
+		<p>Below diagram represents the 
+			<em>
+				<ins>
+					<strong>linker configuration content</strong>
+				</ins>
+			</em> - w.r.t. possibility for physical allocation of mem.sec1 in various memories .
+		</p>
+		<p>
+			<img class="scale" src="images/user_section_linker_memsection.png"/>
+		</p>
+		<p>Based on the above configuration – Linker will allocate Label1, Label2 either in Ram1/Ram2/SYSRAM but not in Ram3/Ram4.</p>
+
+
+<h4><a id="section2.2.7.2"></a>Physical Memory Section</h4>
+		<p>"Physical Memory Sections" are generated by linker. The linker allocates various memory elements (e.g. Label's) inside "Physical Memory Sections".</p>
+		<p>Each "Physical Memory Section" has following properties:</p>
+		<ul>
+			<li>Name – It will be unique across each Memory </li>
+			<li>Start and End address – This represents the size of "Physical Memory Section"</li>
+			<li>Associated Physical Memory 
+				<em>(e.g. Ram1 or Ram2)</em>
+			</li>
+		</ul>
+		<p>
+			<ins>
+				<em>Example:</em>
+			</ins>  There can exist mem.sec1.py inside Ram1 and also in Ram2. But these are physically two different elements as they are associated to different memories (Ram1 and Ram2) and also they have different "start and end address". 
+		</p>
+		<p>Below diagram represents the information w.r.t. virtual memory sections 
+			<em>(defined in data specification and associated to memory elements)</em> and physical memory sections 
+			<i>(generated after linker run)</i>.
+		</p>
+		<p>
+			<img class="scale" src="images/user_section_virtual_to_physical.png"/>
+		</p>
+
+
+<h4><a id="section2.2.7.3"></a>Modeling Memory Section information in AMALTHEA</h4>
+		<ul>
+			<li>As described in the above concept section:
+				<ul>
+					<li>Virtual memory sections are used:
+						<ul>
+							<li>To specify constraints for creation of Physical memory sections by linker</li>
+							<li>To control allocation of data elements (e.g. Labels) in a specific memory 
+								<em>(e.g. Ram1/Ram2/SYSRAM)</em>
+							</li>
+						</ul>
+					</li>
+					<li>Physical memory sections are containing the data elements after linker run 
+						<em>(representing the software to be flashed into ECU)</em> 
+					</li>
+				</ul>
+			</li>
+		</ul>
+		<p>Below figure represents the modeling of "Memory Section" (both virtual and physical) information in AMALTHEA model:
+			<br>
+			<img class="scale" src="images/user_section_amalthea.png"/>
+		</p>
+		<p>Below are equivalent elements of AMALTHEA model used for modeling the Memory Section information:</p>
+		<ul>
+			<li>
+				<strong>Section</strong> 
+				<ul>
+					<li>This element is equivalent to Virtual Memory Section defined during the SW development phase.</li>
+					<li>As a part of data specification defined in the sw-development phase, a Section object 
+						<em>(with specific name)</em> is associated to Label and Runnable elements.
+					</li>
+				</ul>
+			</li>
+		</ul>
+		<ul>
+			<li>
+				<strong>PhysicalSectionConstraint</strong>
+				<ul>
+					<li>This element is equivalent to the constraint specified in the linker configuration file, which is used to instruct linker for the allocation of Physical Memory Sections in specified Memories.</li>
+					<li>PhysicalSectionContraint is used to specify the combination of Virtual Memory Section and Memories 
+						<em>(which can be considered by linker for generation of Physical Memory Sections)</em>.
+					</li>
+				</ul>
+			</li>
+		</ul>
+		<blockquote>
+			<p>
+				<em>
+					<ins>Example:</ins>
+				</em>   PhysicalSectionConstraint-1 is specifying following relation "Section-1" &lt;--&gt; "Memory-1", "Memory-2". This means that the corresponding Physical Memory Section for "Section-1" can be generated by linker in "Memory-1" or in "Memory-2" 	or in both. 
+			</p>
+		</blockquote>
+		<ul>
+			<li>
+				<strong>PhysicalSectionMapping</strong> 
+				<ul>
+					<li>This element is equivalent to Physical Memory Section generated during the linker run.
+						<ul>
+							<li>Each PhysicalSectionMapping element:
+								<ul>
+									<li>Contains the Virtual Memory Section 
+										<em>(e.g. Section-1)</em> which is the source. 
+									</li>
+									<li>is associated to a specific Memory and it contains the start and end memory address 
+										<em>(difference of start and end address represents the size of Physical Memory Section)</em>.
+									</li>
+									<li>contains the data elements 
+										<em>(i.e. Labels, Runnables part of the final software)</em>.
+									</li>
+								</ul>
+							</li>
+						</ul>
+					</li>
+				</ul>
+			</li>
+		</ul>
+		<blockquote>
+			<p>
+				<strong>Note:</strong> There is also a possibility to associate multiple Virtual Memory Section's as linker has a concept of grouping Virtual Memory Sections while generation of Physical Memory Section.
+			</p>
+		</blockquote>
+		<blockquote>
+			<p>
+				<em>
+					<ins>Example:</ins>
+				</em> For the same Virtual Memory Section 
+				<i>(e.g. Section-1)</i>, linker can generate multiple Physical Memory Sections in different Memories 
+				<em>(e.g. PhysicalSectionMapping-1, PhysicalSectionMapping-2)</em>. Each PhysicalSectionMapping element is an individual entity as it has a separate start and end memory address.
+			</p>
+		</blockquote>
+
+
+<h2><a id="section2.3">2.3 </a>Examples</h2>
+
+
+<h3><a id="section2.3.1">2.3.1 </a>Modeling Example 1</h3>
+
+
+<h4><a id="section2.3.1.1"></a>General information</h4>
+		<p>Modeling Example 1 describes a simple system consisting of 4 Tasks, which is running on a dual core processor.
+			<br>The following figure shows the execution footprint in a Gantt chart:
+			<br>
+			<img src="images/modeling_1_gantt.png"/>
+			<br>In the following sections, the individual parts of the AMALTHEA model for Modeling Example 1 are presented followed by a short description of its elements.
+		</p>
+
+
+<h4><a id="section2.3.1.2"></a>Hardware Model</h4>
+		<p>
+			<img src="images/modeling_1_hw.png"/>
+		</p>
+		<p>The hardware model of Modeling Example 1 consists as already mentioned of a dual core processor.
+			<br>The following gives a structural overview on the modeled elements.
+			<br>There, the two cores, 'Core_1' and 'Core_2', have a static processing frequency of 100 MHz each, which is specified by the corresponding quartz oscillator 'Quartz'.
+		</p>
+
+
+<h4><a id="section2.3.1.3"></a>Operating System Model</h4>
+		<p>
+			<img src="images/modeling_1_schedulers.png"/>
+		</p>
+		<p>The operating system (OS) model defines in case of Modeling Example 1 only the needed Scheduler.
+			<br>Since a dual core processor has to be managed, two schedulers are modeled correspondingly.
+			<br>In addition to the scheduling algorithm used by the scheduler, in this case OSEK, a delay of 100 ns is set, which is the presumed time the scheduler needs for context switches.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Scheduler</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Algorithm</th>
+				<th colspan="1" rowspan="1">Delay</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Scheduler_1</strong>
+				</td>
+				<td colspan="1" rowspan="1">SchedulingHWUnit</td>
+				<td colspan="1" rowspan="1">OSEK</td>
+				<td colspan="1" rowspan="1">100 ns</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Scheduler_2</strong>
+				</td>
+				<td colspan="1" rowspan="1">SchedulingHWUnit</td>
+				<td colspan="1" rowspan="1">OSEK</td>
+				<td colspan="1" rowspan="1">100 ns</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section2.3.1.4"></a>Mapping Model</h4>
+		<p>
+			<img src="images/modeling_1_mapping.png"/>
+		</p>
+		<p>The mapping model defines allocations between different model parts.
+			<br>On the one hand, this is the allocation of processes to a scheduler.
+			<br>In case of Example 1, 'Task_1' and 'Task_2' are managed by 'Scheduler_1', while the other tasks are managed by 'Scheduler_2'.
+			<br>On the other hand the allocation of cores to a scheduler is set.
+			<br>For Modeling Example 1 two local schedulers were modeled.
+			<br>As a consequence, each scheduler manages one of the processing cores.
+			<br>A comprehension of the modeled properties can be found in the following tables:
+		</p>
+
+
+<h5><a id="section2.3.1.4.1"></a>Executable Allocation</h5>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Scheduler</th>
+				<th colspan="1" rowspan="1">Process</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Task_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Task_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_2</td>
+				<td colspan="1" rowspan="1">Task_3</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_2</td>
+				<td colspan="1" rowspan="1">Task_4</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section2.3.1.4.2"></a>Core Allocation</h5>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Scheduler</th>
+				<th colspan="1" rowspan="1">Core</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Core_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_2</td>
+				<td colspan="1" rowspan="1">Core_2</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section2.3.1.5"></a>Software Model</h4>
+
+
+<h5><a id="section2.3.1.5.1"></a>Tasks</h5>
+		<p>
+			<img src="images/modeling_1_tasks.png"/>
+		</p>
+		<p>As already mentioned above, the software model of Modeling Example 1 consists exactly of four tasks, named 'Task_1' to 'Task_4'.
+			<br>Each task is preemptive and has a priority assigned according its deadline, meaning the one with the shortest deadline, 'Task_1', has the highest priority, and so on.
+			<br>Each task also calls a definitive number of Runnables in a sequential order.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">MTA*</th>
+				<th colspan="1" rowspan="1">Deadline</th>
+				<th colspan="1" rowspan="1">Calls</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Task_1</strong>
+				</td>
+				<td colspan="1" rowspan="1">4</td>
+				<td colspan="1" rowspan="1">Preemptive</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">75 ms</td>
+				<td colspan="1" rowspan="1">1) Runnable_1_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="2">
+					<strong>Task_2</strong>
+				</td>
+				<td colspan="1" rowspan="2">3</td>
+				<td colspan="1" rowspan="2">Preemptive</td>
+				<td colspan="1" rowspan="2">1</td>
+				<td colspan="1" rowspan="2">115 ms</td>
+				<td colspan="1" rowspan="1">1) Runnable_2_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">2) Runnable_2_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">
+					<strong>Task_3</strong>
+				</td>
+				<td colspan="1" rowspan="3">2</td>
+				<td colspan="1" rowspan="3">Preemptive</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="3">300 ms</td>
+				<td colspan="1" rowspan="1">1) Runnable_3_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">2) Runnable_3_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">3) Runnable_3_3</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="4">
+					<strong>Task_4</strong>
+				</td>
+				<td colspan="1" rowspan="4">1</td>
+				<td colspan="1" rowspan="4">Preemptive</td>
+				<td colspan="1" rowspan="4">1</td>
+				<td colspan="1" rowspan="4">960 ms</td>
+				<td colspan="1" rowspan="1">1) Runnable_4_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">2) Runnable_4_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">3) Runnable_4_3</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">4) Runnable_4_4</td>
+			</tr>
+		</table>
+		<p>*MTA = Multiple Task Activation Limit</p>
+
+
+<h5><a id="section2.3.1.5.2"></a>Runnables</h5>
+		<p>
+			<img src="images/modeling_1_runnables.png"/>
+		</p>
+		<p>In addition to the task, the software model also contains a definition of Runnables.
+			<br>For Modeling Example 1, ten individual Runnables are defined.
+			<br>The only function of those in this example is to consume processing resources.
+			<br>Therefore, for each Runnable a constant number of instruction cycles is stated.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Runnable</th>
+				<th colspan="1" rowspan="1">InstructionCycles</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_1_1</td>
+				<td colspan="1" rowspan="1">1500000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_2_1</td>
+				<td colspan="1" rowspan="1">1500000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_2_2</td>
+				<td colspan="1" rowspan="1">1500000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_3_1</td>
+				<td colspan="1" rowspan="1">1000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_3_2</td>
+				<td colspan="1" rowspan="1">2000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_3_3</td>
+				<td colspan="1" rowspan="1">1000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_4_1</td>
+				<td colspan="1" rowspan="1">1000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_4_2</td>
+				<td colspan="1" rowspan="1">2000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_4_3</td>
+				<td colspan="1" rowspan="1">3000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable_4_4</td>
+				<td colspan="1" rowspan="1">2000000</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section2.3.1.6"></a>Stimuli Model</h4>
+		<p>
+			<img src="images/modeling_1_stimuli.png"/>
+		</p>
+		<p>The stimulation model defines the activations of tasks.
+			<br>Since the four tasks of Modeling Example 1 are activated periodically, four stimuli according their recurrence are modeled.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Stimulus</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Offset</th>
+				<th colspan="1" rowspan="1">Recurrence</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Stimulus_Task_1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1">0 ms</td>
+				<td colspan="1" rowspan="1">180 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Stimulus_Task_2</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1">0 ms</td>
+				<td colspan="1" rowspan="1">200 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Stimulus_Task_3</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1">0 ms</td>
+				<td colspan="1" rowspan="1">300 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Stimulus_Task_4</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1">0 ms</td>
+				<td colspan="1" rowspan="1">1 s</td>
+			</tr>
+		</table>
+
+
+<h3><a id="section2.3.2">2.3.2 </a>Modeling Example 2</h3>
+
+
+<h4><a id="section2.3.2.1"></a>General information</h4>
+		<p>Modeling Example 2 describes a simple system consisting of 4 Tasks, which is running on a single core processor.
+			<br>The following figure shows the execution footprint in a Gantt chart:
+			<br>
+			<img src="images/modeling_2_gantt.png"/>
+			<br>In the following sections, the individual parts of the AMALTHEA model for Modeling Example 2 are presented followed by a short description of its elements.
+		</p>
+
+
+<h4><a id="section2.3.2.2"></a>Hardware Model</h4>
+		<p>
+			<img src="images/modeling_2_hw.png"/>
+		</p>
+		<p>The hardware model of Modeling Example 2 consists as already mentioned of a single core processor.
+			<br>The following gives a structural overview on the modeled elements.
+			<br>There, the core, 'Core_1' , has a static processing frequency of 600 MHz each, which is specified by the corresponding quartz oscillator 'Quartz_1'.
+		</p>
+
+
+<h4><a id="section2.3.2.3"></a>Operating System Model</h4>
+		<p>
+			<img src="images/modeling_2_scheduler.png"/>
+		</p>
+		<p>The operating system (OS) model defines in case of Modeling Example 2 only the needed Scheduler.
+			<br>Since only a single core has to be managed, a single scheduler is modeled correspondingly.
+			<br>In addition to the scheduling algorithm used by the scheduler, in this case OSEK, a delay of 100 ns is set, which is the presumed time the scheduler needs for context switches.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Scheduler</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Algorithm</th>
+				<th colspan="1" rowspan="1">Delay</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Scheduler_1</strong>
+				</td>
+				<td colspan="1" rowspan="1">SchedulingHwUnit</td>
+				<td colspan="1" rowspan="1">OSEK</td>
+				<td colspan="1" rowspan="1">100 ns</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section2.3.2.4"></a>Mapping Model</h4>
+		<p>
+			<img src="images/modeling_2_mapping.png"/>
+		</p>
+		<p>The mapping model defines allocations between different model parts.
+			<br>On the one hand, this is the allocation of processes to a scheduler.
+			<br>Since there is only one scheduler available in the system, all four tasks are mapped to 'Scheduler_1'.
+			<br>On the other hand the allocation of cores to a scheduler is set.
+			<br>As a consequence, the scheduler manages the only available processing core.
+			<br>A comprehension of the modeled properties can be found in the following tables:
+		</p>
+
+
+<h5><a id="section2.3.2.4.1"></a>Executable Allocation</h5>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Scheduler</th>
+				<th colspan="1" rowspan="1">Process</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Task_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Task_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Task_3</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Task_4</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section2.3.2.4.2"></a>Core Allocation</h5>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Scheduler</th>
+				<th colspan="1" rowspan="1">Core</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Scheduler_1</td>
+				<td colspan="1" rowspan="1">Core_1</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section2.3.2.5"></a>Software Model</h4>
+
+
+<h5><a id="section2.3.2.5.1"></a>Tasks</h5>
+		<p>
+			<img src="images/modeling_2_tasks.png"/>
+		</p>
+		<p>As already mentioned above, the software model of Modeling Example 2 consists exactly of four tasks, named 'Task_1' to 'Task_4'.
+			<br>All tasks have assigned the same priority (10) to get a cooperative scheduling.
+			<br>'Task_2' to'Task_4' call a definitive number of Runnables in a sequential order.
+			<br>'Task_1' instead contains a call graph that models two different possible execution sequences.
+			<br>In 70% of the cases the sequence 'Runnable_1_1', 'Runnable_1_2', 'Task_2', 'Runnable_1_4' is called, while in the remaining 30% the sequence 'Runnable_1_1', 'Runnable_1_3', 'Task_3', 'Runnable_1_4' is called.
+			<br>As it can be seen, the call graph of 'Task_1' contains also interprocess activations, which activate other tasks.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">MTA*</th>
+				<th colspan="1" rowspan="1">Deadline</th>
+				<th colspan="1" rowspan="1">Calls</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="8">
+					<strong>Task_1</strong>
+				</td>
+				<td colspan="1" rowspan="8">10</td>
+				<td colspan="1" rowspan="8">Preemptive</td>
+				<td colspan="1" rowspan="8">3</td>
+				<td colspan="1" rowspan="8">25 ms</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">1.1) Runnable_1_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">1.2) Runnable_1_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">1.3) Task_2</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">1.4) Runnable_1_4</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">2.1) Runnable_1_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">2.2) Runnable_1_3</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">2.3) Task_3</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">2.4) Runnable_1_4</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Task_2</strong>
+				</td>
+				<td colspan="1" rowspan="1">10</td>
+				<td colspan="1" rowspan="1">Preemptive</td>
+				<td colspan="1" rowspan="1">3</td>
+				<td colspan="1" rowspan="1">25 ms</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">1) Runnable_2_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Task_3</strong>
+				</td>
+				<td colspan="1" rowspan="1">10</td>
+				<td colspan="1" rowspan="1">Preemptive</td>
+				<td colspan="1" rowspan="1">3</td>
+				<td colspan="1" rowspan="1">25 ms</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">1) Runnable_3_1</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Task_4</strong>
+				</td>
+				<td colspan="1" rowspan="1">10</td>
+				<td colspan="1" rowspan="1">Preemptive</td>
+				<td colspan="1" rowspan="1">3</td>
+				<td colspan="1" rowspan="1">25 ms</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">1) Runnable_4_1</td>
+			</tr>
+		</table>
+		<p>*MTA = Multiple Task Activation Limit</p>
+
+
+<h5><a id="section2.3.2.5.2"></a>Runnables</h5>
+		<p>
+			<img src="images/modeling_2_runnables.png"/>
+		</p>
+		<p>In addition to the task, the software model also contains a definition of Runnables.
+			<br>For Modeling Example 2, seven individual Runnables are defined.
+			<br>The only function of those in this example is to consume processing resources.
+			<br>Therefore, for each Runnable a number of instruction cycles is stated.
+			<br>The number of instruction cycles is thereby either constant or defined by a statistical distribution.
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Runnable</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Instructions</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Runnable_1_1</strong>
+				</td>
+				<td colspan="1" rowspan="1">Constant</td>
+				<td colspan="1" rowspan="1">1000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Runnable_1_2</strong>
+				</td>
+				<td colspan="1" rowspan="1">Constant</td>
+				<td colspan="1" rowspan="1">2000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Runnable_1_3</strong>
+				</td>
+				<td colspan="1" rowspan="1">Constant</td>
+				<td colspan="1" rowspan="1">3000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Runnable_1_4</strong>
+				</td>
+				<td colspan="1" rowspan="1">Constant</td>
+				<td colspan="1" rowspan="1">4000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="2">
+					<strong>Runnable_2_1</strong>
+				</td>
+				<td colspan="1" rowspan="2">Uniform Distribution</td>
+				<td colspan="1" rowspan="1">1000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">5000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">
+					<strong>Runnable_3_1</strong>
+				</td>
+				<td colspan="1" rowspan="3">Gauss Distribution</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">mean: 1000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">sd: 50000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">upper: 5000000</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Runnable_4_1</strong>
+				</td>
+				<td colspan="1" rowspan="1">Constant</td>
+				<td colspan="1" rowspan="1">4000000</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section2.3.2.6"></a>Stimulation Model</h4>
+		<p>
+			<img src="images/modeling_2_stimuli.png"/>
+		</p>
+		<p>The stimulation model defines the activations of tasks.
+			<br>'Task_1' is activated periodically by 'Stimulus_Task_1'
+			<br>'Stimulus_Task_2' and 'Stimulus_Task_3' represent the inter-process activations for the corresponding tasks. 
+			<br>'Task_4' finally is activated sporadically following a Gauss distribution. 
+			<br>A comprehension of the modeled properties can be found in the following table:
+		</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Stimulus</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Parameters</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="2">
+					<strong>Stimulus_Task_1</strong>
+				</td>
+				<td colspan="1" rowspan="2">Periodic</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">offset: 0 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">recurrence: 25 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Stimulus_Task_2</strong>
+				</td>
+				<td colspan="1" rowspan="1">Inter-Process</td>
+				<td colspan="1" rowspan="1"/>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>Stimulus_Task_3</strong>
+				</td>
+				<td colspan="1" rowspan="1">Inter-Process</td>
+				<td colspan="1" rowspan="1"/>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">
+					<strong>Stimulus_Task_4</strong>
+				</td>
+				<td colspan="1" rowspan="3">Sporadic (Gauss)</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">mean: 30 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">sd: 5 ms</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">upper: 100 ms</td>
+			</tr>
+		</table>
+
+
+<h3><a id="section2.3.3">2.3.3 </a>Modeling Example "Purely Periodic without Communication"</h3>
+		<p>This system architecture pattern consists of a task set, where each task is activated periodically and no data accesses are performed. The execution time for each task is determined by the called runnable entities as specified in the table below. All tasks contain just one runnable except of T<sub>7</sub>, which calls at first R<sub>7,1</sub> and after that R<sub>7,2</sub>.</p>
+		<p>The table below gives a detailed specification of the tasks and their parameters. The tasks are scheduled according fixed-priority, preemptive scheduling and if not indicated otherwise, all events are active in order to get a detailed insight into the system's behavior.</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">Multiple Task Activation Limit</th>
+				<th colspan="1" rowspan="1">Activation</th>
+				<th colspan="2" rowspan="1">Execution Time</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>1</sub></td>
+				<td colspan="1" rowspan="3">7</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 9.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 80</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 10</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>2</sub></td>
+				<td colspan="1" rowspan="3">6</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 29.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 120</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 30</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>3</sub></td>
+				<td colspan="1" rowspan="3">5</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>3</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 19.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 160</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 20</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>4</sub></td>
+				<td colspan="1" rowspan="3">4</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>4</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 14.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 180</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 15</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>5</sub></td>
+				<td colspan="1" rowspan="3">3</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>5</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 29.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 200</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 30</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>6</sub></td>
+				<td colspan="1" rowspan="3">2</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>6</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 39.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 300</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 40</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="6">T<sub>7</sub></td>
+				<td colspan="1" rowspan="6">1</td>
+				<td colspan="1" rowspan="6">FULL</td>
+				<td colspan="1" rowspan="6">1</td>
+				<td colspan="1" rowspan="2"/>
+				<td colspan="1" rowspan="3">R<sub>7,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 59.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 60</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="3">R<sub>7,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 1000</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 19.95</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 20</td>
+			</tr>
+		</table>
+		<p>In order to show the impact of changes to the model, the following consecutive variations are made to the model: </p>
+		<dl>
+			<dt>
+				<b>1) Initial Task Set</b>
+			</dt>
+			<dd>For this variation, the Tasks T<sub>4</sub>, T<sub>5</sub>, T<sub>6</sub>, and T<sub>7</sub> of the table above are active.
+				<br>
+				<img src="images/modeling_example_periodic_1.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>2) Increase of Task Set Size I</b>
+			</dt>
+			<dd>For this variation, the Tasks T<sub>3</sub>, T<sub>4</sub>, T<sub>5</sub>, T<sub>6</sub>, and T<sub>7</sub> are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_periodic_2.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>3) Increase of Task Set Size II</b>
+			</dt>
+			<dd>For this variation, the Tasks T<sub>1</sub>, T<sub>3</sub>, T<sub>4</sub>, T<sub>5</sub>, T<sub>6</sub>, and T<sub>7</sub> are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_periodic_3.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>4) Increase of Task Set Size III</b>
+			</dt>
+			<dd>As from this variation on, all tasks (T<sub>1</sub> - T<sub>7</sub>) are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_periodic_4.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>5) Accuracy in Logging</b>
+			</dt>
+			<dd>For this variation, just task events are active. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_periodic_5.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>6) Schedule</b>
+			</dt>
+			<dd>As from this variation on, T<sub>7</sub> is set to non-preemptive. That way, the timing behavior is changed, which results in extinct activations (see red mark in the figure below).
+				<br>
+				<img src="images/modeling_example_periodic_6.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>7) Activation</b>
+			</dt>
+			<dd>As from this variation on, the maximum number of queued activation requests for all tasks is set to 2. That way, the problem with extinct activations resulting from the previous variation is solved.
+				<br>
+				<img src="images/modeling_example_periodic_7.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>8) Schedule Point</b>
+			</dt>
+			<dd>For this variation, a schedule point is added to T<sub>7</sub> between the calls of R<sub>7,1</sub> and R<sub>7,2</sub>. That way, the timing behavior is changed in particular.
+				<br>
+				<img src="images/modeling_example_periodic_8.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>9) Scheduling Algorithm</b>
+			</dt>
+			<dd>For this variation, the scheduling algorithm is set to Earliest Deadline First. That way, the timing behavior is changed completely.
+				<br>
+				<img src="images/modeling_example_periodic_9.png"/>
+			</dd>
+		</dl>
+
+
+<h3><a id="section2.3.4">2.3.4 </a>Modeling Example "Client-Server without Reply"</h3>
+		<p>This system architecture pattern extends the modeling example "Purely Periodic without Communication" by adding an one-way communication between tasks. It consists of two tasks T<sub>1</sub>, and T<sub>2</sub>. Task T<sub>1</sub> sends a message to Task T<sub>2</sub> before runnable R<sub>1</sub> is called. In 20% of the cases Message 1, in 30% of the cases Message 2, in 20% of the cases Message 3, in 15% of the cases Message 4, and in 15% of the cases any other message than the previously mentioned ones is sent. Task T<sub>2</sub> reacts on the contents of the message by calling different runnables. In case of Message 1 runnable R<sub>2,1</sub>, in case of Message 2 runnable R<sub>2,2</sub>, in case of Message 3 runnable R<sub>2,3</sub>, in case of Message 4 runnable R<sub>2,4</sub>, and in case of any other message than the previous mentioned ones runnable R<sub>2,x</sub> is called as default.</p>
+		<p>
+			<img src="images/modeling_example_client_server.png"/>
+		</p>
+		<p>The table below gives a detailed specification of the tasks and their parameters. The tasks are scheduled according fixed-priority, preemptive scheduling and if not indicated otherwise, all events are active in order to get a detailed insight into the system's behavior.</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">Multiple Task Activation Limit</th>
+				<th colspan="1" rowspan="1">Activation</th>
+				<th colspan="2" rowspan="1">Execution Time</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>1</sub></td>
+				<td colspan="1" rowspan="3">2</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 9.9 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 100 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 10 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="15">T<sub>2</sub></td>
+				<td colspan="1" rowspan="15">1</td>
+				<td colspan="1" rowspan="15">FULL</td>
+				<td colspan="1" rowspan="15">1</td>
+				<td colspan="1" rowspan="6"/>
+				<td colspan="1" rowspan="3">R<sub>2,x</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">R<sub>2,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 990</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 1 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>2,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 15 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 60 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="6"/>
+				<td colspan="1" rowspan="3">R<sub>2,3</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 990 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 1 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">R<sub>2,4</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 39.6 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 40 * 10<sup>6</sup></td>
+			</tr>
+		</table>
+		<p>In order to show the impact of changes to the model, the following consecutive variations are made to the model:</p>
+		<dl>
+			<dt>
+				<b>1) Initial Task Set</b>
+			</dt>
+			<dd>As defined by the table above.
+				<br>
+				<img src="images/modeling_example_client_server_1.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>2) Exclusive Area</b>
+			</dt>
+			<dd>For this variation, all data accesses are protected by an exclusive area. Therefore, the data accesses in T<sub>1</sub> as well as all runnables in T<sub>2</sub> (R<sub>2,x</sub>, R<sub>2,1</sub>, R<sub>2,2</sub>, R<sub>2,3</sub>, and R<sub>2,4</sub>) are protected during their complete time of execution via a mutex and priority ceiling protocol. That way, blocking situations appear.
+				<br>
+				<img src="images/modeling_example_client_server_2.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>3) Inter-process Activation</b>
+			</dt>
+			<dd>As from this variation on, task T<sub>2</sub> gets activated by an inter-process activation from task T<sub>1</sub> instead of being activated periodically. The interprocess activation is performed right after the message 
+				<em>message</em> is written in T<sub>2</sub> and consequently before the runnable R<sub>1</sub> is called. That way, a direct connection between T<sub>1</sub> and T<sub>2</sub> is established.
+				<br>
+				<img src="images/modeling_example_client_server_3.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>4) Priority Ordering</b>
+			</dt>
+			<dd>As from this variation on, the priority relation between task T<sub>1</sub> and T<sub>2</sub> is reversed. As a consequence, the priority of task T<sub>1</sub> is set to 1 and the priority of task T<sub>2</sub> is set to 2. That way, a switch from asynchronous to synchronous communication is considered.
+				<br>
+				<img src="images/modeling_example_client_server_4.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>5) Event Frequency Increase</b>
+			</dt>
+			<dd>As from this variation on, the periodicity of T<sub>1</sub> is shortened. For this, the value for the period of task T<sub>1</sub> is cut in half to 50 * 10<sup>6</sup> time units. That way, the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_client_server_5.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>6) Execution Time Fluctuation</b>
+			</dt>
+			<dd>As from this variation on, the execution time distribution is widened for both tasks. Therefore, the maximum of every uniform distribution is increased by 1 percent so that they vary now by 2 percent. That way, the utilization  of the system is increased, which results in extinct activations.
+				<br>
+				<img src="images/modeling_example_client_server_6.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>7) Activation</b>
+			</dt>
+			<dd>As from this variation on, the maximum number of queued activation requests for both tasks is set to 2. That way, the problem with extinct activations resulting from the previous variation is solved.
+				<br>
+				<img src="images/modeling_example_client_server_7.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>8) Accuracy in Logging of Data State I</b>
+			</dt>
+			<dd>For this variation, the data accesses in task T<sub>1</sub> and task T<sub>2</sub> are omitted. Instead, the runnable entities R<sub>2,x</sub>, R<sub>2,1</sub>, R<sub>2,2</sub>, R<sub>2,3</sub>, and R<sub>2,4</sub>, each representing the receipt of a specific message, are executed equally random, meaning each with a probability of 20%. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_client_server_8.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>9) Accuracy in Logging of Data State II</b>
+			</dt>
+			<dd>For this variation, just task events are active. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_client_server_9.png"/>
+			</dd>
+		</dl>
+
+
+<h3><a id="section2.3.5">2.3.5 </a>Modeling Example "State Machine"</h3>
+		<p>In this system architecture pattern the modeling example "Client Server without Reply" is extended in such a way that now the task that receives messages (T<sub>2</sub>) not only varies its dynamic behavior and consequently also its execution time according the transmitted content but also depending on its internal state, meaning the prior transmitted contents. To achieve, this task T<sub>1</sub> sends a message to task T<sub>2</sub> with either 0 or 1 before runnable R<sub>1</sub> is called. The value 0 is used in 75 % of the cases and 1 in the other cases as content of the message. Starting in state 0, T<sub>2</sub> decreases or increases the state its currently in depending on the content of the message, 0 or 1 respectively. The runnable R 
+			<sub>2,1</sub>, R 
+			<sub>2,2</sub>, and R 
+			<sub>2,3</sub> represent then the three different states that the system can be in.
+		</p>
+		<p>
+			<img src="images/modeling_example_state_machine.png"/>
+		</p>
+		<p>The table below gives a detailed specification of the tasks and their parameters. The tasks are scheduled according fixed-priority, preemptive scheduling and if not indicated otherwise, all events are active in order to get a detailed insight into the system's behavior.</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">Multiple Task Activation Limit</th>
+				<th colspan="1" rowspan="1">Activation</th>
+				<th colspan="2" rowspan="1">Execution Time</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>1</sub></td>
+				<td colspan="1" rowspan="3">2</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 9.9 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 100 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 10 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="9">T<sub>2</sub></td>
+				<td colspan="1" rowspan="9">1</td>
+				<td colspan="1" rowspan="9">FULL</td>
+				<td colspan="1" rowspan="9">1</td>
+				<td colspan="1" rowspan="3"/>
+				<td colspan="1" rowspan="3">R 
+					<sub>2,1</sub>
+				</td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R 
+					<sub>2,2</sub>
+				</td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 15 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 60 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3"/>
+				<td colspan="1" rowspan="3">R<sub>2,3</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>6</sup></td>
+			</tr>
+		</table>
+		<p>In order to show the impact of changes to the model, the following consecutive variations are made to the model:</p>
+		<dl>
+			<dt>
+				<b>1) Initial Task Set</b>
+			</dt>
+			<dd>As defined by the table above.
+				<br>
+				<img src="images/modeling_example_state_machine_1.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>2) Exclusive Area</b>
+			</dt>
+			<dd>For this variation, all data accesses are protected by an exclusive area. Therefore, the data accesses in T<sub>1</sub> as well as all runnables in T<sub>2</sub> (R<sub>2,1</sub>, R<sub>2,2</sub>, and R<sub>2,3</sub>) are protected during their complete time of execution via a mutex and priority ceiling protocol. That way, blocking situations appear.
+				<br>
+				<img src="images/modeling_example_state_machine_2.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>3) Priority Ordering</b>
+			</dt>
+			<dd>As from this variation on, the priority relation between task T<sub>1</sub> and T<sub>2</sub> is reversed. As a consequence, the priority of task T<sub>1</sub> is set to 1 and the priority of task T<sub>2</sub> is set to 2. That way, the timing behavior is changed fully.
+				<br>
+				<img src="images/modeling_example_state_machine_3.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>4) Inter-process Activation</b>
+			</dt>
+			<dd>As from this variation on, task T<sub>2</sub> gets activated by an inter-process activation from task T<sub>1</sub> instead of being activated periodically. The interprocess activation is performed right after the message 
+				<em>message</em> is written in T<sub>1</sub> and consequently before the runnable R<sub>1</sub> is called. That way, a direct connection between T<sub>1</sub> and T<sub>2</sub> is established.
+				<br>
+				<img src="images/modeling_example_state_machine_4.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>5) Event Frequency Increase</b>
+			</dt>
+			<dd>As from this variation on, the periodicity of T<sub>1</sub> is shortened. For this, the value for the period of task T<sub>1</sub> is halved to 50 * 10<sup>6</sup>. That way, the utilization  of the system is increased, which results in extinct activations.
+				<br>
+				<img src="images/modeling_example_state_machine_5.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>6) Activation</b>
+			</dt>
+			<dd>As from this variation on, the maximum number of queued activation requests for both tasks is set to 2. That way, the problem with extinct activations resulting from the previous variation is solved.
+				<br>
+				<img src="images/modeling_example_state_machine_6.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>7) Execution Time Fluctuation</b>
+			</dt>
+			<dd>As from this variation on, the execution time distribution is widened for both tasks. Therefore, the maximum of the uniform distribution is increased by 1 percent so that the uniform distribution varies now by 2 percent. That way, the utilization  of the system is further increased.
+				<br>
+				<img src="images/modeling_example_state_machine_7.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>8) Accuracy in Logging of Data State I</b>
+			</dt>
+			<dd>For this variation, the data write accesses in task T<sub>1</sub> and task T<sub>2</sub> are omitted. Instead, the runnables R<sub>2,1</sub>, R<sub>2,2</sub>, and R<sub>2,3</sub>, each representing the execution of a specific state, are executed with a probability of 60 %, 30 %, and 10 % respectively. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_state_machine_8.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>9) Accuracy in Logging of Data State II</b>
+			</dt>
+			<dd>For this variation, just task events are active. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_state_machine_9.png"/>
+			</dd>
+		</dl>
+
+
+<h3><a id="section2.3.6">2.3.6 </a>Modeling Example "Feedback Loop"</h3>
+		<p>The task set of the modeling example "State Machine" is expanded further in this architecture pattern with the result that messages are exchanged in a loop, instead of just in one way. To achieve this, task T<sub>1</sub> sends a message 
+			<em>u</em> to task T<sub>2</sub> before runnable R<sub>1</sub> is called. The content of this message is 0, if the content of a previously received message 
+			<em>e</em> is 0, or 1 if it was 1. Task T<sub>2</sub> represents then a state machine with three states that increases its state, if message 
+			<em>u</em> is 1 and decreases, if it is 0. In each state the messages 
+			<em>y</em> and 
+			<em>w</em> are set with state specific values and sent to task T<sub>3</sub> and task T<sub>4</sub> respectively. In case of 
+			<em>State 0</em>, the messages 
+			<em>y</em> and 
+			<em>w</em> contain the value 0, in case of 
+			<em>State 1</em> both contain 50 and in case of 
+			<em>State 2</em> the value 100 is sent. These messages are written before runnable R<sub>2</sub> is called. However, in 30 % of the cases task T<sub>4</sub> is activated via an inter-process activation before this runnable call happens. Task T<sub>3</sub> varies its dynamic behavior and consequently also its execution time according the transmitted content of message 
+			<em>y</em>. Task T<sub>4</sub> finally prepares again the input for task T<sub>1</sub>. If the content received in message 
+			<em>w</em> is 0, then in 30% of the cases the content of message 
+			<em>e</em> is 0, otherwise 1. In the case that message 
+			<em>w</em> is 50, message 
+			<em>e</em> is set to 0 with a probability of 50% and to 1 accordingly. Finally, message 
+			<em>e</em> is set to 0 in 70% of the cases and to 1 in 30% of the cases, if message 
+			<em>w</em> is 100. In addition to this feedback loop, other system architecture patterns are added to be executed concurrently in order to increase the complexity. The tasks T<sub>5</sub> and T<sub>6</sub> represent a client-server without reply and are equal to the tasks T<sub>1</sub> and T<sub>2</sub> respectively as described in the modeling example "Client-Server without Reply". T<sub>7</sub> is a periodically activated task without any communication and identical to task T<sub>7</sub> of modeling example "Purely Periodic without Communication".
+		</p>
+		<p>
+			<img src="images/modeling_example_feedback_loop.png"/>
+		</p>
+		<p>The table below gives a detailed specification of the tasks and their parameters. The tasks are scheduled according fixed-priority, preemptive scheduling and if not indicated otherwise, all events are active in order to get a detailed insight into the system's behavior.</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">Multiple Task Activation Limit</th>
+				<th colspan="1" rowspan="1">Activation</th>
+				<th colspan="2" rowspan="1">Execution Time</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>1</sub></td>
+				<td colspan="1" rowspan="3">3</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 9.9 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 600 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 10 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>2</sub></td>
+				<td colspan="1" rowspan="3">2</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 20 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>4</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 300 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>4</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="9">T<sub>3</sub></td>
+				<td colspan="1" rowspan="9">3</td>
+				<td colspan="1" rowspan="9">FULL</td>
+				<td colspan="1" rowspan="9">1</td>
+				<td colspan="1" rowspan="3"/>
+				<td colspan="1" rowspan="3">R<sub>3,0</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>4</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>4</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>3,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 50 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 500 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3"/>
+				<td colspan="1" rowspan="3">R<sub>3,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>4</sub></td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1"/>
+				<td colspan="1" rowspan="3">R<sub>4</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Inter-process Activation</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>5</sub></td>
+				<td colspan="1" rowspan="3">5</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>5</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 100 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="15">T<sub>6</sub></td>
+				<td colspan="1" rowspan="15">4</td>
+				<td colspan="1" rowspan="15">FULL</td>
+				<td colspan="1" rowspan="15">1</td>
+				<td colspan="1" rowspan="6"/>
+				<td colspan="1" rowspan="3">R<sub>6,x</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">R<sub>6,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 990</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 1 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>6,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 15 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 60 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="6"/>
+				<td colspan="1" rowspan="3">R<sub>6,3</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 990 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 1 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">R<sub>6,4</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="6">T<sub>7</sub></td>
+				<td colspan="1" rowspan="6">0</td>
+				<td colspan="1" rowspan="6">FULL</td>
+				<td colspan="1" rowspan="6">1</td>
+				<td colspan="1" rowspan="2"/>
+				<td colspan="1" rowspan="3">R<sub>7,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 59.4 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 60 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="3">R<sub>7,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 1000</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 19.8 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 20 * 10<sup>6</sup></td>
+			</tr>
+		</table>
+		<p>In order to show the impact of changes to the model, the following consecutive variations are made to the model:</p>
+		<dl>
+			<dt>
+				<b>1) Initial Task Set</b>
+			</dt>
+			<dd>For this variation, the tasks T<sub>1</sub>, T<sub>2</sub>, T<sub>3</sub>, and T<sub>4</sub> of the table above are active.
+				<br>
+				<img src="images/modeling_example_feedback_loop_1.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>2) Increase of Task Set Size I</b>
+			</dt>
+			<dd>For this variation, the Tasks T<sub>1</sub>, T<sub>2</sub>, T<sub>3</sub>, T<sub>4</sub>, T<sub>5</sub>, and T<sub>6</sub> are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_feedback_loop_2.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>3) Increase of Task Set Size II</b>
+			</dt>
+			<dd>As from this variation on, all tasks are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_feedback_loop_3.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>4) Inter-process Activation</b>
+			</dt>
+			<dd>As from this variation on, task T<sub>2</sub> gets activated by an inter-process activation from task T<sub>1</sub>, task T<sub>3</sub> by an inter-process activation from task T<sub>2</sub>, and task T<sub>6</sub> by an inter-process activation from task T<sub>5</sub> instead of being activated periodically. The inter-process activation in task T<sub>1</sub> is performed right after the message 
+				<em>u</em> is written in T<sub>2</sub> and consequently before the runnable R<sub>1</sub> is called, in task T<sub>2</sub> respectively right before task T<sub>4</sub> is activated, and in task T<sub>5</sub> task T<sub>6</sub> is called right before runnable R<sub>5</sub>. That way, a direct connection between these tasks is established.
+				<br>
+				<img src="images/modeling_example_feedback_loop_4.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>5) Event Frequency Increase</b>
+			</dt>
+			<dd>As from this variation on, the periodicity of the tasks T<sub>1</sub>, T<sub>5</sub>, and T<sub>7</sub> are shortened. For task T<sub>1</sub>, the value for the period is set to 450 * 10<sup>6</sup>, the task T<sub>5</sub> to 60 * 10<sup>6</sup>, and for task T<sub>7</sub> to 575 * 10<sup>6</sup>. That way, the information density is increased.
+				<br>
+				<img src="images/modeling_example_feedback_loop_5.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>6) Execution Time Fluctuation</b>
+			</dt>
+			<dd>As from this variation on, the execution time distribution is widened for both tasks. Therefore, the maximum of the uniform distribution is increased by 1 percent so that the uniform distribution varies now by 2 percent. That way, the utilization  of the system is increased, which results in extinct activations.
+				<br>
+				<img src="images/modeling_example_feedback_loop_6.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>7) Activation</b>
+			</dt>
+			<dd>As from this variation on, the maximum number of queued activation requests for both tasks is set to 2. That way, the problem with extinct activations resulting from the previous variation is solved.
+				<br>
+				<img src="images/modeling_example_feedback_loop_7.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>8) Accuracy in Logging of Data State I</b>
+			</dt>
+			<dd>For this variation, the data accesses in all tasks are omitted. Instead, the runnable entities R<sub>3,0</sub>, R<sub>3,1</sub>, and R<sub>3,2</sub>, are executed with a probability of 50 %, 30 %, and 20 % respectively, and the runnable entities R<sub>6,x</sub>, R<sub>6,1</sub>, R<sub>6,2</sub>, R<sub>6,3</sub>, and R<sub>6,4</sub> are executed with a probability of 15 %, 20 %, 30 %, 20 %, and 15 % respectively. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_feedback_loop_8.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>9) Accuracy in Logging of Data State II</b>
+			</dt>
+			<dd>For this variation, just task events are active. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_feedback_loop_9.png"/>
+			</dd>
+		</dl>
+
+
+<h3><a id="section2.3.7">2.3.7 </a>Modeling Example "State Machine Feedback Loop"</h3>
+		<p>The task set of the modeling example "State Machine" is expanded further in this architecture pattern by combining the ideas behind the modeling example "State Machine" and "Feedback Loop". This means that messages are exchanged in a loop and each sender/receiver is also a state machine. To achieve this, task T<sub>1</sub> has two different internal states 0 and 1, and task T<sub>2</sub> manages three consecutive states 0, 1, and 2. The state task T<sub>1</sub> is currently in is sent via a message to task T<sub>2</sub> before runnable R<sub>1</sub> is called. If the content of the message sent from task T<sub>1</sub> is 1, task T<sub>2</sub> increases its internal state, e.g. from state 0 to 1, and if it is 0, task T<sub>2</sub> decreases its internal state accordingly. Then, depending on the state task T<sub>2</sub> is currently in, the according runnable (R<sub>2,0</sub> for state 0, etc.) is executed. If the maximum or minimum state of task T<sub>2</sub> is reached but the received message from task T<sub>1</sub> tells task T<sub>2</sub> to further increase or respectively decrease its internal state, task T<sub>2</sub> sends a message to task T<sub>1</sub>. This message then causes task T<sub>1</sub> to toggle its internal state which consequently results in a switch from increasing to decreasing or vice versa. In addition to this state machine feedback loop, other system architecture patterns are added to be executed concurrently in order to increase the complexity. The tasks T<sub>3</sub> and T<sub>4</sub> represent a client-server without reply and are equal to the tasks T<sub>1</sub> and T<sub>2</sub> respectively as described above in the modeling example "Client-Server without Reply". T<sub>5</sub> is a periodically activated task without any communication and identical to task T<sub>7</sub> in the modeling example "Purely Periodic without Communication".</p>
+		<p>
+			<img src="images/modeling_example_state_machine_feedback_loop.png"/>
+		</p>
+		<p>The table below gives a detailed specification of the tasks and their parameters. The tasks are scheduled according fixed-priority, preemptive scheduling and if not indicated otherwise, all events are active in order to get a detailed insight into the system's behavior.</p>
+		<table class="classic" style="text-align:center; background:#f8f8f8">
+			<tr style="background:#eee">
+				<th colspan="1" rowspan="1">Task</th>
+				<th colspan="1" rowspan="1">Priority</th>
+				<th colspan="1" rowspan="1">Preemption</th>
+				<th colspan="1" rowspan="1">Multiple Task Activation Limit</th>
+				<th colspan="1" rowspan="1">Activation</th>
+				<th colspan="2" rowspan="1">Execution Time</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>1</sub></td>
+				<td colspan="1" rowspan="3">2</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 9.9 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 300 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 10 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="9">T<sub>2</sub></td>
+				<td colspan="1" rowspan="9">1</td>
+				<td colspan="1" rowspan="9">FULL</td>
+				<td colspan="1" rowspan="9">1</td>
+				<td colspan="1" rowspan="3"/>
+				<td colspan="1" rowspan="3">R<sub>2,0</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>2,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 15 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 250 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3"/>
+				<td colspan="1" rowspan="3">R<sub>2,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">T<sub>3</sub></td>
+				<td colspan="1" rowspan="3">4</td>
+				<td colspan="1" rowspan="3">FULL</td>
+				<td colspan="1" rowspan="3">1</td>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>3</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 100 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100 * 10<sup>5</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="15">T<sub>4</sub></td>
+				<td colspan="1" rowspan="15">3</td>
+				<td colspan="1" rowspan="15">FULL</td>
+				<td colspan="1" rowspan="15">1</td>
+				<td colspan="1" rowspan="6"/>
+				<td colspan="1" rowspan="3">R<sub>4,x</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 99</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 100</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">R<sub>4,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 990</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 1 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="3">R<sub>4,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 15 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 60 * 10<sup>6</sup></td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="6"/>
+				<td colspan="1" rowspan="3">R<sub>4,3</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 990 * 10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 1 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="3">R<sub>4,4</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 49.5 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 50 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="6">T<sub>5</sub></td>
+				<td colspan="1" rowspan="6">0</td>
+				<td colspan="1" rowspan="6">FULL</td>
+				<td colspan="1" rowspan="6">1</td>
+				<td colspan="1" rowspan="2"/>
+				<td colspan="1" rowspan="3">R<sub>5,1</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 59.4 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Periodic</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 60 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Offset = 0</td>
+				<td colspan="1" rowspan="3">R<sub>5,2</sub></td>
+				<td colspan="1" rowspan="1">Uniform</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Recurrence = 1000</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Min = 19.8 * 10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">Max = 20 * 10<sup>6</sup></td>
+			</tr>
+		</table>
+		<p>In order to show the impact of changes to the model, the following consecutive variations are made to the model:</p>
+		<dl>
+			<dt>
+				<b>1) Initial Task Set</b>
+			</dt>
+			<dd>For this variation, the tasks T<sub>1</sub>, and T<sub>2</sub> of the table above are active.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_1.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>2) Increase of Task Set Size I</b>
+			</dt>
+			<dd>For this variation, the tasks T<sub>1</sub>, T<sub>2</sub>, T<sub>3</sub>, and T<sub>4</sub> are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_2.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>3) Increase of Task Set Size II</b>
+			</dt>
+			<dd>As from this variation on, all tasks are active. That way the utilization  of the system is increased.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_3.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>4) Inter-process Activation</b>
+			</dt>
+			<dd>As from this variation on, task T<sub>2</sub> gets activated by an inter-process activation from task T<sub>1</sub>, and task T<sub>4</sub> by an inter-process activation from task T<sub>3</sub> instead of being activated periodically. The inter-process activation in task T<sub>1</sub> is performed right after the message to task T<sub>2</sub> is written and consequently before the runnable R<sub>1</sub> is called, and in task T<sub>3</sub> task T<sub>4</sub> is called right before runnable R<sub>3</sub>. That way, a direct connection between these tasks is established.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_4.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>5) Event Frequency Increase</b>
+			</dt>
+			<dd>As from this variation on, the periodicity of the tasks T<sub>1</sub>, T<sub>3</sub>, and T<sub>5</sub> are shortened. For task T<sub>1</sub>, the value for the period is set to 220 * 10<sup>6</sup>, the task T<sub>3</sub> to 50 * 10<sup>6</sup>, and for task T<sub>5</sub> to 500 * 10<sup>6</sup>. That way, the information density is increased.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_5.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>6) Execution Time Fluctuation</b>
+			</dt>
+			<dd>As from this variation on, the execution time distribution is widened for both tasks. Therefore, the maximum of the uniform distribution is increased by 1 percent so that the uniform distribution varies now by 2 percent. That way, the utilization  of the system is increased, which results in extinct activations.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_6.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>7) Activation</b>
+			</dt>
+			<dd>As from this variation on, the maximum number of queued activation requests for both tasks is set to 2. That way, the problem with extinct activations resulting from the previous variation is solved.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_7.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>8) Accuracy in Logging of Data State I</b>
+			</dt>
+			<dd>For this variation, the data accesses in all tasks are omitted. Instead, all runnablea representing a state are executed equally random, meaning the runnables R<sub>2,0</sub>, R<sub>2,1</sub>, and R<sub>2,2</sub> are each executed with a probability of 33 %, and the runnables R<sub>4,x</sub>, R<sub>4,1</sub>, R<sub>4,2</sub>, R<sub>4,3</sub>, and R<sub>4,4</sub> each with a probability of 20 %. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_8.png"/>
+			</dd>
+		</dl>
+		<dl>
+			<dt>
+				<b>9) Accuracy in Logging of Data State II</b>
+			</dt>
+			<dd>For this variation, just task events are active. That way, only a limited insight into the system's runtime behavior is available.
+				<br>
+				<img src="images/modeling_example_state_machine_feedback_loop_9.png"/>
+			</dd>
+		</dl>
+
+
+<h3><a id="section2.3.8">2.3.8 </a>Modeling Examples "Scheduler"</h3>
+		<p>The following elements are used to illustrate the structure of the example schedulers:</p>
+		<p>
+			<img src="images/modeling_example_scheduler_legend.png"/>
+		</p>
+
+
+<h4><a id="section2.3.8.1"></a>Hierarchical Scheduler</h4>
+		<p>In this example the main scheduler realizes a 
+			<strong>Priority Round Robin</strong> strategy. The main scheduler works as a global scheduler that schedules subsystems like virtual machines or hypervisor partitions. Each partition realizes an 
+			<strong>OSEK</strong> scheduling system. In this case the main scheduler is responsible for both cores but only running on one core. Each 
+			<strong>OSEK</strong> subsystem is responsible for exactly one core but only if the main scheduler grants the core usage. The 
+			<strong>OSEK</strong> subsystems then decide on a FPP basis, which task can run. The coreAffinity for the tasks is not needed, since their scheduler is only responsible for one core.
+		</p>
+		<p>
+			<img src="images/modeling_example_scheduler_hierarchical.png"/>
+		</p>
+
+
+<h4><a id="section2.3.8.2"></a>Partitioned_FPP Scheduler</h4>
+		<p>In this example a custom FPP scheduler named 
+			<strong>Partitioned_FPP</strong> is representing a global scheduler. It schedules tasks on a FPP basis but with the additional constraint that it's group must have budget left (has similarities to QNX's adaptive partitioned scheduling). The scheduler "Grouping" is only there to assign budgets to a logical task group and define no mapping or responsibility at all. Therefore in the taskAllocation only priority and coreAffinity are specified. The coreAffinity of tasks in the same group can differ, even task migration is possible if a task's affinity is 
+			<strong>CoreA</strong> as well as 
+			<strong>CoreB</strong>.
+		</p>
+		<p>
+			<img src="images/modeling_example_scheduler_partitioned_fpp.png"/>
+		</p>
+
+
+<h3><a id="section2.3.9">2.3.9 </a>Democar Example</h3>
+		<p>The so called Democar model presented in the AMALTHEA example files describe a simple engine management system.</p>
+
+
+<h4><a id="section2.3.9.1"></a>Origin</h4>
+		<p>The Democar example is loosely based on the publicly available information taken from</p>
+		<blockquote>
+			<p>
+				<br> 
+				<strong>A Timing Model for Real-Time Control-Systems and its Application</strong>
+				<br> 
+				<strong>on Simulation and Monitoring of AUTOSAR Systems</strong>
+				<br> 
+				<em>Author: Patrick Frey</em>
+			</p>
+		</blockquote>
+		<p>A version of the dissertation can be downloaded from University of Ulm: 
+			<a href="https://oparu.uni-ulm.de/xmlui/handle/123456789/1770">pdf</a>.
+		</p>
+
+
+<h4><a id="section2.3.9.2"></a>Files</h4>
+		<p>
+			<strong>AMALTHEA_Democar.amxmi</strong>
+			<br>contains the complete model, consisting of a hardware model, a model of the operating system, a stimulation model and a model that describes the software system.
+		</p>
+		<p>
+			<strong>Amalthea_ArExampleEngine.atdb</strong>
+			<br>is an AMALTHEA Trace Database and it contains a trace that is the result of a simulation of this example. 
+		</p>
+
+
+<h3><a id="section2.3.10">2.3.10 </a>HwModel Example</h3>
+		<p>This example contains two simple hardware models:</p>
+		<p>
+			<strong>Example 1: Simple_ECU</strong>
+		</p>
+		<p>
+			<img class="scale" src="images/example_hw_example_1_diagram.png"/>
+		</p>
+		<p>The example shows a single structure with two identical cores with such an Instruction per cycle feature. The model includes only one frequency domain and no power domain. Each core is connected to all three different memory units via a 
+			<em>HwAccessElement</em> with read and write latencies. The memory components include an access latency. This means the total latency for a read and a write access are calculated in the following way:
+		</p>
+		<p>
+			<em>TotalReadLatency = readLatency + accessLatency</em>
+			<br>
+			<em>TotalWriteLatency = writeLatency + accessLatency</em>
+		</p>
+		<p>This example shows a very simple hardware modeling approach where no interconnects and ports are necessary. Such a model can be used in a very early design phase where only rough estimations or a limited amount of informations about the system are available.</p>
+		<p>
+			<img src="images/example_hw_example_1_editor.png"/>
+		</p>
+		<p>
+			<strong>Example 2: Simple_E_E_Architecture</strong>
+		</p>
+		<p>
+			<img class="scale" src="images/example_hw_example_2_diagram.png"/>
+		</p>
+		<p>The second example shows a simple E/E-Architecture out of two identical ECUs. Each ECU contains two cores, one interconnect and a memory component. Both ECUs are connected via a CAN-Bus. In this example both possibilities for a 
+			<em>HwAccessElement</em> are shown. The local memory is just connected with read and write latencies and the external memory of the other ECU is connected with the help of a 
+			<em>HwAccessPath</em>. To use access paths hardware ports and connections between those ports are mandatory. The access paths itself is an ordered list of elements which are used for the connection. As an example for the access path between Core1EC1 and MainMemEC2 following access path elements are referred:
+		</p>
+		<p>con1 -&gt; internalCan_ECU1 -&gt; con4 -&gt; con9 -&gt; CAN -&gt; con10 -&gt; con8 -&gt; InterconnectEC2 -&gt; con7.</p>
+		<p>That means the complete access paths includes:</p>
+		<ul>
+			<li>3 x ConnectionHandler</li>
+			<li>6 x HwConnections</li>
+		</ul>
+		<p>The latency in this case is the sum of all elements of the path plus the access latency of the memory. However latencies at connections are usually only used to account an offset for a specific component. In case a data rate is used the maximum data rate is limited by the lowest data rate in the path. In case of a 
+			<em>ConnectionHandler</em> the data rate is usually shared between different accesses.
+			<br>The hierarchical ports from both ECUs to connect the CAN Bus with the ECUs as block boxes are not mandatory but recommended. This concept of hierarchical ports increases the number of HwConnections but allows also the structuring of all internal modules within a HwStructure and only connect the hierarchical ports with the rest of the system.
+		</p>
+		<p>
+			<img src="images/example_hw_example_2_editor.png"/>
+		</p>
+
+
+<h2><a id="section2.4">2.4 </a>Tutorials</h2>
+
+
+<h3 id="example-task-creation"><a id="section2.4.1">2.4.1 </a>Task creation example</h3>
+		<p>The following section will describe how to generate tasks out of software models with 
+			<i>sequencing constraints</i>.
+		</p>
+		<p>
+			<strong>Step 1</strong>
+		</p>
+		<p>
+			<img src="images/02-democar-example.png"/>
+		</p>
+		<p>Create a new example project based on the "Democar Example" (
+			<strong>File -&gt; New -&gt; Example</strong>).
+		</p>
+		<p>
+			<strong>Step 2</strong>
+		</p>
+		<p>
+			<img class="gray" src="images/04-generate-tasks.png"/>
+		</p>
+		<p>Click on the left arrow of the "org.eclipse.app4mc.amalthea.example.democar.mapping" project to expand it. You will see several files with models of the democar project, each of them containing one specific model, e.g. "AMALTHEA_Democar_MappingExample.amxmi" with the software model and constraints model. Usually, a software model needs to be partitioned before it can be mapped. You can either use the partitioning plugin for this, or the included (already partitioned) software model.
+			<br>Right-click on the file "AMALTHEA_Democar_MappingExample.amxmi" and click "Generate Tasks" to start the task generation process. This will also convert the 
+			<i>Activation</i> elements from the partitioned software model to 
+			<i>Stimuli</i> and store these in a stimulation model.
+		</p>
+		<p>
+			<strong>Step 3</strong>
+		</p>
+		<p>
+			<img src="images/05-output-model.png"/>
+		</p>
+		<p>Once the tasks have been generated, a new file with tasks will be created in the "output" folder. The file "AMALTHEA_Democar_MappingExample_withTasks.amxmi" contains the final software model, the stimulation model and the constraints model and is ready to be mapped.</p>
+
+
+<h3 id="example-mapping-1"><a id="section2.4.2">2.4.2 </a>Mapping example 1</h3>
+		<p>The following section will describe how to calculate a mapping with the AMALTHEA tool platform using the DFG and ILP based load balancing algorithms.</p>
+		<p>
+			<strong>Step 1</strong>
+		</p>
+		<p>
+			<img src="images/06-perform-mapping.png"/>
+		</p>
+		<p>The mapping example required a software model with tasks. You can either use the resulting model from the previous task creation example ("AMALTHEA_Democar_MappingExample_withTasks.amxmi") or the already existing software model example. Right-click the file with the software model you would like to map and select "Perform Mapping" to open the GUI for the mapping.</p>
+		<p>
+			<strong>Step 2</strong>
+		</p>
+		<p>
+			<img src="images/07-perform-mapping-ui.png"/>
+		</p>
+		<p>The name of the project as well as the path to the software project have already been entered for you. To perform the mapping, you need to specify the path to a hardware model. This can be done by clicking on the second "Search" button from the top and locating the file "AMALTHEA_Democar_MappingExample-hw.amxmi". Now you only need to click "Create Mapping" to perform the calculations and create a mapping from tasks to cores.</p>
+		<p>
+			<strong>Step 3</strong>
+		</p>
+		<p>
+			<img class="gray" src="images/08-inspect.png"/>
+		</p>
+		<p>Once the mapping is performed, a new file will be generated in the "output" folder. Mapping and OS can be found in the file "AMALTHEA_Democar_MappingExample_withTasks_out.amxmi". To inspect this file, just double-click on it to open a content tree explorer.
+			<br>Additional information about the mapping is provided in the console.
+		</p>
+
+
+<h3 id="example-mapping-2"><a id="section2.4.3">2.4.3 </a>Mapping example 2</h3>
+		<p>The following section will describe how to calculate a mapping with the AMALTHEA Tool Platform using the experimental energy minimization algorithm.</p>
+		<p>
+			<strong>Step 1</strong>
+		</p>
+		<p>
+			<img src="images/09-preferences.png"/>
+		</p>
+		<p>The first step is to change the mapping algorithm into the "Energy efficient mapping" algorithm. Do this by clicking on "Window" and then "Preferences" in the menu bar. The preferences window will open and you are able to configure the mapping plugin on its preferences page under the point "AMALTHEA Mapping".
+			<br>Select "Energy efficient mapping (Experimental)" and close the page using the OK button on the bottom.
+		</p>
+		<p>
+			<strong>Step 2</strong>
+		</p>
+		<p>The algorithm for energy efficient mapping (minimization of the energy consumption) comes with specifically altered model files based on the Democar and HVAC use case which are stored in the folder "modelEnergyEfficient". Open this folder, right click on one of the two "AMALTHEA????_EnergyEfficientMappingExample.amxmi" files and select perform mapping. As this algorithm comes with its own task creation algorithm, we can skip the task creation process.</p>
+		<p>
+			<strong>Step 3</strong>
+		</p>
+		<p>Similar to the previous example, the name of the project as well as the path have already been entered for you. To perform the mapping, specify the path to the hardware model. This is done by clicking the second search button from the top and locating the file "IMX6.amxmi-hw" within the "modelEnergyEfficient" folder. Start the mapping calculation by hitting the "Create Mapping" button.</p>
+		<p>
+			<strong>Step 4</strong>
+		</p>
+		<p>
+			<img src="images/10-inspect.png"/>
+		</p>
+		<p>Once the mapping is performed, two additional files will be generated in the "output" folder. The mapping can be found in the file "AMALTHEA_????_MappingExample_withTasks_mapping.amxmi-mapping". To inspect this file, just double-click on it to open a content tree explorer.
+			<br>Additional information about the mapping is provided in the console.
+		</p>
+
+
+<h3 id="example-taskvis"><a id="section2.4.4">2.4.4 </a>Task Visualizer Example</h3>
+		<p>The following section describes how to visualize the execution of tasks along with their states on cores using the task visualizer plugin.</p>
+		<p>
+			<strong>Preparation</strong>
+		</p>
+		<p>In order to execute the task visualizer, it is necessary to describe the overall system in terms of an AMALTHEA Model file. The minimal amount of information consists of</p>
+		<ul>
+			<li>Tasks (Software Model) which contain Runnables (Software Model) and refer to Periodic Activations (Stimuli Model)</li>
+			<li>Cores (Hardware Model)</li>
+			<li>Allocations of Tasks to Cores (Mapping Model) </li>
+		</ul>
+		<p>Creating such a Model can either be done manually or by following the Tutorial on "Mapping example 1" </p>
+		<p>
+			<strong>Step 1</strong>
+		</p>
+		<p>
+			<img src="images/01-taskvis.png"/>
+		</p>
+		<p>Right-click the file containing the System you would like to visualize and select "Visualize Task Execution" from the "AMALTHEA Multicore Features" context menu to open the Task Visualization Overview.</p>
+		<p>
+			<strong>Step 2</strong>
+		</p>
+		<p>
+			<img src="images/02-taskvis-overview.png"/>
+		</p>
+		<p>The Task Visualization Overview provides basic information about the software as well as the hardware of the system. The upper part summarizes the allocations of Tasks to Cores, along with the number of total instructions per Task, the period between a tasks activation, the core these tasks are allocated to, as well as the Worst Case Execution Time (WCET) in terms of ps and percentages of the cores total utilization. THe lower part summaraizes the available cores along with the number of computatable instructions per second (IPS) and their utilization (with 1.0 being 100%). Continue by clicking next to advance to the the Task Dependencie Overview. </p>
+		<p>
+			<strong>Step 3</strong>
+		</p>
+		<p>
+			<img src="images/03-taskvis-dependencies.png"/>
+		</p>
+		<p>The Task Dependencies Overview visualizes the task graph with its inter-task dependencies as well as the communication delay. For simplicity, several restrictions are applied to the considered dependencies as illustrated in the box "Relations Filter".    </p>
+		<p>If the check box "Consider task precedence" is deactivated, the tasks will be handled as batch tasks without any dependencies among each other.</p>
+		<p>For this tutorial, we activate the task precedence consideration and advance to the scheduling selection by clicking next.</p>
+		<p>
+			<strong>Step 4</strong>
+		</p>
+		<p>
+			<img src="images/04-taskvis-scheduling.png"/>
+		</p>
+		<p>The Scheduling Selection screen allows to fine-tune the execution visualization and to specify a scheduling algorithm. Until now, the following scheduling approaches are implemented:</p>
+		<ul>
+			<li>Preemptive Rate Monotonic Scheduling</li>
+			<li>Cooperative Earliest Deadline First</li>
+			<li>Preemptive Earliest Deadline First</li>
+		</ul>
+		<p>The scale allows configuring the "step" or "increment size" during the execution calculation, e.g. by setting this value to ms, each internal "tick" will increment the the execution model by one millisecond. If a task's total execution time is lower then the increment size, it will be round up to one millisecond. Consequently, the value should be set to a similar scale as the average execution time of the tasks.</p>
+		<p>Finally, the Simulation-Time allows specifying the time frame which should be visualized, e.g. with a task period of 15 ms, a value of 30.000.000.000 ps (30 ms) will visualize 2 periods. </p>
+		<p>To continue with this tutorial, set all values as shown in the figure and click "Finish" to plot the Execution Visualization.</p>
+		<p>
+			<strong>Step 5</strong>
+		</p>
+		<p>
+			<img src="images/05-taskvis-traceview.png"/>
+		</p>
+		<p>Finally, a Gantt-Chart illustrating the execution of each core is shown. By double-clicking the tab "TraceView", you can maximize the window to full-screen.</p>
+		<p>The top element of each chart illustrates the core's utilization, followed by the states of each task, which are defined as followed:</p>
+		<ul>
+			<li>Green: Running</li>
+			<li>Yellow: Ready</li>
+			<li>Red: Suspended</li>
+			<li>Orange: Waiting</li>
+		</ul>
+		<p>The description of the actual state as well as their start/end times can also been seen by hovering the cursor over a state.</p>
+
+
+<h3><a id="section2.4.5">2.4.5 </a>AMALTHEA Trace Database (ATDB) Import Example</h3>
+		<p>The following section describes how to use the information contained within an AMALTHEA Trace Database (ATDB) to create a model.</p>
+		<p>
+			<strong>Step 1</strong>
+		</p>
+		<p>
+			<img src="images/amalthea_trace_db_example.png"/>
+		</p>
+		<p>The figure above shows content of "Amalthea_ArExampleEngine.atdb", an AMALTHEA Trace database provided with the "Democar Example". 
+			<br>To get this file create a new example project (see "Creating an example"), based on the "Democar Example".
+		</p>
+		<p>
+			<strong>Step 2</strong>
+		</p>
+		<p>
+			<img src="images/amalthea_import_options.png"/>
+		</p>
+		<p>Right-click on the project folder "org.eclipse.app4mc.amalthea.example.democar" or any other. You will see several possible options. In that option menu press "Import..." then.
+			<br>This will open a dialogue where the different import options available are listed. Open the folder called "AMALTHEA" by clicking on cross next to the title. This is shown in the figure above.
+		</p>
+		<p>
+			<strong>Step 3</strong>
+		</p>
+		<p>
+			<img src="images/atdb_import_dialogue.png"/>
+		</p>
+		<p>Next, choose mark the option "From AMALTHEA Trace DB" by clicking on it and proceed to the next page by either double-clicking the option name or by pressing the "Next" button. There you are prompted to enter the location of the ATDB file you want to import. Click the upper "Browse..." button to navigate your file system and select the wanted file. If you want to change the target project the model will be created in press the lower "Browse..." button and make your choice. The figure above shows an example input.</p>
+		<p>
+			<strong>Step 4</strong>
+		</p>
+		<p>
+			<img src="images/atdb_import_result.png"/>
+		</p>
+		<p>After you have made all required inputs, click on "Finish". This will start the analysis of the database. Once the model creation is done the dialogue will close and the newly created amxmi file opened on the AMALTHEA Model editor as shown in the figure above.</p>
+
+
+<h2><a id="section2.5">2.5 </a>Editors / Viewers</h2>
+
+
+<h3><a id="section2.5.1">2.5.1 </a>AMALTHEA Trace Database Metrics Viewer</h3>
+		<p>This is a simple viewer that shows how to access the AMALTHEA trace database.</p>
+		<p>
+			<img src="images/metric-viewer_open.png"/>
+		</p>
+		<p>
+			<img src="images/metric-viewer_table.png"/>
+		</p>
+
+
+<h3><a id="section2.5.2">2.5.2 </a>Sirius Viewer</h3>
+		<p>Basic graphical viewers are realized using 
+			<a href="https://www.eclipse.org/sirius/">Sirius</a>.
+		</p>
+		<p>The following viewers are treated as a POC (Proof of concept) and are not final.
+			<br>They can be extended and further developed to show additional parts of the model.
+		</p>
+
+
+<h4><a id="section2.5.2.1"></a>Activate capabilities for project</h4>
+		<p>The following steps will activate the Sirius feature and AMALTHEA viewpoints:</p>
+		<p>To use Sirius, projects needs to have the 
+			<i>Modeling Feature</i> enabled. This can be done by right clicking on the project and select 
+			<strong>Configure – Convert to Modeling Project</strong>. Note that a new file 
+			<i>representations.aird</i> is created at top level of the project. This file is containing the user created diagrams.
+		</p>
+		<p>
+			<img src="images/sirius_convert_project.png"/>
+		</p>
+		<p>Activate the AMALTHEA viewpoint by right click on the project and select 
+			<strong>Viewpoint Selection</strong>. 
+		</p>
+		<p>
+			<img src="images/sirius_viewpoints_selection.png"/>
+		</p>
+		<p>
+			<b>Note:</b> Using one of the available commands to open a view using a right click on an element automatically adds the Modeling Nature and selects the available AMALTHEA viewpoint.
+		</p>
+
+
+<h4><a id="section2.5.2.2"></a>Available Diagrams</h4>
+
+
+<h5><a id="section2.5.2.2.1"></a>Task View</h5>
+		<p>The current version of the Task View shows the Task as a container with the included Runnables.</p>
+		<p>Open/Create a view for a 
+			<i>Task</i> element by right click on it and select 
+			<i>Task View</i>.
+		</p>
+		<p>
+			<img src="images/sirius_task_view_create.png"/>
+		</p>
+		<p>A new diagram is shown based on the given 
+			<i>Task</i> element.
+		</p>
+		<p>
+			<img src="images/sirius_task_view_1.png"/>
+		</p>
+
+
+<h6><a id="section2.5.2.2.1.1"></a>Communication Layer</h6>
+		<p>The Communication Layer shows direct dependencies between 
+			<i>Runnables</i>. Therefore the following requirement must be fulfilled:
+		</p>
+		<ol>
+			<li>Runnable R1 writes Label L1</li>
+			<li>Runnable R2 reads Label L1</li>
+		</ol>
+		<p>Enable it through the Layers option menu.</p>
+		<p>
+			<img src="images/sirius_task_view_comm_layer_enable.png"/>
+		</p>
+		<p>In this sample some of the available communications are fulfilling this requirement.</p>
+		<p>
+			<img src="images/sirius_task_view_comm_layer_show1.png"/>
+		</p>
+
+
+<h6><a id="section2.5.2.2.1.2"></a>Label Layer</h6>
+		<p>The Label Layer shows all Read/Write dependencies between 
+			<i>Runnables</i> and 
+			<i>Labels</i>.
+		</p>
+		<p>Enable it through the Layers option menu.</p>
+		<p>
+			<img src="images/sirius_task_view_label_layer_enable.png"/>
+		</p>
+		<p>After some arrangement it can look like the following:</p>
+		<p>
+			<img src="images/sirius_task_view_label_layer_show.png"/>
+		</p>
+
+
+<h5><a id="section2.5.2.2.2"></a>Label View</h5>
+		<p>The Label View shows a 
+			<i>Label</i> element including read/write accesses from corresponding 
+			<i>Runnables</i>.
+		</p>
+		<p>Open/Create a view for a 
+			<i>Label</i> element by right click on it and select 
+			<i>Label View</i>.
+		</p>
+		<p>
+			<img src="images/sirius_label_view_create.png"/>
+		</p>
+		<p>A new diagram is shown based on the given 
+			<i>Label</i> element.
+		</p>
+		<p>
+			<img src="images/sirius_label_view_1.png"/>
+		</p>
+
+
+<h5><a id="section2.5.2.2.3"></a>EventChain View</h5>
+		<p>The 
+			<i>EventChain</i> view is the first version to show the included 
+			<i>Events</i>.
+			<br>If there is a reference to a 
+			<i>RunnableEvent</i>, the corresponding 
+			<i>Runnable</i> is also shown.
+			<br>This behavior can be extended also for 
+			<i>Labels</i> and 
+			<i>Tasks</i> for example.
+		</p>
+		<p>Open/Create a view for an 
+			<i>EventChain</i> element by right click on it and select 
+			<i>Event Chain View</i>.
+		</p>
+		<p>
+			<img src="images/sirius_event_chain_view_create.png"/>
+		</p>
+		<p>A new diagram is opening showing the order of the included 
+			<i>Events</i>.
+			<br>If there is a 
+			<i>RunnableEvent</i>, the association to the 
+			<i>Runnable</i> includes the configured 
+			<i>EventType</i>.
+		</p>
+		<p>
+			<img src="images/sirius_event_chain_view_show.png"/>
+		</p>
+
+
+<h5><a id="section2.5.2.2.4"></a>Tasks View</h5>
+		<p>The 
+			<i>Tasks</i> view is in general the same view as the already mentioned 
+			<i>Task</i> view above with the advantage to get an overview about all included 
+			<i>Tasks</i> of a Software model.
+		</p>
+		<p>To open/create a Tasks view it is needed to switch to the Sirius perspective.</p>
+		<ul>
+			<li>This can be done by 
+				<b>Window – Perspective – Open Perspective – Other</b> and select then Sirius.
+			</li>
+			<li>On the left side inside of the Model Explorer go to an AMALTHEA model, expand it and do a right click on the 
+				<i>Software</i> model.
+			</li>
+			<li>Select 
+				<b>New Representation – new Tasks Overview</b> to create a new diagram.
+			</li>
+			<li>Change the name if needed and click on ok.</li>
+		</ul>
+		<p>The same additional options are available as in the normal 
+			<i>Task</i> view like the 
+			<i>Label Layer</i> and 
+			<i>Communication Layer</i>.
+		</p>
+		<p>
+			<img src="images/sirius_tasks_view_create.png"/>
+		</p>
+		<p>
+			<img src="images/sirius_tasks_view_show.png"/>
+		</p>
+
+
+<h5><a id="section2.5.2.2.5"></a>Mapping View</h5>
+		<p>The 
+			<i>Mapping</i> view gives an overview of the relation between 
+			<i>Cores</i>, 
+			<i>Schedulers</i> and 
+			<i>Tasks</i>, which is defined in the 
+			<i>Mapping Model</i> of AMALTHEA.
+		</p>
+		<p>To open/create a Tasks view it is needed to switch to the Sirius perspective.</p>
+		<ul>
+			<li>This can be done by 
+				<b>Window – Perspective – Open Perspective – Other</b> and select then Sirius.
+			</li>
+			<li>On the left side inside of the Model Explorer go to an AMALTHEA model, expand it and do a right click on the 
+				<i>Mapping</i> model.
+			</li>
+			<li>Select 
+				<b>New Representation – new Tasks Overview</b> to create a new diagram.
+			</li>
+			<li>Change the name if needed and click on ok.</li>
+		</ul>
+		<p>
+			<img src="images/sirius_mapping_view_create.png"/>
+		</p>
+		<p>
+			<img src="images/sirius_mapping_view_show.png"/>
+		</p>
+
+
+<h2><a id="section2.6">2.6 </a>Model Validation</h2>
+
+
+<h3><a id="section2.6.1">2.6.1 </a>Usage of Check-based Validation</h3>
+		<p>The AMALTHEA validation can be triggered by right clicking a model element in the left Model Explorer View and choose in the context menu Validate – Check-based Validation.</p>
+		<p>
+			<img class="gray" src="images/sphinx_validation_trigger_command.png"/>
+		</p>
+		<p>All AMALTHEA sub elements of the chosen element are then included for the validation. In the next window the catalog appears allowing the selection of specific validation checks based on your selected model. Button "Select All" will select all listed validation checks for execution. Each entry of the catalog is called 
+			<i>Category</i> which may contain several validation checks (i.e. constraints). The simplest way is to define a 1:1 relationship between category and constraint.
+		</p>
+		<p>
+			<img src="images/sphinx_validation_selection.png"/>
+		</p>
+		<p>If an error is found, it is shown in the Problems view of Eclipse. A simple double click on the error will lead you to the affected elements in the AMALTHEA model. Sphinx validation distinguishes between three error types: 
+			<i>errors</i>, 
+			<i>warnings</i> and 
+			<i>info</i>.
+		</p>
+		<p>
+			<img class="gray" src="images/sphinx_validation_results.png"/>
+		</p>
+
+
+<h3><a id="section2.6.2">2.6.2 </a>Available Validations</h3>
+		<p>The plugin 
+			<i>org.eclipse.app4mc.amalthea.validation</i> contains several validators and constraints (i.e. checks) for various model types of AMALTHEA.
+		</p>
+
+
+<h4><a id="section2.6.2.1"></a>Basic Check Validator</h4>
+		<p>Basic checks which cannot be assigned to a specific AMALTHEA model are summarized. Responsible implementation for this validation is the class 
+			<code>org.eclipse.app4mc.amalthea.validation.checks.BasicCheckValidator</code>.
+		</p>
+		<p>
+			<b>Missing Referable Name</b>
+			<br>Checks the name of all objects that are instances of 
+			<code>IReferable</code>. The name is used to refer to objects in the AMALTHEA model, therefore missing names are handled as an 
+			<b>
+				<i>error</i>
+			</b>.
+		</p>
+		<p>
+			<b>Duplicate Unique Name</b>
+			<br>Checks the unique name of all objects that are instances of 
+			<code>IReferable</code>. The unique name is used to refer to objects in the AMALTHEA model, therefore duplicates are handled as an 
+			<b>
+				<i>error</i>
+			</b>.
+		</p>
+		<p>
+			<b>Undefined Unit</b>
+			<br>Checks all units: 
+			<code>TimeUnit</code>, 
+			<code>FrequencyUnit</code>, 
+			<code>DataSizeUnit</code>, 
+			<code>DataRateUnit</code>.
+			<br>If the unit is undefined, it will be handled as an 
+			<b>
+				<i>error</i>
+			</b>.
+		</p>
+		<p>
+			<b>Custom Property Duplicate Key</b>
+			<br>A validation to check all custom attributes of one element. If it contains duplicate key entries, it is treated as a 
+			<b>
+				<i>warning</i>
+			</b>.
+		</p>
+		<p>
+			<b>Weibull Parameters</b>
+			<br>Checks the parameters in the 
+			<i>Distribution</i> of type 
+			<i>WeibullEstimators</i>. The parameters must not be equal to each other, if this is the case, it will be handled as an 
+			<b>
+				<i>warning</i>
+			</b>.
+		</p>
+
+
+<h4><a id="section2.6.2.2"></a>ConstraintsModel Check Validator</h4>
+		<p>Responsible implementation for this validation is the class 
+			<code>org.eclipse.app4mc.amalthea.validation.checks.ConstraintsModelCheckValidator</code>.
+		</p>
+		<p>
+			<b>EventChainsConstraint</b>
+			<br>Checks for the AMALTHEA constraints model if the 
+			<i>EventChains</i> are consistent regarding completeness (fully build chain) and correctness. Therefore each EventChain's stimulus/response pair is checked if events are existent and linked properly to a complete chain. An event chain of type 
+			<i>SubEventChain</i> is checked for its "border" events fit to the stimulus and response event of the parent event chain. Cascades of sub events are processed recursively. A missing or wrong information in the event chain will be handled as an 
+			<b>
+				<i>error</i>
+			</b>. 
+		</p>
+
+
+<h4><a id="section2.6.2.3"></a>MappingModel Check Validator</h4>
+		<p>Responsible implementation for this validation is the class 
+			<code>org.eclipse.app4mc.amalthea.validation.checks.MappingModelCheckValidator</code>.
+		</p>
+		<p>
+			<b>Process2Scheduler2CoreMappingConstraint</b>
+			<br>Checks for the entire AMALTHEA model instance if the mapping information are complete and correct between 
+			<i>Software</i>(SW) &lt;-&gt; 
+			<i>Operating System</i>(OS) &lt;-&gt; 
+			<i>Software</i>(SW) model. I.e. mapping relationship {Process(SW) to Scheduler(OS) to Core(HW)}. A missing mapping information (i.e. no Entity) or unmapped Processes will be handled as an 
+			<b>
+				<i>error</i>
+			</b>.
+		</p>
+
+
+<h4><a id="section2.6.2.4"></a>EventModel Check Validator</h4>
+		<p>Responsible implementation for this validation is the class 
+			<code>org.eclipse.app4mc.amalthea.validation.checks.EventModelCheckValidator</code>.
+		</p>
+		<p>
+			<i>to be extended</i>
+		</p>
+
+
+<h4><a id="section2.6.2.5"></a>HardwareModel Check Validator</h4>
+		<p>Responsible implementation for this validation is the class 
+			<code>org.eclipse.app4mc.amalthea.validation.checks.HardwareModelCheckValidator</code>.
+		</p>
+		<p>
+			<i>to be extended</i>
+		</p>
+
+
+<h2><a id="section2.7">2.7 </a>Model Migration</h2>
+
+
+<h3><a id="section2.7.1">2.7.1 </a>AMALTHEA Model Migration</h3>
+
+
+<h4><a id="section2.7.1.1"></a>Why model migration is required ?</h4>
+		<p>EMF based models are the instances of ECORE meta model (which is updated for each release). </p>
+		<p>As there is a tight dependency between model instance and the corresponding meta model, old EMF models can not be loaded with the newer release of meta model.</p>
+		<blockquote>
+			<p>Example : Due to the change in the namespace of the meta model, loading of model files from prior versions would fail with the latest version</p>
+		</blockquote>
+		<p>This problem can be solved by explicitly migrating the model files from the prior versions to be compatible to the latest meta model version</p>
+
+
+<h4><a id="section2.7.1.2"></a>AMALTHEA model migration</h4>
+		<p>As described above, same scenario is also applicable for AMALTHEA models as they are instances of EMF based AMALTHEA ECORE meta model.</p>
+		<p>For each release of AMALTHEA there will be changes in the meta model contents, due to this it is not possible to load models built from previous releases of AMALTHEA into latest tool distribution.</p>
+		<p>
+			<strong>Model Migration functionality</strong> is part of this distribution, using this feature it is possible to convert models from previous releases (e.g. itea.1.0.3, itea.1.1.0, itea.1.1.1, 0.7.0, 0.7.1, 0.7.2, 0.8.0, 0.8.1, 0.8.2,0.8.3) to the ones which are compatible to the next versions of AMALTHEA meta model.
+		</p>
+		<p>
+			<em>Only forward migration of models is supported by Model Migration functionality of AMALTHEA</em>
+		</p>
+
+
+<h3><a id="section2.7.2">2.7.2 </a>Supported versions for model Migration</h3>
+		<p>Model migration functionality provides a possibility to migrate the models (
+			<em>created from previous releases of AMALTHEA</em> ) to the latest versions
+		</p>
+		<p>
+			<em>Only forward migration is supported</em>
+		</p>
+		<p>
+			<b>AMALTHEA meta model versions information</b>
+		</p>
+		<p>Below were the releases of AMALTHEA meta model during its phase of being as a ITEA2 funded project ( For details refer : 
+			<a href="http://www.amalthea-project.org/index.php/roadmap">www.amalthea-project.org</a> )
+		</p>
+		<ul>
+			<li>1.0.3</li>
+			<li>1.1.0</li>
+			<li>1.1.1</li>
+		</ul>
+		<p>From below version, AMALTHEA meta model is a part of the official  project Eclipse APP4MC ( See: 
+			<a href="https://www.eclipse.org/app4mc">www.eclipse.org/app4mc</a> )
+		</p>
+		<ul>
+			<li>0.7.0</li>
+		</ul>
+		<p>
+			<b>Model migration</b>
+		</p>
+		<p>As described above, only forward migration is supported by the AMALTHEA model migration utility.</p>
+		<p>Model migration utility migrates the specified model sequentially to the next versions (step by step) till expected version is reached.</p>
+		<p>Below figure represents the steps involved in the migration of model from ITEA2 1.0.3 version to APP4MC 0.7.0 version:</p>
+		<p>
+			<img class="scale" src="images/migration_flow.png"/>
+		</p>
+
+
+<h3><a id="section2.7.3">2.7.3 </a>Pre-requisites for AMALTHEA model migration</h3>
+
+
+<h4 id="migration-vm-args"><a id="section2.7.3.1"></a>VM arguments</h4>
+		<p>Default max heap memory (Xmx) used by the APP4MC distribution is 2 GB. In case of migrating huge models, it is recommended to increase this memory to 4 GB before invocation of "AMALTHEA Model Migration" feature</p>
+		<p>Follow the below steps to increase the heap memory setting of APP4MC :</p>
+		<ul>
+			<li>Open 
+				<strong>app4mc.ini</strong> file (
+				<em>present in the location where APP4MC is installed</em>) and change the parameter -Xmx from 2g to 4g. (
+				<em>
+					<strong>Note</strong>: In case if APP4MC plugins are integrated inside custom eclipse application, then corresponding &lt;application_name&gt;.ini file -Xmx parameter should be updated as specified below
+				</em>)
+			</li>
+		</ul>
+		<img class="gray_scale" src="images/vm_arguments_configuration.png"/>
+
+
+<h4 id="migration-linked-files"><a id="section2.7.3.2"></a>Linked files in eclipse project (virtual files)</h4>
+		<p>In case you want to have linked files in eclipse project, during the drag and drop of the files select 
+			<strong>"Link to files"</strong> option in 
+			<em>
+				<strong>File Operation</strong>
+			</em> dialog and uncheck 
+			<em>
+				<strong>create link locations relative to</strong>
+			</em> option
+		</p>
+		<img class="gray_scale" src="images/linked_files_creation.png"/>
+
+
+<h4 id="migration-uuid"><a id="section2.7.3.3"></a>Usage of UUID's instead of URI fragments inside AMALTHEA models</h4>
+		<p>It is recommended that AMALTHEA models (1.0.3 and 1.1.0 versions) have UUID's instead of Xpath like URI fragments for identifying the elements.</p>
+		<p>
+			<strong>
+				<em>Note:</em>
+			</strong> Default referencing mechanism within an EMF model or across models is to have Xpath like URI fragments (example : "//@stimuliModel/@stimuli.9") but this is not recommended when the model elements are modified through external mechanism (
+			<em>instead of standard EMF editors</em>) as it is quite challenging to update index order and references accordingly.
+		</p>
+		<p>
+			<strong>Model files generated by AMALTHEA (1.0.3) /Amalthea4Public (1.1.0) IDE contains UUID instead of Xpath like URI fragments. From Amalthea4Public (1.1.1), custom URI fragments are introduced which are based on the element names rather than index</strong>
+		</p>
+
+
+<h5><a id="section2.7.3.3.1"></a>How to identify if Xpath like URI fragments are used in AMALTHEA model files</h5>
+		<p>Open AMALTHEA model files in text editor  </p>
+		<ul>
+			<li>search if xmi:id attribute is present for the tags</li>
+			<li>search for String : "//@" , if the search result consists of this kind of Strings 
+				<code>"//@stimuliModel/@stimuli.9"</code> 
+			</li>
+		</ul>
+		<p>If the results of "xmi:id" are false and "//@" are true, this means - &gt; URI fragments are used in the AMALTHEA model files</p>
+
+
+<h5><a id="section2.7.3.3.2"></a>How to identify if UUID's are used in AMALTHEA model files</h5>
+		<p>Open AMALTHEA model files in text editor  </p>
+		<ul>
+			<li>search if xmi:id attribute is present for the tags</li>
+		</ul>
+		<p>If model elements consists of xmi:id attributes for their identification and for referencing, model content looks like below:  </p>
+		<p>
+			<code>&lt;calls xsi:type="sw:TaskRunnableCall" xmi:id="_FddJyEJsEeW3445fEkSwWQ" runnable="_FeWjyUJsEeW3445fEkSwWQ"/&gt;</code>
+		</p>
+
+
+<h5><a id="section2.7.3.3.3"></a>Update AMALTHEA models to use UUID's instead of Xpath like URI fragments</h5>
+		<p>Once it is identified that models contain Xpath like URI fragments, it is recommended to update them to have UUID's before invoking model migration.</p>
+		<p>For update of models to have UUID's,  use one of the below plugin (depending on the model version) and execute it in the corresponding AMALTHEA distribution to which model is belonging to</p>
+		<table class="classic">
+			<tr>
+				<td colspan="1" rowspan="1">
+					<strong>AMALTHEA Model Version</strong>
+				</td>
+				<td colspan="1" rowspan="1">
+					<strong>Utility plugin to convert URI Fragments to UUID's</strong>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">1.0.3</td>
+				<td colspan="1" rowspan="1"><div><a href="zip/1.0.3_org.itea2.amalthea.urifragments.converter.zip">download : 1.0.3 AMALTHEA models converter</a> </div></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">1.1.0</td>
+				<td colspan="1" rowspan="1"><div><a href="zip/1.1.0_org.itea2.amalthea.urifragments.converter.zip">download : 1.1.0 AMALTHEA models converter</a> </div></td>
+			</tr>
+		</table>
+		<p>Follow the below steps to convert URI Fragments to UUID's:</p>
+		<ol>
+			<li>Import the dowloaded utility plugin into corresponding AMALTHEA distribution <br><br> 
+				<img class="gray_scale" src="images/import.png"/> <br><br>
+				<ul>
+					<li>Select the option "Existing Projects into Workspace" <br><br> 
+						<img class="gray_scale" src="images/import_existing_projects.png"/> <br><br>
+					</li>
+					<li>Select the location of zip file (downloaded utility plugin) <br><br> 
+						<img class="gray_scale" src="images/select_project_to_import.png"/> <br><br>
+					</li>
+				</ul>
+			</li>
+			<li>Open the models folder in the project - &gt; remove the existing models and copy the models which should be updated for UUID's  (
+				<em>It is important to have all the models and the dependent models copied with the same folder structure</em>) <br><br> 
+				<img class="gray_scale" src="images/copy_models.png"/> <br><br>
+			</li>
+			<li>Configuring the copied models to be considered for UUID's updation : <br><br> 
+				<img class="gray_scale" src="images/configuring_models_mwe2.png"/> <br><br>
+			</li>
+			<li>Executing workflow to update the Amalthea models : <br><br> 
+				<img class="gray_scale" src="images/execute_workflow.png"/> <br><br>
+			</li>
+			<li>Updated model files (with UUID's) will overwrite the input models. 
+				<strong>These model files should be used for model migration</strong>
+			</li>
+		</ol>
+		<p>
+			<strong>Special behavior</strong>
+		</p>
+		<p>During the UUID update process following behavior is performed:</p>
+		<ul>
+			<li>If AMALTHEA model elements are referring to Franca Interfaces, references are removed but the content of the reference is copied as CustomProperty for FInterfacePort element <br><br> 
+				<img class="gray_scale" src="images/franca_interface_handling.png"/> <br><br>
+			</li>
+		</ul>
+
+
+<h3><a id="section2.7.4">2.7.4 </a>How to invoke AMALTHEA model migration</h3>
+		<p>AMALTHEA model migration utility is developed as a eclipse plugin and it is part of APP4MC distribution (
+			<em>from release 0.7.0</em>)
+		</p>
+		<p>Model migration utility can be invoked by selecting the required models to be migrated in the UI and specifying the target AMALTHEA version to which models should be migrated</p>
+		<ul>
+			<li>
+				<b>Step 1:</b> Selection of AMALTHEA models
+			</li>
+		</ul>
+		<p>
+			<img class="gray_scale" src="images/models_selection.png"/>
+		</p>
+		<ul>
+			<li>
+				<strong>Step 2:</strong> Opening AMALTHEA Model Migration dialog and configuring migration inputs
+			</li>
+		</ul>
+		<p>On click of AMALTHEA Model Migration action, selected files are parsed and the following information is retrieved:</p>
+		<ol>
+			<li>AMALTHEA model version to which model is belonging to</li>
+			<li>Referred AMALTHEA models inside the selected model (
+				<em>i.e. case of cross document references</em>) 
+				<ul>
+					<li>AMALTHEA model version to which these models are belonging to</li>
+				</ul>
+			</li>
+		</ol>
+		<p>Once the above information is successfully retrieved, following Model Migration dialog is opened:</p>
+		<p>
+			<img class="gray_scale" src="images/migration_dialog.png"/>
+		</p>
+		<p>Model Migration dialog consists of following information:</p>
+		<ol>
+			<li>Selected AMALTHEA model files : These are the models which are explicitly selected by the user</li>
+			<li>Model scope files : These are the model files which are referred in the models explicitly selected by the user <div>
+				<em>Example:</em> In the dialog shown above, mapping.amxmi is the file selected by the user, and it contains references to the model elements of : sw.amxmi, sw.amxmi-sw, default.amxmi-os. Due to this reason, all these referred models are selected implicitly for model migration <br>
+				<strong>
+					<em>Note:</em>
+				</strong> In case if the selected/referred models are having the different AMALTHEA model versions, migration can not be proceeded and the following error dialog is displayed <br> 
+				<img class="gray_scale" src="images/different_model_versions.png"/> </div>
+			</li>
+			<li>Input model version : This is the AMALTHEA model version to which both selected &amp; referred models are belonging to <br><div> 
+				<strong>
+					<em>Note:</em>
+				</strong> AMALTHEA model versions are represented with the following naming convention in this dialog<br><table id="classic"><tr><td colspan="1" rowspan="1">AMALTHEA 1.0.3</td><td colspan="1" rowspan="1">itea.103</td></tr><tr><td colspan="1" rowspan="1">AMALTHEA4public 1.1.0</td><td colspan="1" rowspan="1">itea.110</td></tr><tr><td colspan="1" rowspan="1">AMALTHEA4public 1.1.1</td><td colspan="1" rowspan="1">itea.111</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.7.0</td><td colspan="1" rowspan="1">0.7.0</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.7.1</td><td colspan="1" rowspan="1">0.7.1</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.7.2</td><td colspan="1" rowspan="1">0.7.2</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.8.0</td><td colspan="1" rowspan="1">0.8.0</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.8.1</td><td colspan="1" rowspan="1">0.8.1</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.8.2</td><td colspan="1" rowspan="1">0.8.2</td></tr><tr><td colspan="1" rowspan="1">APP4MC 0.8.3</td><td colspan="1" rowspan="1">0.8.3</td></tr></table><br></div>
+			</li>
+			<li>Output model version : This is the AMALTHEA model version to which both selected &amp; referred models should be migrated to</li>
+			<li>Output directory : This is the location where migrated AMALTHEA models should be generated. <div>
+				<strong>
+					<em>Note:</em>
+				</strong> <u>This option is available only if the specified output model version is 1.1.1 or higher.</u><br> In case of AMALTHEA model versions 1.0.3 and 1.1.0 - &gt; Model scope is set as project, where as from version 1.1.1 and higher - &gt; model scope is limited to a folder. Due to this reason below is the behavior of model migration utility : <ul><li>If the output model version is selected as 1.1.1 or higher - &gt; <u>migrated models are generated in a single folder (due to scope restriction) specified by the user</u></li><li>If the output model version is selected as 1.1.0 - &gt; <u>input model files will be overwritten by the migrated model files</u></li></ul></div>
+			</li>
+		</ol>
+		<ul>
+			<li>
+				<strong>Step 3:</strong> Model migration
+			</li>
+		</ul>
+		<p>Once the required parameters are configured in the model migration dialog, click on "Migrate Models" button in the dialog to invoke migration.</p>
+		<p>
+			<strong>Special cases:</strong>
+		</p>
+		<ul>
+			<li>
+				<strong>Handling of input model files with name in the following format :</strong> &lt;model name&gt;.amxmi-&lt;sub model name&gt; (
+				<em>Example: test.amxmi-sw</em>)
+				<ul>
+					<li>From 1.1.1 version, files of these extension are not recognized by the AMALTHEA loader as AMALTHEA models, due to this reason if such files are supplied as input to model migration utility - &gt; generated files will be of following convention  &lt;model name&gt;.amxmi-&lt;sub model name&gt;.amxmi (
+						<em>Example: test.amxmi-sw.amxmi</em>). <div>For details refer to the below image containing both input models and migrated models :<br> 
+						<img class="gray_scale" src="images/generated_model_file_names.png"/></div>
+					</li>
+				</ul>
+			</li>
+		</ul>
+
+
+<h3><a id="section2.7.5">2.7.5 </a>Additional details</h3>
+		<p>For details regarding the below topics, refer to the corresponding links:</p>
+		<ol>
+			<li>
+				<a href="#metamodel-changes">How model elements are migrated across various versions ?</a>
+			</li>
+			<li>
+				<a href="#migration-uuid">How to update models to contain UUID ?</a>
+			</li>
+			<li>
+				<a href="#migration-vm-args">How to update max heap memory used by the application ?</a>
+			</li>
+		</ol>
+
+
+<h2><a id="section2.8">2.8 </a>Partitioning</h2>
+		<p>The AMALTHEA partitioning approach supports various features, which can be combined and configured in order to exploit software parallelism in various ways. Besides mandatory model enhancements such as the label access analysis leading to a constraints model with 
+			<code>RunnableSequencingConstraints</code> and the cycle elimination to provide directed acyclic graphs, features like activation grouping or the independent graph grouping can be optionally performed. Subsequently, one of two different partitioning approaches can be performed, that cut the created graphs into partitions (
+			<code>ProcessPrototypes</code>) that can later be transformed to tasks. These tasks can be efficiently executed in parallel on a target platform, since ordering constraints are considered and task execution time and inter task communications are minimized. On the one hand, the 
+			<i>CPP</i> approach performs graph theoretical mechanisms to initially reveal a critical path of 
+			<code>runnables</code> (also denoted as nodes) and dependencies (also denoted as edges) from a source node to a sink node. That initial path is assigned to the first partition and branch nodes are identified and assigned to additional tasks with respect to order constraints, execution cycles and communication overheads. This partitioning approach provides an automatic 
+			<code>runnable</code> distribution resulting in an efficient parallelism factor with respect to an unbounded number of tasks and causal runnable orders i.e. dependencies. On the other hand, the 
+			<i>ESSP</i> partitioning approach performs a timing based partitioning with respect to a bounded number of partitions (configurable by the user), since this case is often mandatory in order to meet system requirements. Both approaches therefore read, adapt and write AMALTHEA specific constraints and software models and express the first approaches within the AMALTHEA platform to automatically exploit system parallelism and utilize parallel resources. The user benefits from not manually assigning runnables to tasks through a complex, error prone and time consuming process but triggering a configurable partitioning approach, that automatically performs that assignment using different algorithms for various optimizing criteria in order to distribute existing software effectively.
+		</p>
+
+
+<h3><a id="section2.8.1">2.8.1 </a>Usage of Partitioning</h3>
+		<p>The following configuration window shows the different features, which are available for the partitioning process.</p>
+		<p>
+			<img src="images/config.png"/>
+		</p>
+		<p>Each process is described in the following sections.</p>
+		<p>In order to start the partitioning, the user should right click on an 
+			<i>.amxmi</i> file and select the 
+			<i>Perform Partitioning</i> command as shown in the following figure. 
+			<br>
+			<img src="images/click_small.png"/>
+		</p>
+		<p>Alternatively, a workflow can be written (e.g. using the 
+			<i>EASE</i> script technology) to start the partitioning process and further define various workflows for different inputs and outputs (see example at this partitioning help's end).
+		</p>
+		<p>With regard to the partitioning configuration, the partitioning process will perform various model adaptations as shown in the following figure and described in the next sections.</p>
+		<p>
+			<img class="scale" src="images/psteps_small.png"/>
+		</p>
+
+
+<h3><a id="section2.8.2">2.8.2 </a>Pre-Partitioning</h3>
+		<p>In order to perform the actual partitioning based on <i>DAWG</i>s (directed acyclic weighted graphs), various processing needs to be performed on the given input i.e. a set of runnables with label accesses, execution cycles and activations. Required processing are creating a constraints model with 
+			<code>RunnableSequencingConstraints</code> and cycle elimination that creates 
+			<code>AccessPrecedences</code> for each dependency that needs to be decomposed from a 
+			<code>RunnableSequencingConstraint</code> to eliminate one or more cycles. Further adaptations can create 
+			<code>ProcessPrototypes</code> in order to group runnables based on activation references or based on independent graphs.
+		</p>
+
+
+<h4><a id="section2.8.2.1"></a>Label Access Analysis</h4>
+		<p>The label access analysis comprises the comparison of 
+			<i>read</i> and 
+			<i>write</i> accesses of all runnables for identifying dependencies. For example, in case runnable 
+			<i>A</i> writes a label and another runnable 
+			<i>B</i> reads the same label, runnable 
+			<i>B</i> depends on runnable 
+			<i>A</i>. This dependency is saved as a 
+			<code>RunnableSequencingConstraint</code>. Such 
+			<code>RunnableSequencingConstraint</code> is the basis for performing a 
+			<i>DAG</i> (directed acyclic graph) analysis and allows the determination of concurrency due to giving information about fork and join dependencies respectively 
+			<code>runnables</code> that can be calculated in parallel. Furthermore, the label access analysis allows deriving memory structure via common data accesses. The 
+			<code>RunnableSequencingConstraints</code> are stored within a new or an existing constraints model. An example is given in the following picture:
+		</p>
+		<p>
+			<img src="images/dependency_new.png"/>
+		</p>
+
+
+<h4><a id="section2.8.2.2"></a>Cycle Elimination</h4>
+		<p>The cycle elimination is a mandatory step for all subsequent methods and features. Topological and graph theoretical calculations require <i>DAWG</i>s, such that a cycle elimination has to be performed in advance. A cycle may occur in case two runnables share the same resource (label) in both directions, i.e. both runnables read and write the same label, or in case runnable 
+			<i>A</i> reads label 
+			<i>BA</i> and writes label 
+			<i>AB</i> and runnable 
+			<i>B</i> reads label 
+			<i>AB</i> and writes label 
+			<i>BA</i>. Furthermore, a cycle may be formed across multiple runnables. For the purpose of finding such cycles, the external 
+			<i>JgraphT</i> library has been added to the project, that supports finding all of these cycles. After all cycles have been identified, a specific mechanism (configurable through 'Minimal dependency decompositions for cycle elimination' in the preference page) detects edges (dependencies), which occur in multiple cycles. This mechanism iterates over edges within multiple cycles in descending order, i.e. it starts with an edge, that occurs in most cycles for ensuring minimal edge elimination. In order to retain a dependency that has been selected for elimination, such selected edges are transformed from a 
+			<code>RunnableSequencingConstraint</code> to an 
+			<code>AccessPrecedence</code>. After edge sharing cycles have been decomposed, all cycles that do not share any edges have to be decomposed as well. For each of these cycles an edge can be identified that provides an optimal retaining graph (configurable through 'Increase parallelization potential for cycle elimination result' in the preference page). The following figure shows 7 cycle elimination possibilities with an example graph.
+			<br>
+			<img class="scale" src="images/cycle_small.png"/>
+			<br>Red transitions indicate edges, that are decomposed into 
+			<code>AccessPrecedences</code> for the corresponding solution. Rretaining graphs are shown on the right side of each solution indicated by a dashed rectangle. For illustration purposes, we assume equal execution time for each runnable (letter). Solution 1 and 5 (green dashed rectangles) feature the minimal runtime for two tasks. This assessment is made with respect to topological graph structure respectively the 
+			<i>span</i> of a graph (critical path) compared with its 
+			<i>parallelism</i>.
+		</p>
+
+
+<h4><a id="section2.8.2.3"></a>Activation Partitioning</h4>
+		<p>Typical for embedded software, code fragments need to be executed within different intervals i.e. timers, interrupts or events. Sensors or actuators for example must often be read within short intervals for precise and accurate executions. Contrarily, certain processing fragments independent from the system's stability can be executed at greater intervals due to having less impact on the system's performance. Such activations can either be referenced by tasks via the stimulation model or by runnables via activations in the software model. By assessing these model entities and references, temporal classification can be implied. The activation analysis feature creates 
+			<code>ProcessPrototypes</code> for each activation and assigns referencing runnables correspondingly via creating 
+			<code>TaskRunnableCalls</code> within the 
+			<code>ProcessPrototypes</code>.
+		</p>
+
+
+<h4><a id="section2.8.2.4"></a>Independent Graph Partitioning</h4>
+		<p>The independent graph identification process, or also denoted as global graph partitioning, can be executed after the cycle elimination in case the user selected the corresponding entry in the configurations ('Create independent graph partitions'). This methodology looks for graphs or single nodes, that do not share any label with other runnables or complete graphs that do not share labels with other graphs. Such methodology allows forming tasks, which can be totally distributed to either different cores or even to totally different systems as seen in the following figure:</p>
+		<p>
+			<img class="scale" src="images/ggp_small.png"/>
+		</p>
+
+
+<h4><a id="section2.8.2.5"></a>Tag Partitioning</h4>
+		<p>Tags can be used to group runnables similar to the 
+			<i>Activation Partitioning</i> approach. A typical use case of tags are software components. This mechanism provides the user with any type of grouping in order to keep related runnables within the same partition respectively task.  
+		</p>
+
+
+<h4><a id="section2.8.2.6"></a>ASIL-level Partitioning</h4>
+		<p>
+			<code>ASIL-levels</code> and 
+			<code>Tags</code> (e.g., for software components) are equally considered such that separate groups are formed prior to the partitioning process, which always splits the most instructions consuming partition first. Consequently, generated partitions are aligned regarding their instruction sums as much as possible. In other words, all runnables referencing the same tag are grouped into a partition that may be split further if the sum of all runnables contained in this group is higher than other the instruction sums at other partitions. An important aspect of this mechanism is its influence of the overall software distribution. In order to keep the amount of generated 
+			<code>AccessPrecedencs</code> (i.e., a dissolution of a direct cause and effect relation of two runnables) low, i.e., to keep the program's causality at a high level, existing groups can me merged with other groups or partitions. 
+		</p>
+
+
+<h4><a id="section2.8.2.7"></a>Consideration of Runnable Pairing Constraints</h4>
+		<p>The folowing figure outlines the consideration of 
+			<code>RunnablePairingConstraints</code> via runnable cumulation. 
+			<br>
+			<img class="scale" src="images/pairing_small.png"/>
+			<br>Any 
+			<code>RunnablePairingConstraints</code> merges the corresponding runnables for the subsequent graph algorithms (cumulation) and decomposes (reconstruction) to the original structure after partitions have been formed. Consequently, causality, i.e., the runnable pairing positions and sequences within the partitions are considered.
+		</p>
+
+
+<h3><a id="section2.8.3">2.8.3 </a>Partitioning Algorithms</h3>
+		<p>Each of the algorithms described in the following creates ProcessPrototypes i.e. task precursor. </p>
+
+
+<h4><a id="section2.8.3.1"></a>Critical Path Partitioning (CPP)</h4>
+		<p>The 
+			<i>CPP</i> approach considers node weights (i.e. arbitrary computation / execution cycles / instructions of 
+			<code>runnables</code>) and partitions <i>DAWG</i>s, whereas 
+			<code>runnables</code> are equally distributed among an automatically determined number of partitions. The partitioning's objective is to reduce overall execution time and inter-task communication. The subsequent mapping methodology further considers resource constraints (availability of hardware and software resources namely program and data memory). The system's critical path is assigned to the first partition and branches of the graph are subsequently assigned to additional partitions. The approach has been chosen, because the critical path features mandatory sequential ordering, that cannot be computed in parallel. Thus, the weight of a critical path provides a lower bound on the total time to perform all the jobs. A 
+			<i>CPP</i> example is shown in the following figure (left = input graph; right = partitioning result):
+		</p>
+		<p>
+			<img class="scale" src="images/cpp_small.png"/>
+		</p>
+
+
+<h4><a id="section2.8.3.2"></a>Earliest Start Schedule Partitioning (ESSP)</h4>
+		<p>The 
+			<i>ESSP</i> partitioning is developed for allowing the user to restrict the number of partitioning. This may be important and useful in very large systems in order to keep the task creation and task inter-communication costs low. The 
+			<i>ESSP</i> partitioning balances runnables across partitions with respect to their causal orders. For this purpose, only runnable's 
+			<code>eit</code> (earliest initial time) -values are calculated that define the sum of the longest preceding path's instructions. The methodology picks the partition with the lowest schedule length, calculates a set of assignable 
+			<code>runnables</code>, which predecessors are already scheduled, and assigns a runnable to the current partition that minimizes the schedule length.
+		</p>
+
+
+<h3><a id="section2.8.4">2.8.4 </a>Further Features</h3>
+		<p>Two further features provide graph visualizations and a different graph representation through 
+			<code>RunnableSequencingConstraints</code>.
+		</p>
+
+
+<h4><a id="section2.8.4.1"></a>Applet Generation</h4>
+		<p>The applet generation can be triggered with a different command in the context menu via right-clicking on an 
+			<i>.amxmi</i> file. In case the file contains a software model with runnables and a constraints model with 
+			<code>RunnableSequencingConstraints</code>, a java file will be generated that can be executed as an applet with the help of the 
+			<i>JgraphT</i> library. Such an applet visualizes a graph and can be adapted in an applet viewer. The following figure shows such an applet.
+		</p>
+		<p>
+			<img class="scale" src="images/applet_small.png"/>
+		</p>
+
+
+<h4><a id="section2.8.4.2"></a>Dependency Alternative</h4>
+		<p>This file generation feature focuses on a constraints model approach that features a different dependency representation compared with the result from the label access analysis that always features two 
+			<code>RunnableGroups</code> with each one 
+			<code>RunnableGroupEntry</code> entity within a 
+			<code>RunnableSequencingConstraint</code>. The approach can be adapted to feature more 
+			<code>RunnableGroups</code> and more 
+			<code>RunnableGroupEntries</code> and a less amount of 
+			<code>RunnableSequencingConstraints</code>, derived from the same graph. An example is expressed in the following figure.
+		</p>
+		<p>
+			<img src="images/ta_small.png"/>
+		</p>
+
+
+<h3><a id="section2.8.5">2.8.5 </a>Partitioning Examples</h3>
+		<p>The following sections present some basic examples to illustrate the different 
+			<i>CPP</i> and 
+			<i>ESSP</i> results and further to provide an easy starting point for developers performing mutliple partitioning steps across mutlplie models via just a single start of an 
+			<i>EASE</i> script.
+		</p>
+
+
+<h4><a id="section2.8.5.1"></a>Algorithm Comparison</h4>
+		<p>The following figure illustrates the resulting partitions of the previously described algorithms based on an example graph shown on the left. On the right, the partitioning results are shown for (top) - 
+			<code>CPP</code>, (middle) - 
+			<code>ESSP</code> configured with 2 partitions and (bottom) - 
+			<code>ESSP</code> for 3 partitions.
+		</p>
+		<p>
+			<img class="scale" src="images/partexample.png"/>
+		</p>
+
+
+<h4><a id="section2.8.5.2"></a>Workflow Example</h4>
+		<p>The above described features can also be triggered via a workflow exemplarily shown in the following code (
+			<i>EASE</i> script):
+		</p>
+		<pre xml:space="preserve"><code>Workflow {
+//basic setup
+loadModule('/System/Resources')
+loadModule('/APP4MC/Workflow')
+
+//Importing needed packages
+importPackage(org.eclipse.app4mc.amalthea.workflow.component)
+importPackage(org.eclipse.app4mc.amalthea.workflow.core)
+importPackage(org.eclipse.app4mc.multicore.partitioning.workflow)
+
+//Configure logging
+addLoggerToConsole("org.eclipse.app4mc.multicore")
+addLoggerToConsole("org.eclipse.app4mc.amalthea.workflow")
+
+print("Starting Workflow ...")
+//general setup
+const BASE = "platform:/resource"
+const PROJECT = BASE + "/org.eclipse.app4mc.amalthea.example.democar.mapping"
+const MODEL_LOCATION1 = PROJECT + "/model/AMALTHEA_Democar_MappingExample.amxmi"
+
+var ctx = new DefaultContext()
+
+//Reader
+var reader = new ModelReader()
+reader.addFileName(MODEL_LOCATION1)
+reader.run(ctx)
+
+//prepartitioning
+var prepart = new PrePartitioningWrkflw()
+prepart.setAa(false)
+prepart.setGgp(false)
+prepart.setMinimEdge(false)
+prepart.setEffEdge(false)
+prepart.run(ctx)
+//result is saved in modelslot prePartitioning
+
+//Writer
+var writer = new ModelWriter()
+writer.setModelSlot("prePartitioning")
+writer.setFileName("prePartitioning")
+writer.setSingleFile(true)
+writer.setOutputDir(PROJECT + "/workflow-output")
+writer.run(ctx)
+
+//partitioning
+var part = new GeneratePartitioning()
+part.setModelLoc(MODEL_LOCATION1);
+part.setModelSlot("prePartitioning")
+part.setPartitioningAlg("essp")
+part.setNumberOfPartitions("4")
+part.run(ctx)
+
+//Writer
+var writer = new ModelWriter()
+writer.setModelSlot("partitioning")
+writer.setFileName("partitioning")
+writer.setSingleFile(true)
+writer.setOutputDir(PROJECT + "/workflow-output")
+writer.run(ctx)
+
+print("Finished Workflow")
+ctx.clear()
+endWorkflow()
+</code></pre>
+		<p><!-- --></p>
+
+
+<h3><a id="section2.8.6">2.8.6 </a>Plugin dependencies</h3>
+		<pre xml:space="preserve"><code>org.eclipse.core.runtime,
+org.eclipse.emf.ecore,
+org.eclipse.emf.ecore.xmi,
+org.eclipse.sphinx.emf,
+org.eclipse.ui,
+org.jgrapht,
+org.eclipse.app4mc.amalthea.model,
+org.eclipse.app4mc.multicore.openmapping
+</code></pre>
+		<p><!-- --></p>
+
+
+<h2 id="user-mapping"><a id="section2.9">2.9 </a>Mapping</h2>
+		<p>One of the essential steps during embedded software development for multi-core platforms is the mapping from elements of the software to elements of the hardware, e.g. 
+			<code>Tasks</code> to 
+			<code>Schedulers</code>, 
+			<code>Labels</code> to 
+			<code>Memorys</code> etc. This is usually a non trivial task, as an infinite number of combinations arises if either the software or the hardware becomes very complex. The purpose of APP4MCs OpenMapping Plugin is to determine such a mapping and store it in a 
+			<em>
+				<strong>Mapping Model</strong>
+			</em> which will contain the allocations of elements of the 
+			<em>
+				<strong>Software Model</strong>
+			</em> to elements of the 
+			<em>
+				<strong>Hardware Model</strong>
+			</em>.
+		</p>
+
+
+<h3 id="user-mapping-concept"><a id="section2.9.1">2.9.1 </a>Concept</h3>
+		<p>The conceptual implementation of OpenMapping Plugin is shown in the following Figure. </p>
+		<p>
+			<img src="images/mapping-tool-concept.png" style="width:75.0%;height:auto;"/>
+		</p>
+		<p>As shown in the top of this figure, it requires several models to operate. The models for 
+			<strong>Software</strong>, 
+			<strong>Hardware</strong> and 
+			<strong>Constraints</strong> are mandatory while the 
+			<strong>Property Constraints</strong> Model is optional.
+		</p>
+		<p>Using the OpenMapping Plugin, the user is able to choose between different mapping strategies. Currently these strategies are split into two categories: 
+			<em>Heuristic methods</em> and 
+			<em>Integer Linear Programming (ILP) based methods</em>. Unlike ILP based methods, Heuristic methods, such as the 
+			<em>Heuristic Data Flow Graph (DFG) load balancing</em>, will immediately create a mapping.
+		</p>
+		<p>ILP based methods on the other hand will first need to generate an ILP model of the mapping problem according to the selected mapping strategy, e.g. 
+			<em>ILP based load balancing</em> or 
+			<em>Energy aware mapping</em>. Once the ILP model has been created, it will be solved by one of the mathematical 
+			<em>Solvers</em>. Currently, the open source project Oj!Algo
+			<sup class="footnote">
+				<a href="#___fn1">1</a>
+			</sup> has been used in OpenMapping Plugin. Furthermore, the user can activate an optional MPS generator, which will generate an MPS file containing the ILP problem. This file may be used to solve the ILP problem by external (e.g. commercial) solvers, which tend to be more efficient in solving larger models compared to open source Java implementations.
+		</p>
+		<p>Once a mapping has been determined, it is displayed within the eclipse console and following output models are generated:</p>
+		<ul>
+			<li>
+				<strong>Mapping Model</strong>, containing the allocations from 
+				<code>Tasks</code> to 
+				<code>Schedulers</code>
+			</li>
+			<li>
+				<strong>OS Model</strong>, containing the 
+				<code>Schedulers</code> for each 
+				<code>Core</code>
+			</li>
+			<li>
+				<strong>Stimuli Model</strong>, containing the 
+				<code>Stimuli</code> for the resp. 
+				<code>Runnable</code> and 
+				<code>Task</code> activations
+			</li>
+		</ul>
+
+
+<h3 id="user-mapping-implementation"><a id="section2.9.2">2.9.2 </a>Implementation</h3>
+		<p>The following subsections give a short introduction about the different algorithm implementations of the OpenMapping Plugin. Section 
+			<a href="#user-mapping-task-gen">Task generation</a> describes the task generation method which is used to convert process prototypes into tasks. It is meant to be used by mapping algorithms which do not feature task generation by themselves. Sections 
+			<a href="#user-mapping-strategy-load-bal-dfg">Mapping Strategy 1: Heuristic DFG load balancing</a> and 
+			<a href="#user-mapping-strategy-load-bal-ilp">Mapping Strategy 2: ILP based load balancing</a> describe a heuristic and a mathematical load balancing approach for mapping tasks to cores. Finally, a more complex method for energy efficient task mapping with its own task creation algorithm is outlined in section 
+			<a href="#user-mapping-strategy-energy">Mapping Strategy 3: Minimizing Energy Consumption</a>.
+		</p>
+
+
+<h4 id="user-mapping-task-gen"><a id="section2.9.2.1"></a>Task generation</h4>
+		<p>The task generation method in OpenMapping Plugin is a pragmatic way to create tasks for other mapping algorithms which require 
+			<code>Tasks</code>, i.e. are not designed to agglomerate 
+			<code>Runnables</code> into 
+			<code>Tasks</code> on their own. This step utilizes 
+			<code>ProcessPrototypes</code> which are generated by the partitioning plugin (see Chapter 
+			<strong>Partitioning</strong>) and transforms them into 
+			<code>Tasks</code>. Furthermore, it will also create the 
+			<strong>
+				<em>Stimuli Model</em>
+			</strong> which contains the activation elements for the 
+			<code>Tasks</code>, i.e. 
+			<code>PeriodicStimulus</code>. An overview about the transformed elements and their sources as well as destinations is shown in 
+			<a href="#user-mapping-table-1">Table 1</a>.
+		</p>
+		<p id="user-mapping-table-1" style="text-align: left;"><!-- --></p>
+		<table>
+			<tr>
+				<th colspan="1" rowspan="1">Source Model</th>
+				<th colspan="1" rowspan="1">Source Element</th>
+				<th colspan="1" rowspan="1">Target Model</th>
+				<th colspan="1" rowspan="1">Target Element</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">SW</td>
+				<td colspan="1" rowspan="1">
+					<code>ProcessPrototype</code>
+				</td>
+				<td colspan="1" rowspan="1">SW</td>
+				<td colspan="1" rowspan="1">
+					<code>Task</code>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">SW</td>
+				<td colspan="1" rowspan="1">
+					<code>PeriodicActivation</code>
+				</td>
+				<td colspan="1" rowspan="1">Stimuli</td>
+				<td colspan="1" rowspan="1">
+					<code>PeriodicStimulus</code>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">SW</td>
+				<td colspan="1" rowspan="1">
+					<code>TaskRunnableCall</code> (within 
+					<code>ProcessPrototype</code>)
+				</td>
+				<td colspan="1" rowspan="1">SW</td>
+				<td colspan="1" rowspan="1">
+					<code>TaskRunnableCall</code> (within 
+					<code>Task</code>)
+				</td>
+			</tr>
+		</table>
+		<p style="text-align: center;">Table 1</p>
+
+
+<h4 id="user-mapping-strategy-load-bal-dfg"><a id="section2.9.2.2"></a>Mapping Strategy 1: Heuristic DFG load balancing</h4>
+		<p>The 
+			<em>Heuristic Data Flow Graph (DFG) load balancing</em> algorithm aims at achieving an equal utilization of a hardware platforms cores for DFG based software models.
+		</p>
+		<p>The first step in this algorithm is to determine the most complex 
+			<code>Task</code> (usually representing the critical path) and allocate it to the best fit core of a hardware platform. The runtime for each 
+			<code>Task</code> will now be estimated for every 
+			<code>Core</code> within the 
+			<code>System</code> and allocated to a 
+			<code>Core</code> which has the smallest increase of the longest overall runtime within all cores.
+		</p>
+		<p>One of the major benefits of this algorithm is its very low runtime. The information which is processed by this mapping strategy and, as such, has to be present in the input models, is shown in 
+			<a href="#user-mapping-table-2">Table 2</a>.
+		</p>
+
+
+<h4 id="user-mapping-strategy-load-bal-ilp"><a id="section2.9.2.3"></a>Mapping Strategy 2: ILP based load balancing</h4>
+		<p>This section described a comparatively simple ILP based strategy for allocating tasks to processors while minimizing the total execution time. This method supports multiple processors with the same processing speed (e.g. homogeneous processors) and it does not consider any dependencies between the tasks (e.g. waiting for the results of the predecessor).</p>
+		<p>Load balancing within this method is achieved by minimizing the highest execution duration 
+			<em>C</em> 
+			<em>
+				<sub>max</sub>
+			</em> of all 
+			<em>m</em> processing units with 
+			<em>n</em> tasks. The variable 
+			<em>x</em> 
+			<em>
+				<sub>ij</sub>
+			</em> is set to 
+			<em>1</em> if a task 
+			<em>j</em> is allocated to processor 
+			<em>i</em> and 
+			<em>0</em> otherwise. The model guarantees that each task is allocated to exactly one processor and limits the variables 
+			<em>x</em> 
+			<em>
+				<sub>ij</sub>
+			</em> type to boolean values. The duration (execution time) of a task 
+			<em>j</em> is specified by 
+			<em>p</em> 
+			<em>
+				<sub>j</sub>
+			</em>.
+		</p>
+		<p>
+			<img src="images/matheq.png" style="width:33.0%;height:auto;"/>
+		</p>
+		<p>One of the downsides in this algorithm is caused by variable 
+			<em>p</em> 
+			<em>
+				<sub>j</sub>
+			</em> which forces an equal processing duration of a task 
+			<em>j</em> on all cores. It is however possible to expand the method to support heterogeneous processors (in this case: processors with different processing speeds) with a minor modification: replacing 
+			<em>p</em> 
+			<em>
+				<sub>j</sub>
+			</em> with 
+			<em>p</em> 
+			<em>
+				<sub>ij</sub>
+			</em>, i.e. a separate processing duration of task 
+			<em>j</em> for every core 
+			<em>i</em>, will solve this problem.
+		</p>
+		<p>The minimal amount of information which is required to execute this algorithm is outlined in 
+			<a href="#user-mapping-table-2">Table 2</a>.
+		</p>
+		<p id="user-mapping-table-2" style="text-align: left;"><!-- --></p>
+		<table>
+			<tr>
+				<th colspan="1" rowspan="1">Source Model</th>
+				<th colspan="1" rowspan="1">Element</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">HW</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Core</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">A 
+					<code>Core</code> represents the target of an allocation. One OS Model with a 
+					<code>Scheduler</code> for each 
+					<code>Core</code> will be generated.
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>CoreType</code> 
+					<code>Prescaler</code> 
+					<code>Quartz</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">A cores 
+					<code>Prescaler</code>, the referenced 
+					<code>Quartz</code> and the 
+					<code>CoreTypes</code> attribute 
+					<code>CyclesPerTick</code> of a 
+					<code>Core</code> are used to determine the number of processed 
+					<code>Instructions</code> per second.
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">SW</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Task</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Tasks</code> will be allocated to a 
+					<code>Core</code> (over the cores 
+					<code>Scheduler</code>)
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Runnable</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Runnables</code> are derived from a tasks 
+					<code>TaskRunnableCalls</code>, their attribute 
+					<code>Instructions</code> is used during the load calculation for each 
+					<code>Core</code>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Stimuli</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Stimulus</code> (
+					<code>PeriodicStimulus</code>)
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">The 
+					<code>PeriodicStimulus</code> is used to specify a tasks activation rate, i.e. the period between its calls
+				</td>
+			</tr>
+		</table>
+		<p style="text-align: center;">Table 2</p>
+
+
+<h4 id="user-mapping-strategy-energy"><a id="section2.9.2.4"></a>Mapping Strategy 3: Minimizing Energy Consumption</h4>
+		<p>This mapping algorithm is based on the work 
+			<em>"Task Scheduling and Voltage Selection for Energy Minimization"</em> from Zhang et al. which presents a framework that aims at minimizing the energy consumption of variable voltage processors executing real time dependent tasks. This method is implemented as a two phase approach which integrates
+		</p>
+		<ul>
+			<li>
+				<strong>Task assignment</strong>: allocating each task to a core
+			</li>
+			<li>
+				<strong>Task ordering</strong>: ordering the tasks in due consideration of their constraints and deadlines
+			</li>
+			<li>
+				<strong>Voltage selection</strong>: selecting a slower but less energy consuming processor mode in order to save energy without harming any constraints or deadlines
+			</li>
+		</ul>
+		<p>In the first phase, opportunities for energy minimization are revealed by ordering real-time dependent tasks and assigning them to processors on the respective target platform.</p>
+		<ul>
+			<li>On 
+				<strong>single processor platforms</strong>, the ordering of tasks is performed by applying an Earliest Deadline First (EDF) scheduling. An further allocation of tasks to processors becomes needless, as only one allocation target exists.
+			</li>
+			<li>On 
+				<strong>multi processor platforms</strong>, a priority based task ordering is performed. The allocation of tasks to processors is determined by a best fit processor assignment.
+			</li>
+		</ul>
+		<p>Once the scheduling is created, there will be time frames between the end of one task and the start of another during which the processor is not being utilized (so called slacks). These slacks the prerequisites for the second phase, which performs the voltage selection. This phase aims at determining the resp. (optimal) processor voltage for each of its task executions without harming the constraints and eventually minimizing the total energy consumption of the system. In order to determine these voltages, the task scheduling is transformed into a directed acyclic graph (DAG) that is used to model the selection problem as integer programming (IP) problem. Once the model has been set up, it is optimized by a mathematical solver.</p>
+		<p>This algorithm has been implemented with two constraints:</p>
+		<ul>
+			<li>Only multi-core systems may be chosen as target platform, single core is not supported.</li>
+			<li>The algorithm is not meant to be used on heterogeneous cores, i.e. only multiple instances of the same type of core are supported.</li>
+		</ul>
+		<p>
+			<a href="#user-mapping-table-3">Table 3</a> lists the minimal amount of information which has to be present in the input models in order for this mapping strategy to work as well the special annotations which are added to the mapping model.
+		</p>
+		<p id="user-mapping-table-3" style="text-align: left;"><!-- --></p>
+		<table>
+			<tr>
+				<th colspan="1" rowspan="1">Source Model</th>
+				<th colspan="1" rowspan="1">Element</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">HW</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Core</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">A 
+					<code>Core</code> represents the target of an allocation. One OS Model with a 
+					<code>Scheduler</code> for each 
+					<code>Core</code> will be generated.
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>CoreType</code> 
+					<code>Prescaler</code> 
+					<code>Quartz</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">A cores 
+					<code>Prescaler</code>, the referenced 
+					<code>Quartz</code> and the 
+					<code>CoreTypes</code> attribute 
+					<code>CyclesPerTick</code> of a 
+					<code>Core</code> are used to determine the number of processed 
+					<code>Instructions</code> per second.
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;"/>
+				<td colspan="1" rowspan="1" style="text-align: left;"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">The 
+					<code>CoreTypes</code> contained 
+					<code>CustomProperty</code> (
+					<code>DoubleValue</code>) starting with the label 
+					<em>EnEf-Volt_{SomeID}</em> and 
+					<em>EnEf-Scale_{SomeID}</em> are used to specify the voltage levels, i.e. the performance of a core during a specific voltage.
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">SW</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Runnable</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Runnables</code> will be distributed to the cores (over the cores 
+					<code>Scheduler</code>), their attribute 
+					<code>Instructions</code> is used during the load calculation for each 
+					<code>Core</code>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;"/>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>Activation</code> (
+					<code>PeriodicActivation</code>)
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">The 
+					<code>PeriodicActivation</code> specifies the recurrence of the 
+					<code>Runnable</code>. The lowest recurrence is used to specify the overall deadline of all 
+					<code>Runnables</code>, i.e. the max amount of time for the sum of all 
+					<code>Runnable</code> executions.
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Constraints</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>RunnableEntityGroup</code> 
+					<code>RunnableSequencingConstraint</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Are used to determine the executional order of the 
+					<code>Runnables</code> as well as their interdependencies
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1" style="text-align: left;">Mapping</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">
+					<code>RunnableAllocation</code> 
+					<code>CustomProperty</code> 
+					<code>LongValue</code>
+				</td>
+				<td colspan="1" rowspan="1" style="text-align: left;">Specifies the selected voltage level and the number of 
+					<code>ExecutionCycles</code> at this voltage level.
+				</td>
+			</tr>
+		</table>
+		<p style="text-align: center;">Table 3</p>
+		<p>h3sec:mapUtilization). Utilization of the OpenMapping Plugin</p>
+		<p>This section provides information on the utilization of the AMALTHEA Mapping Plugin, i.e. its configuration (section 
+			<a href="#user-mapping-config">Configuration and Preferences</a> ) and how to generate mappings (section 
+			<a href="#user-mapping-create-mapping">Generating a mapping</a> ).
+		</p>
+
+
+<h4 id="user-mapping-config"><a id="section2.9.2.5"></a>Configuration and Preferences</h4>
+		<p>
+			<img src="images/mapping-preferences.png" style="width:50.0%;height:auto;"/>
+		</p>
+		<p>The configuration of OpenMapping Plugin can be performed through its preferences page. It is integrated into APP4MC and can be accessed through the menu bar under 'Window' -&gt; 'Preferences' -&gt; 'AMALTHEA Mapping'. The configurable fields, their types and their descriptions are listed below.</p>
+
+
+<h4 id="enabling-verbose-logging"><a id="section2.9.2.6"></a>Enabling verbose logging</h4>
+		<p>Checking the box 
+			<strong>
+				<em>'Enable verbose logging to console'</em>
+			</strong> will enable verbose logging to stdout. This may help to identify problems if the mapping plugin should fail to generate a mapping.
+		</p>
+
+
+<h4 id="specifying-the-output-location"><a id="section2.9.2.7"></a>Specifying the output location</h4>
+		<p>The radio buttons under 
+			<strong>
+				<em>'Select output location'</em>
+			</strong> allow to customize the directory which where newly generated files will be placed into.
+		</p>
+		<ul>
+			<li>
+				<strong>Default location</strong> specifies the 'output' directory within the respective projects root folder as destination for all new generated files.
+			</li>
+			<li>
+				<strong>Custom location (relative to project root)</strong> will ensure that all new files are created in a custom directory of the respective projects root folder. The name of this custom directory can be customized by changing the value in the text field below the radio buttons.
+			</li>
+			<li>
+				<strong>Custom location (absolute path)</strong> allows the user to specify a full custom destination for new generated files. The destination can be specified by either changing the value of the text field below the radio buttons, or by using the "Select" button.
+			</li>
+		</ul>
+		<p>
+			<em>Hint: It should be noted, that using this option will NOT update the project explorers folder list once the mapping is finished. It should be avoided to use this option in combination with a target location within the eclipse workspace.</em>
+		</p>
+
+
+<h4 id="selecting-a-mapping-algorithm"><a id="section2.9.2.8"></a>Selecting a mapping algorithm</h4>
+		<p>The radio buttons within 
+			<strong>
+				<em>'Select mapping algorithm'</em>
+			</strong> allow to customize the mapping strategy which should be applied during the mapping process. Currently, there are three valid options:
+		</p>
+		<ul>
+			<li>
+				<strong>Load balancing for DFG</strong>, described in section 
+				<a href="#user-mapping-strategy-load-bal-dfg">Mapping Strategy 1: Heuristic DFG load balancing</a>
+			</li>
+			<li>
+				<strong>ILP based load balancing</strong>, described in section 
+				<a href="#user-mapping-strategy-load-bal-ilp">Mapping Strategy 2: ILP based load balancing</a>
+			</li>
+			<li>
+				<strong>Energy efficient mapping</strong>, described in section 
+				<a href="#user-mapping-strategy-energy">Mapping Strategy 3: Minimizing Energy Consumption</a>
+			</li>
+		</ul>
+
+
+<h4 id="configuring-mathematical-solver"><a id="section2.9.2.9"></a>Configuring Mathematical Solver</h4>
+		<p>
+			<em>Hint: The settings described in this section only affect ILP based algorithms!</em>
+		</p>
+		<p>The section 
+			<strong>
+				<em>Solver Settings</em>
+			</strong> allows to configure the solver which is used to approximate the ILP problems, specify the minimal accuracy of the found solution and activate the MPS file output of the - ready to solve - ILP problem.
+		</p>
+		<ul>
+			<li>
+				<strong>Generate MPS file</strong> will activate MPS file generation. The resulting MPS file will contain the actual ILP problem for the chosen mapping strategy.
+			</li>
+			<li>
+				<strong>Max. Gap</strong> specifies the maximal gap (percentage) between the LP relaxion and a feasible solution before the solver considers it to be optimal.
+			</li>
+		</ul>
+		<p>Setting this value to 0.0 will order to solver to continue until either the final solution reaches the same value as the LP relaxion or another limit (below) has been reached while 1.0 will consider the first feasible solution being optimal.
+			<br>
+			<em>Valid values: <span class="math">0.0 – 1.0</span></em>
+		</p>
+		<p>Furthermore, it is possible to specify the maximum number of iterations or time spend on finding an optimal solution.</p>
+		<ul>
+			<li>
+				<strong>Max. Iterations (Abort)</strong> specifies the maximal 
+				<strong>
+					<em>total</em>
+				</strong> number of iterations which may be performed by the approximation algorithm in order to find an optimal solution for the ILP problem.
+			</li>
+			<li>
+				<strong>Max. Time (Abort)</strong> specifies the maximal 
+				<strong>
+					<em>total</em>
+				</strong> amount of time (milliseconds) that may be spend by the approximation algorithm in order to find an optimal solution for the ILP problem.
+			</li>
+			<li>
+				<strong>Max. Iteration (Suffice)</strong> specifies the maximal number of iterations which may be performed by the approximation algorithm in order to 
+				<strong>
+					<em>improve</em>
+				</strong> a previously found feasible solution.
+			</li>
+			<li>
+				<strong>Max. Time (Suffice)</strong> specifies the maximal amount of time (milliseconds) that may be spend by the approximation algorithm in order to 
+				<strong>
+					<em>improve</em>
+				</strong> a previously found feasible solution.
+			</li>
+		</ul>
+		<p>Setting one of these values to zero will pass the value of INT_MAX to the solver, technically removing the respective constraint.</p>
+
+
+<h4 id="user-mapping-create-mapping"><a id="section2.9.2.10"></a>Generating a mapping</h4>
+		<p>Depending on the selected mapping strategy, it may be required to create tasks in advance of the mapping algorithm. The method 
+			<strong>'Create Tasks'</strong>, which is accessible through the 
+			<em>AMALTHEA Software Models</em> file context menu (right click on 
+			<em>*.amxmi</em> and 
+			<em>*.amxmi-sw</em> files), is capable of transforming partitioned software models into software models with tasks.
+		</p>
+		<p>The mapping can be performed once input models with the required amount of information are present. Opening the context menu again (right click on 
+			<em>*.amxmi</em> and 
+			<em>*.amxmi-sw</em> files) and selecting 
+			<strong>'Perform Mapping'</strong> will open the 'Perform Mapping GUI'.
+		</p>
+		<p>
+			<img src="images/mapping-gui.png" style="width:66.0%;height:auto;"/>
+		</p>
+		<p>The fields within the GUI are described below.</p>
+		<ul>
+			<li>
+				<strong>Name of the Project</strong> is automatically filled and based on the selected software model. This value is used to specify the base name of the output files and may be customized.
+			</li>
+			<li>
+				<strong>Path to Software Model</strong> points to the location of the file containing the AMALTHEA Software Model which will be used during the mapping process. This path is automatically set, but may be changed if desired.
+			</li>
+			<li>
+				<strong>Path to Hardware Model</strong> points to the location of the file containing the AMALTHEA Hardware Model which will be used during the mapping process.
+			</li>
+		</ul>
+		<p class="footnote" id="___fn1">
+			<sup>1</sup> Oj!Algorithms, licensed under the MIT license, see: http://ojalgo.org
+		</p>
+
+
+<h2><a id="section2.10">2.10 </a>Model Checker</h2>
+		<p>Model Checker is a feature integrated with the APP4MC platform. Its task is to verify that the model fulfills a Model Description in form of a set of Model Specifications. Model Checker has been integrated with the main plugins of the APP4MC platform, like mapping and partitioning plugins. In order to provide better feedback to the developer about what is missing with its model at a specific process step, Model Checker provides a list of issues in form of a Pop-up window or in its own view. So, for example; if you what to run the partitioning feature on your model and you are missing 
+			<code>Runnables</code>. A Pop-up window will display as shown in the following image:
+		</p>
+		<p>
+			<img src="images/modelchecker-popup.png"/>
+		</p>
+		<p>If you close the Pop-up window don't worry, the Model Checker View keeps the latest issues list. </p>
+		<p>
+			<img src="images/modelchecker-view.png"/> 
+		</p>
+		<p>You can open this view by typing 
+			<em>Model Checker</em>  at 
+			<strong>Window &gt;&gt; Show View &gt;&gt; Other View</strong>; as shown in the picture below.
+		</p>
+		<p>
+			<img src="images/modelchecker-view-enable.png"/>
+		</p>
+
+
+<h3><a id="section2.10.1">2.10.1 </a>Model Description</h3>
+		<p>A model description comprises a list of ordered specifications. Model Checker takes this list and verifies that a specific model fulfills all this specifications. If a specification is not fulfilled, it will provide feedback to the user as shown in previous section.</p>
+
+
+<h4><a id="section2.10.1.1"></a>Model Specifications</h4>
+		<p>A model specification is a particullar characteristic that has to be check in the model. There are two predefined types of model specifications;  </p>
+		<ul>
+			<li>
+				<strong>Has a model type:</strong> Checks that the model contains a specific type of model type, for example 
+				<code>Software Model</code>. 
+			</li>
+			<li>
+				<strong>Amount of type:</strong> Checks that the model contains a specific element type, for example 
+				<code>Runnables</code>. 
+			</li>
+		</ul>
+		<p>Model Checker also supports a custom and more complex specifications. </p>
+
+
+<h4><a id="section2.10.1.2"></a>Specifications Severity</h4>
+		<p>When the Model Specifications are defined a severity is also added. Model Checker has different severities for its specifications;</p>
+		<ul>
+			<li>
+				<strong>Ok</strong>: Successfull and don't do anything if 
+				<code>Model Specifications</code> isn't fullfilled.
+			</li>
+			<li>
+				<strong>Info</strong>: Successfull and display some information if 
+				<code>Model Specifications</code> isn't fullfilled.
+			</li>
+			<li>
+				<strong>Warning</strong>: Process can run, a non-fatal issue was found in the model and a warning will be displayed if 
+				<code>Model Specifications</code> isn't fullfilled.
+			</li>
+			<li>
+				<strong>Error</strong>: Process can't run, a fatal issue was found and an error will be displayed if 
+				<code>Model Specifications</code> isn't fullfilled.
+			</li>
+		</ul>
+
+
+<h3><a id="section2.10.2">2.10.2 </a>Solving Model Checker issues</h3>
+		<p>In order to solve model checker issues it's always a good idea to start with the first item of the list. Let's say we want to map our model's 
+			<code>tasks</code> to the different 
+			<code>cores</code> of a platform model. If our model doesn't have a 
+			<code>Software Model</code>, a message as the one shown in the following image will display.
+		</p>
+		<p>
+			<img src="images/modelchecker-popup.png"/>
+		</p>
+		<p>Other issues are shown that derive from the missing 
+			<code>Software Model</code>. By adding a complete 
+			<code>Software Model</code> you'll fix all the issues listed.  
+		</p>
+
+
+<h2><a id="section2.11">2.11 </a>Multicore Wizard</h2>
+		<p>The APP4MC Multicore Wizard allows you to easily configure and run the entire 
+			<code>Workflow</code>;
+		</p>
+		<ul>
+			<li>
+				<strong>PrePartitioning</strong>
+			</li>
+			<li>
+				<strong>Partitioning</strong>
+			</li>
+			<li>
+				<strong>Task Creation</strong>
+			</li>
+			<li>
+				<strong>Mapping</strong>
+			</li>
+		</ul>
+		<p>In the following subsection the different pages of the wizard will be explained in detail.</p>
+		<p>To launch the APP4MC Multicore Wizard you only need to right-click on the model file containing the 
+			<strong>Software Model</strong>. Then click on 
+			<strong>
+				<em>AMALTHEA Multicore Features &gt; Run Wizard</em>
+			</strong>.
+		</p>
+
+
+<h3><a id="section2.11.1">2.11.1 </a>Flow Configuration</h3>
+		<p>The APP4MC Multicore Wizard's first page looks like in the following image;</p>
+		<p>
+			<img src="images/flow_configuration.png"/>
+		</p>
+		<p>In the 
+			<strong>Flow</strong> settings group you can select which steps of the 
+			<code>Workflow</code> you want to configure and run. Here a short description about the configuration options;
+		</p>
+		<ul>
+			<li>
+				<strong>Perform Partitioning:</strong> Adds the running of the 
+				<strong>Partitioning</strong> step to the 
+				<code>Workflow</code>. If selected the 
+				<strong>Partitioning Configuration</strong> page is enabled.
+			</li>
+			<li>
+				<strong>Perform Task Creation:</strong> Adds the running of the 
+				<strong>Task Creation</strong> step to the 
+				<code>Workflow</code>. No wizard page is enabled by selecting this option.
+			</li>
+			<li>
+				<strong>Perform Mapping:</strong> Adds the running of the 
+				<strong>Mapping</strong> step to the 
+				<code>Workflow</code>. If selected the 
+				<strong>Hardware Model</strong> filed and 
+				<strong>Mapping Configuration</strong> page are enabled.
+			</li>
+			<li>
+				<strong>Hardware Model:</strong> Allows you to select the 
+				<strong>Hardware Model</strong> to be used to for the 
+				<code>Workflow</code> run. If the model selected when the wizard was launched has a 
+				<strong>Hardware Model</strong> this field will be auto-completed. This field is mandatory if  
+				<strong>Perform Mapping</strong> is enabled.
+			</li>
+		</ul>
+		<p>The 
+			<strong>Logging</strong> settings group offers the possibility to set the 
+			<strong>Enable Verbose Logging to console</strong>. If checked every underlying APP4MC plugin instantiated during the 
+			<code>Workflow</code> run will verbosely log to the 
+			<strong>Console</strong> view.
+		</p>
+		<p>Finally, the 
+			<strong>Output</strong> settings group allows the user to select the location of the output model. Below the description for the available options;
+		</p>
+		<ul>
+			<li>
+				<strong>Default location:</strong> The output model will be located at 
+				<strong>ProjectRoot/wizard</strong>.
+			</li>
+			<li>
+				<strong>Relative location:</strong> Selecting this option enables the 
+				<strong>Path</strong> text box. The output model will be located at the relative path from 
+				<strong>ProjectRoot</strong>. The relative path has to be specified in the 
+				<strong>Path</strong> text box.
+			</li>
+			<li>
+				<strong>Absolute location:</strong> Selecting this option enables the 
+				<strong>Path</strong> text box and the 
+				<strong>Browse...</strong> button. By clicking 
+				<strong>Browse...</strong> you can specify the absolute path to locate you output model.
+			</li>
+		</ul>
+
+
+<h3><a id="section2.11.2">2.11.2 </a>Partitioning Configuration</h3>
+		<p>The 
+			<strong>Partitioning Configuration</strong> view allows you to configure the 
+			<strong>PrePartitioning</strong> and 
+			<strong>Partitioning</strong> steps of the 
+			<code>Workflow</code>.
+		</p>
+		<p>
+			<img src="images/partitioning_configuration_cpp.png"/>
+		</p>
+		<p>First, the 
+			<strong>PreParitioning Algorithm</strong> settings group allows you to configure what options to take into account for the 
+			<strong>PrePartitioning</strong> 
+			<code>Workflow</code> step.
+		</p>
+		<p>Finally, the 
+			<strong>Partitioning Algorithm</strong> settings allows you to select the 
+			<strong>Partitioning</strong> algorithm to be used. Below a short explanation about the algorithms options;
+		</p>
+		<ul>
+			<li>
+				<strong>ESSP:</strong> Selecting this algorithm enables the 
+				<strong>Number of ESSP partitions</strong> text box
+			</li>
+			<li>
+				<strong>CPP:</strong> Selecting this algorithm enables the 
+				<strong>Define one global critical path ...</strong> checkbox
+			</li>
+		</ul>
+		<p>For more information regarding 
+			<strong>PrePartitioning</strong> or 
+			<strong>Partitioning</strong> review the 
+			<strong>Partitioning</strong> help entry.
+		</p>
+
+
+<h3><a id="section2.11.3">2.11.3 </a>Mapping Configuration</h3>
+		<p>The APP4MC Multicore Wizard's 
+			<strong>Mapping Configuration</strong> page looks like in the following image;
+		</p>
+		<p>
+			<img src="images/mapping_configuration_ga.png"/>
+		</p>
+		<p>In the first settings group, 
+			<strong>Select mapping algorithm</strong> the user can select what mapping algorithm can be used. There are two categories of mapping algorithm available in 
+			<em>APP4MC</em>;
+		</p>
+		<ul>
+			<li>Genetic Algorithm based algorithms</li>
+			<li>Integer Linear Programming based algorithms</li>
+		</ul>
+		<p>For the first type no further configuration is needed. For the second some parameters still have to be set by the user (or use the defaults).</p>
+
+
+<h4><a id="section2.11.3.1"></a>ILP-based mapping</h4>
+		<p>If an 
+			<strong>ILP-based</strong> approach is selected the 
+			<strong>Solver Settings</strong> group is enabled as shown in the following image;
+		</p>
+		<p>
+			<img src="images/mapping_configuration_ilp.png"/>
+		</p>
+		<p>The 
+			<strong>Generate MPS file of ILP problem</strong> check box allows the user to have the 
+			<strong>MPS</strong> file also as an output of the 
+			<strong>Mapping</strong> step. The other fields allow you to fine-tune the 
+			<strong>ILP</strong> running.
+		</p>
+
+
+<h3><a id="section2.11.4">2.11.4 </a>Summary</h3>
+		<p>The 
+			<strong>Summary</strong> view is the last view of the wizard. It displays in a tree-structured way the summary of the configured 
+			<code>Workflow</code>. The image below shows a configured 
+			<code>Workflows</code> that includes 
+			<strong>all</strong> the 
+			<code>Workflow</code> steps, if some step isn't configured it won't be shown in the summary.
+		</p>
+		<p>
+			<img src="images/summary.png"/>
+		</p>
+
+
+<h3><a id="section2.11.5">2.11.5 </a>Finish</h3>
+		<p>The 
+			<code>Workflow</code> configuration in the wizard is automatically stored for you. This allows you to click the 
+			<strong>Finish</strong> button at any time, using the last known configuration. When running every 
+			<code>Workflow</code> configuration the 
+			<code>Model Checker</code> is triggered to verify that the model can in fact run the 
+			<code>Workflow</code>. If issues are found a pop-up message with show up, an example of the pop-up message box is shown below.
+		</p>
+		<p>
+			<img src="images/flow_failed.png"/>
+		</p>
+		<p>If the model checker finds any 
+			<strong>Error</strong> the 
+			<code>Workflow</code> won't run. This means you need to rework you model accordingly. If only 
+			<strong>Warning</strong> issues are found the 
+			<code>Workflow</code> will run after clicking 
+			<strong>OK</strong>.
+		</p>
+		<p>If your model fulfills all the requirements to successfully run the entire 
+			<code>Workflow</code> a pop-up like the one in the image below will show up.
+		</p>
+		<p>
+			<img src="images/flow_success.png"/>
+		</p>
+</article>
+
+
+<article>
+<h1><a id="section3">3 </a>Data Models</h1>
+
+
+<h2><a id="section3.1">3.1 </a>Data Model Overview</h2>
+		<p>The AMALTHEA data models are related to the activities in a typical design flow. The focus is on design, implementation and optimization of software for multicore systems. The data exchange between the activities is supported by the two main models of AMALTHEA, the System-Model and the Trace-Model.</p>
+		<p>
+			<img src="images/amalthea_models_actions.png"/>
+		</p>
+		<p>
+			<strong>Modeling</strong>
+			<br>The behavior of a component or system is often defined in the form of block diagrams or state charts. Dynamical behavior can also be formalized by differential equations that describe how the state of a system changes over time. Modeling tools like Matlab/Simulink, ASCET or Yakindu allow to simulate the model and to generate software descriptions and implementation.
+		</p>
+		<p>
+			<strong>Partitioning</strong>
+			<br>Based on the description of the software behavior (e.g. label accesses, synchronization, ...) this step identifies software units that can be executed in parallel.
+		</p>
+		<p>
+			<strong>System Modeling</strong>
+			<br>The structure of the hardware (e.g. cores, memory sizes, ...) and system constraints are added to the model.
+			<br>The constraints are limiting the possible results of the next step.
+		</p>
+		<p>
+			<strong>Optimization</strong>
+			<br>The activity of assigning executable software units to the cores and mapping data and instructions to memory sections. This step can be done manually or supported by a tool that optimizes the partitioning based on information about the software behavior (e.g. data dependencies, required synchronization, etc.).
+		</p>
+		<p>
+			<strong>Simulation / Software Execution</strong>
+			<br>In this step model-based simulation tools evaluate the timing behavior of the software.
+			<br>Typically these types of high level simulations are based on the hardware and software description of the system.
+			<br>Low level simulators (e.g. instruction set simulators) or real hardware can be used to execute existing software.
+			<br>The resulting traces provide additional data that is the basis for a more detailed analysis.
+		</p>
+		<p>A simplified picture shows the main purpose of the models.</p>
+		<p>
+			<img src="images/amalthea_models.png" style="width: 500px"/>
+		</p>
+		<p>The open AMALTHEA models allow custom tooling, interoperability of tools and the combination of different simulation or execution environments.</p>
+
+
+<h3><a id="section3.1.1">3.1.1 </a>AMALTHEA System Model</h3>
+		<p>
+			<img src="images/amalthea_system_model.png" style="width: 400px"/>
+		</p>
+		<p>The System Model contains:</p>
+		<p>
+			<strong>Hardware / ECU Description</strong>
+			<br>Hardware abstraction that includes general information about the hardware. Examples are: Number of cores, features of the cores, available memory, access times (from core x to memory y), etc.
+		</p>
+		<p>
+			<strong>SW Description</strong>
+			<br>The description contains information about the static or dynamic behavior the software. This includes: tasks, software components, interfaces, variables, types, etc. It is also possible to describe the characteristics of software functions like the access to variables (read, write, frequency) or the calls to service routines (call tree).
+		</p>
+		<p>
+			<strong>Timing Constraints</strong>
+			<br>Timing Constraints like End-to-End Delay, Latency and Synchronization can be formally written in the "TIMMO Timing Augmented Description Language" (TADL). They are derived from timing requirements or control theory.
+		</p>
+		<p>
+			<strong>Mapping Constraints</strong>
+			<br>The different cores of a typical embedded multicore ECU have different features. For optimal performance it is necessary to restrict the assignment of some software functions to e.g. cores with fastest I/O connections or the maximum clock rate. For safety reasons it is required that some functions are located on specific cores that e.g. can run in lock step mode. Constraints like this are represented in this sub model.
+		</p>
+		<p>
+			<strong>SW Mapping</strong>
+			<br>All information about the assignment of software units (e.g. tasks or runnables) to the cores and about the mapping of data and instructions to memory sections.
+		</p>
+
+
+<h3><a id="section3.1.2">3.1.2 </a>AMALTHEA Trace Model</h3>
+		<p>There is no specific EMF data model to describe event traces. The relevant events and their states are represented in the Event Model. In addition special trace formats for multicore have been specified in the AMALTHEA project and a Trace Database has been implemented. This database stores traces in a way that allows fast retrieval of the information (see the Developer Guide for a detailed description of the database structure).</p>
+
+
+<h3><a id="section3.1.3">3.1.3 </a>Structure of the model</h3>
+		<p>The definition of the AMALTHEA data model follows some basic principles:</p>
+		<ul>
+			<li>The model is defined in one package to simplify the handling (e.g. allow opposite references).</li>
+			<li>Different aspects are addressed in different logical sub models.</li>
+			<li>Existing EMF models from other Eclipse projects are reused and referenced instead of creating own definitions.</li>
+			<li>References are based on unique names within the same type of element.</li>
+		</ul>
+		<p>We also try to use cycles wherever possible and needed instead of direct time information. This has advantages in a multi-core environment, as the cores could have different clock frequencies.</p>
+		<p>The following figure shows the different logical parts of the AMALTHEA data model and how they are referencing each other. The central AMALTHEA model and common model that contains reusable elements are drawn without connections in this diagram.</p>
+		<p>
+			<img src="images/model_dependencies.png"/>
+		</p>
+
+
+<h2><a id="section3.2">3.2 </a>Common Model</h2>
+		<p>The AMALTHEA common model is not a model by itself, but provides standard elements used by other models as containments.</p>
+
+
+<h3><a id="section3.2.1">3.2.1 </a>Common Elements</h3>
+		<p>The only exception is the 
+			<i>CommonElements</i> class that provides a central container for tags and classifiers. These elements are used in many sub models where references to tags or classifiers provide a mechanism to annotate the objects.
+		</p>
+		<p>
+			<img src="images/model_common_elements.png"/>
+		</p>
+
+
+<h3 id="common-tags"><a id="section3.2.2">3.2.2 </a>Tags</h3>
+		<p>Tags are a generic possibility to annotate objects in the AMALTHEA model.</p>
+		<p>
+			<img src="images/model_common_tag.png"/>
+		</p>
+
+
+<h3 id="common-classifiers"><a id="section3.2.3">3.2.3 </a>Classifiers</h3>
+		<p>Classifiers are used to define specific features or abilities of a core or a memory. They are used in the 
+			<i>PropertyConstraintsModel</i> to restrict the allocation to cores or the memory mapping.
+		</p>
+		<p>
+			<img src="images/model_common_classifier.png"/>
+		</p>
+
+
+<h3 id="common-custom-props"><a id="section3.2.4">3.2.4 </a>Custom Properties</h3>
+		<p>The 
+			<i>CustomProperty</i> element is used to define own properties that are not (yet) available in AMALTHEA. If there is the need to extend an element or to store tool information related to processing steps, 
+			<i>CustomProperties</i> can be used to store this type of information. It also provides the possibility to work with prototypical approaches that later (if established and more stable) can be integrated in the standard model.
+		</p>
+		<p>
+			<img src="images/model_common_custom_property.png"/>
+		</p>
+		<p>The elements are stored in a 
+			<i>HashMap</i>. The values can be of different types as shown in the structure picture, like String, Integer, Boolean...
+			<br>In addition a 
+			<i>ReferenceObject</i> is available to store own references to other 
+			<i>EObject</i> elements.
+			<br>The 
+			<i>ListObject</i> can be used to store multi-valued custom properties.
+		</p>
+		<p>
+			<img class="scale" src="images/model_common_custom_property_value.png"/>
+		</p>
+
+
+<h3><a id="section3.2.5">3.2.5 </a>Time (and Time Unit)</h3>
+		<p>The AMALTHEA data model includes a common element to describe time ranges in an easy way, the 
+			<i>Time</i> element. The 
+			<i>Time</i> class in general allows to define negative time values. If only positive values are expected the AMALTHEA validation will show a warning.
+			<br>The 
+			<i>Time</i> element can be contained by any other element for specifying attributes to store time information.
+			<br>Time units are needed to describe different timing behavior and requirements, like deadlines or offsets of components.
+			<br>To support different time ranges, especially different time units, AMALTHEA predefines these types like seconds, milli-seconds, micro-seconds,  nano-seconds or pico-seconds.
+		</p>
+		<p>
+			<img class="scale" src="images/model_common_time.png"/>
+		</p>
+
+
+<h3><a id="section3.2.6">3.2.6 </a>Frequency (and Frequency Unit)</h3>
+		<p>
+			<img class="scale" src="images/model_common_frequency.png"/>
+		</p>
+
+
+<h3><a id="section3.2.7">3.2.7 </a>Data Size (and Data Size Unit)</h3>
+		<p>The  
+			<i>DataSize</i> (and  
+			<i>DataRate</i>) definition contains units and prefixes
+		</p>
+		<ul>
+			<li>according to the SI Standard</li>
+			<li>for binary multiples</li>
+		</ul><table>
+		 <tr>
+		 <th colspan="1" rowspan="1" style="padding:15px">International System of Units (SI)</th>
+		 <th colspan="1" rowspan="1" style="padding:15px">Prefixes for binary multiples</th>
+		 </tr>
+		 <tr>
+		 <td colspan="1" rowspan="1" style="vertical-align:top; padding:15px"> 
+		<table class="classic">
+			<tr>
+				<td colspan="1" rowspan="1">
+					<em>
+						<strong>Name</strong>
+					</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>
+						<strong>Prefix</strong>
+					</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>
+						<strong>Factor</strong>
+					</em>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">kilo</td>
+				<td colspan="1" rowspan="1">k</td>
+				<td colspan="1" rowspan="1">10<sup>3</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">mega</td>
+				<td colspan="1" rowspan="1">M</td>
+				<td colspan="1" rowspan="1">10<sup>6</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">giga</td>
+				<td colspan="1" rowspan="1">G</td>
+				<td colspan="1" rowspan="1">10<sup>9</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">tera</td>
+				<td colspan="1" rowspan="1">T</td>
+				<td colspan="1" rowspan="1">10<sup>12</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<em>peta</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>P</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>10<sup>15</sup></em>
+				</td>
+			</tr>
+		</table></td>
+		 <td colspan="1" rowspan="1" style="vertical-align:top; padding:15px"> 
+		<table class="classic">
+			<tr>
+				<td colspan="1" rowspan="1">
+					<em>
+						<strong>Name</strong>
+					</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>
+						<strong>Prefix</strong>
+					</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>
+						<strong>Factor</strong>
+					</em>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">kibi</td>
+				<td colspan="1" rowspan="1">Ki</td>
+				<td colspan="1" rowspan="1">2<sup>10</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">mebi</td>
+				<td colspan="1" rowspan="1">Mi</td>
+				<td colspan="1" rowspan="1">2<sup>20</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">gibi</td>
+				<td colspan="1" rowspan="1">Gi</td>
+				<td colspan="1" rowspan="1">2<sup>30</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">tebi</td>
+				<td colspan="1" rowspan="1">Ti</td>
+				<td colspan="1" rowspan="1">2<sup>40</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">pebi</td>
+				<td colspan="1" rowspan="1">Pi</td>
+				<td colspan="1" rowspan="1">2<sup>50</sup></td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<em>exbi</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>Ei</em>
+				</td>
+				<td colspan="1" rowspan="1">
+					<em>2<sup>60</sup></em>
+				</td>
+			</tr>
+		</table></td>
+		 </tr>
+		 </table>
+		<p>The 
+			<i>DataSize</i> provides convenience methods to get the size also in bit and byte.
+			<br>It is internally converted and can be retrieved in both ways.
+		</p>
+		<p>
+			<img class="scale" src="images/model_common_data_size.png"/> 
+		</p>
+
+
+<h3><a id="section3.2.8">3.2.8 </a>Data Rate (and Data Rate Unit)</h3>
+		<p>
+			<img class="scale" src="images/model_common_data_rate.png"/> 
+		</p>
+
+
+<h3><a id="section3.2.9">3.2.9 </a>Deviation</h3>
+		<p>The 
+			<i>Deviation</i> class is used to model statistical distributions within AMALTHEA. There is a wide variety of possible use cases, where such a distribution is needed. With such a deviation for example, the variation in run times of functions or respectively their instructions can be imitated. Therefore, AMALTHEA currently supports the following three statistical distributions:
+		</p>
+		<p>
+			<img class="scale" src="images/model_common_deviation.png"/>
+		</p>
+
+
+<h4><a id="section3.2.9.1"></a>Boundaries</h4>
+		<p>With the 
+			<i>Boundaries</i> class it is possible to define the deviation of instructions in such a way that a specific scenario is covered. The scenario is on the one hand specified by the minimum and maximum value between which the instructions vary. On the other hand, the 
+			<i>Sampling Type</i> specifies the specific scenario that is covered. The following sampling types are available which are visualised in the figures below:
+		</p>
+		<dl>
+			<dt>BestCase</dt>
+			<dd>Defines the scenario in which most instances should have runtimes close to the set minimum runtime, but still should consider some more time-consuming outliers up to the set maximum.</dd>
+			<dt>WorstCase</dt>
+			<dd>Defines the scenario in which most instances should have runtimes close to the set maximum runtime, but still should consider some less time-consuming outliers down to the set minimum.</dd>
+			<dt>AverageCase</dt>
+			<dd>Defines the scenario in which most instances should have runtimes close to the middle between the set minimum and maximum, but still should consider some less and more time-consuming outliers down to the set minimum or up to the set maximum respectively.</dd>
+			<dt>CornerCase</dt>
+			<dd>Defines the scenario in which most instances should have runtimes close to the set minimum and maximum runtime, but still should consider some other time-consuming outliers between those two.</dd>
+			<dt>Uniform</dt>
+			<dd>Defines the scenario in which all instances should have runtimes that are uniformly distributed between the set minimum and maximum.</dd>
+		</dl>
+		<p>
+			<img src="images/model_common_deviation_boundaries_1.png"/>
+		</p>
+		<p>
+			<img src="images/model_common_deviation_boundaries_2.png"/>
+		</p>
+
+
+<h4><a id="section3.2.9.2"></a>Uniform Distribution</h4>
+		<p>The uniform distribution is a statistical distribution where the values between the stated lower and upper bound are equally likely to be observed.</p>
+		<p>
+			<img src="images/model_common_deviation_uniform.png"/>
+		</p>
+
+
+<h4><a id="section3.2.9.3"></a>Gaussian/Normal Distribution</h4>
+		<p>The Gaussian/normal distribution is a statistical distribution where the values decrease symmetrically. The maximum value and thus its location is thereby stated by the mean and the rate of decrease is defined by its standard deviation. Since the curves approach zero on either side, an additional upper and lower bound can be added to constraint the values.</p>
+		<p>
+			<img src="images/model_common_deviation_normal.png"/>
+		</p>
+
+
+<h4><a id="section3.2.9.4"></a>Beta Distribution</h4>
+		<p>The Beta distribution is a statistical distribution whose shape is defined by alpha &gt; 0 and beta &gt; 0. That way, the Beta distribution can also be used to model other distributions like for example uniform, normal, or Bernoulli distribution. Since the curves can approach zero or infinity on either side, an additional upper and lower bound can be added to constraint the values.</p>
+		<p>
+			<img src="images/model_common_deviation_beta.png"/>
+		</p>
+
+
+<h4><a id="section3.2.9.5"></a>Weibull Distribution</h4>
+		<p>The Weibull distribution is a statistical distribution whose shape is defined by kappa &gt; 0 and the scale of the distribution by lambda &gt; 0. That way, the Weibull distribution can also be used to model other distributions like for example the exponential or normal distribution. Since the curves can approach zero or infinity on either side, an additional upper and lower bound can be added to constraint the values. Alternatively, the Weibull distribution can also be parameterized using the mean value and a parameter that constraints the distribution regarding the per mill of remaining values.</p>
+		<p>
+			<img src="images/model_common_deviation_weibull.png"/>
+		</p>
+
+
+<h3><a id="section3.2.10">3.2.10 </a>Statistic Elements</h3>
+		<p>The contained elements are representing statistical values.
+			<br>The values can be set either with a min, avg and max representation using the 
+			<i>MinAvgMaxStatistic</i> element.
+			<br>The other possibility is to set a single value using the 
+			<i>SingleValueStatistic</i> element.
+			<br>The minimum and maximum values are set as a normal 
+			<i>int</i> value,  the average the single value as 
+			<i>float</i>.
+		</p>
+		<p>
+			<img src="images/model_common_statistic.png"/>
+		</p>
+
+
+<h3><a id="section3.2.11">3.2.11 </a>Instructions</h3>
+		<p>Instructions are used to express execution times in a more abstract way. The number of instructions characterizes the amount of computation that is necessary to execute e.g. a 
+			<i>Runnable</i>. Depending on the capabilities of a 
+			<i>Core</i> (the frequency and the instructions per cycle) the time to execute such an element will differ.
+		</p>
+		<p>In the next picture a more detailed overview is given about the 
+			<i>Instructions</i>.
+		</p>
+		<p>
+			<img src="images/model_common_instructions.png"/>
+		</p>
+		<table class="minimal" style="padding:10px; border:1px solid black; background:#f8f8f8">
+			<tr>
+				<th colspan="1" rowspan="1">Name</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>Instructions</i>
+				</td>
+				<td colspan="1" rowspan="1">As a runnable contains several instructions to perform, this is represented using different algorithms or a constant value to consume the same amount of time/ticks per cycle.</td>
+			</tr>
+		</table>
+
+
+<h3><a id="section3.2.12">3.2.12 </a>Needs</h3>
+		<p>
+			<i>Needs</i> are used to express execution needs in the most abstract way. The number characterizes the amount of computation that is necessary to execute e.g. a 
+			<i>Runnable</i>. In future releases 
+			<i>Needs</i> will replace 
+			<i>Instructions</i> because they can also represent instructions but are more flexible.
+		</p>
+
+
+<h3><a id="section3.2.13">3.2.13 </a>Counters</h3>
+		<p>The 
+			<i>Counter</i> element describes an activation of a target element that happens only every n<sup>th</sup> time.
+		</p>
+		<table class="minimal" style="padding:10px; border:1px solid black; background:#f8f8f8">
+			<tr>
+				<th colspan="1" rowspan="1">Name</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>prescaler</i>
+				</td>
+				<td colspan="1" rowspan="1">Gives the number n for the activation,<br>e.g. if set to 2, the target element is executed every second time.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>offset</i>
+				</td>
+				<td colspan="1" rowspan="1">Initial shift for the first execution of the target.</td>
+			</tr>
+		</table>
+		<p>If for example 
+			<i>prescaler</i> is 5 and 
+			<i>offset</i> is 2 it is executed on the 2<sup>nd</sup>, 7<sup>th</sup>, 12<sup>th</sup>, … time.
+		</p>
+		<p>Counters are available at the following elements:</p>
+		<ul>
+			<li>Call sequence items:
+				<ul>
+					<li>
+						<i>ClearEvent</i>
+					</li>
+					<li>
+						<i>EnforcedMigration</i>
+					</li>
+					<li>
+						<i>InterProcessActivation</i>
+					</li>
+					<li>
+						<i>SchedulePoint</i>
+					</li>
+					<li>
+						<i>SetEvent</i>
+					</li>
+					<li>
+						<i>TaskRunnableCall</i>
+					</li>
+					<li>
+						<i>TerminateProcess</i>
+					</li>
+					<li>
+						<i>WaitEvent</i>
+					</li>
+				</ul>
+			</li>
+			<li>Stimuli:
+				<ul>
+					<li>
+						<i>InterProcess</i>
+					</li>
+					<li>
+						<i>EventStimulus</i>
+					</li>
+				</ul>
+			</li>
+		</ul>
+
+
+<h2><a id="section3.3">3.3 </a>Components Model</h2>
+		<p>The AMALTHEA component model is central accessible through the 
+			<i>ComponentsModel</i> element.
+		</p>
+		<p>It holds the following types:</p>
+		<ul>
+			<li>
+				<strong>Component</strong> / 
+				<strong>Composite</strong> ('components' containment reference)
+			</li>
+			<li>
+				<strong>System</strong> ('systems' containment reference)
+			</li>
+		</ul>
+		<p>
+			<img class="scale" src="images/model_components.png"/>
+		</p>
+
+
+<h3><a id="section3.3.1">3.3.1 </a>Components Model Elements</h3>
+		<p>The elements of the Components Model inherit several capabilities from common elements.</p>
+		<p>
+			<img class="scale" src="images/model_components_common.png"/>
+		</p>
+		<p>Ports, Components, Composites and ComponentInstances are referable by unique names.
+			<br>A Connector also has a name but the name is optional and does not have to be unique.
+		</p>
+
+
+<h4><a id="section3.3.1.1"></a>Component</h4>
+		<p>The 'Component' class represents a component. Components could be created directly within the 'ComponentModel' and are used as a type for a component instance.</p>
+		<p>
+			<img class="scale" src="images/model_components_component_references.png"/>
+		</p>
+		<p>It contains several ports of type 'Port'. A component refers the classes 'OsEvent', 'Label', 'Runnable' and 'AbstractProcess' from the software model and the class 'Semaphore' from the OS model.</p>
+
+
+<h4><a id="section3.3.1.2"></a>System and Composite</h4>
+		<p>Systems are defined as top level elements within a component model. A system contains several Component- and
+			<br>Connection-instances and is used to define the architecture of a technical system. 
+		</p>
+		<p>A 'Composite' is a special component type to aggregate Component- and Connection-instances compositely.
+			<br>So it could be used to create hierarchical component structures.
+		</p>
+		<p>System and Composite implement the interface 'ISystem'.
+			<br>The following diagram shows the main elements to represent the hierarchical structure.
+		</p>
+		<p>
+			<img src="images/model_components_isystem.png"/>
+		</p>
+		<p>In general each inner port should be connected. If a port is intentionally left unconnected it has to be added to the list of 'groundedPorts'.</p>
+
+
+<h4><a id="section3.3.1.3"></a>ComponentInstance and Connector</h4>
+		<p>The 'ComponentInstance' and the 'Connector' can be created within a 'System' or a 'Composite'. 'ComponentInstances' are used to represent instances of component- or composite-types. The 'Connector' class is used to connect the component instances to each other via their Ports. The connector contains a source and target 'QualifiedPort'.</p>
+
+
+<h4><a id="section3.3.1.4"></a>QualifiedPort</h4>
+		<p>A 'qualified' port refers a 'ComponentInstance' and a 'Port'.
+			<br>If the 'instance' link is null then the QualifiedPort refers to a port of the enclosing composite. 
+		</p>
+
+
+<h4><a id="section3.3.1.5"></a>InterfacePort</h4>
+		<p>The 'InterfacePort' class contains the attribute 'kind' to set the port direction.
+			<br>The attribute 'interface name' can be used to refer to an external definition, e.g. described in detail with the Franca IDL. 
+		</p>
+
+
+<h3><a id="section3.3.2">3.3.2 </a>Example</h3>
+
+
+<h4><a id="section3.3.2.1"></a>Diagram</h4>
+		<p>The diagram of the example shows a composite 'A' that contains two component instances 'X' and 'Y' of type 'B'. The connections between the ports are named 'c1' to 'c4'. The grounded port 'in_3' of instance 'X' (intentionally left unconnected) is marked green. The second unconnected port 'in_2' of instance 'Y' is unspecified. It is marked red and has to be changed, either declared as grounded or connected to another port. </p>
+		<p>
+			<img src="images/model_components_example.png"/>
+		</p>
+
+
+<h4><a id="section3.3.2.2"></a>Model Editor</h4>
+		<p>The same example is shown in the standard AMALTHEA editor.</p>
+		<p>
+			<img src="images/model_components_example_treeview.png"/>
+		</p>
+
+
+<h3><a id="section3.3.3">3.3.3 </a>Franca IDL</h3>
+		<p>Franca is a common interface definition  language (IDL). The initial version has been developed by the GENIVI consortium as part of the standardization of an In-Vehicle Infotainment (IVI) platform. The first public version of Franca was released in 2012 under the Eclipse Public License. Franca is approved as official Eclipse project.</p>
+		<p>The Franca IDL files can be edited in a textual editor that is provided by Franca. </p>
+		<p>
+			<img src="images/model_franca_editor_screenshot.png"/>
+		</p>
+		<p>AMALTHEA ports can specify the 'interface name' to refer to interfaces.</p>
+		<p>
+			<img src="images/model_components_franca_idl.png"/>
+		</p>
+
+
+<h2><a id="section3.4">3.4 </a>Configuration Model</h2>
+		<p>The purpose of the configuration model is to provide a common mechanism for configuration purposes. The included configurations can contain elements for further processing or build steps.</p>
+		<p>The central element is the 
+			<i>ConfigModel</i> class.
+		</p>
+		<p>Currently the only configuration object is 
+			<i>EventConfig</i>.
+		</p>
+		<p>
+			<img src="images/model_config_overview.png"/>
+		</p>
+
+
+<h3><a id="section3.4.1">3.4.1 </a>Event Configuration</h3>
+		<p>The event configuration represents target events to trace, either in a simulation or on a target hardware platform. The 
+			<i>EventConfig</i> elements are contained in the ConfigModel class as list with the name 
+			<i>eventsToTrace</i>. Attributes of 
+			<i>EventConfig</i> are:
+		</p>
+		<ol>
+			<li>
+				<i>name</i>: (optional) name of the element
+			</li>
+			<li>
+				<i>event</i>: reference to an existing events in the 
+				<i>Events</i> model
+			</li>
+		</ol>
+
+
+<h4><a id="section3.4.1.1"></a>Sample</h4>
+		<p>An example use case can be to trace all 
+			<i>Process</i> activate events. To express this in the configuration, one contained element must be of type 
+			<i>EventConfig</i> with the corresponding 
+			<i>Event</i> pointing to an already existent element. The 
+			<i>Event</i> is of type 
+			<i>ProcessEvent</i> and the 
+			<i>ProcessEventType</i> is set to 
+			<i>activate</i>. The other attributes are left blank to not limit the configuration to one 
+			<i>Process</i> with a given name for example.
+		</p>
+		<p>The consumer of the configuration must then match and filter the relevant elements for further processing.</p>
+		<p>The following screenshot is showing this minimal configuration.</p>
+		<p>
+			<img src="images/model_config_sample.png"/>
+		</p>
+
+
+<h2><a id="section3.5">3.5 </a>Constraints Model</h2>
+		<p>The constraints model contains different kind of constraints. There are the runnable-sequencing-constraints that can be used to define a required order for the runnables of the Software Model, the affinity constraints for defining the constraints for the mapping of runnables, processes and schedulers, and the timing constraints for restricting the time span between events or the duration of event chains. Regarding to that, it is also possible to define event chains in this model. </p>
+		<p>
+			<img src="images/model_constraints.png"/>
+		</p>
+
+
+<h3><a id="section3.5.1">3.5.1 </a>Requirements</h3>
+		<p>The Requirements are used to specify quality requirements for the dynamic architecture. 
+			<br>Requirements are divided into the following types depending on the entity type for which the requirement is specified:
+		</p>
+		<ul>
+			<li>Architecture Requirements for components</li>
+			<li>Process Chain Requirements for process chains</li>
+			<li>Process Requirements for tasks and isrs</li>
+			<li>Runnable Requirements for runnables</li>
+		</ul>
+		<p>The Severity attribute is used to describe the quality impact if the requirement is not fulfilled.
+			<br>The Limit defines the metric, the value and if the value for the metric is an upper limit or a lower limit. 
+			<br>Depending on the metric unit, the following Limits can be specified
+		</p>
+		<ul>
+			<li>Count Requirement Limit for metrics like 
+				<i>Preemptions</i>
+			</li>
+			<li>CPU Percentage Requirement Limit for metrics like 
+				<i>CPULoad</i>
+			</li>
+			<li>Frequency Requirement Limit for metrics like 
+				<i>CacheMissFrequency</i>
+			</li>
+			<li>Percentage Requirement Limit for metrics like 
+				<i>OsOverheadRelative</i>
+			</li>
+			<li>Time Requirement Limit for metrics like 
+				<i>ResponseTime</i>
+			</li>
+		</ul>
+		<p>
+			<img class="scale" src="images/model_constraints_requirements.png"/>
+		</p>
+		<p>An example for a requirement is the Deadline for a task. The Deadline is specified by an upper limit for the response time of the respective task.</p>
+
+
+<h3><a id="section3.5.2">3.5.2 </a>Runnable Sequencing Constraints</h3>
+		<p>These constraints can be used to define execution orders of runnables or, in other words, the dependencies between runnables. These dependencies can result from data exchange or any functional dependency that is not necessarily visible by other model parameters.</p>
+		<p>The following requirements can be specified with this constraint:</p>
+		<ul>
+			<li>Execution sequence of runnables A  -&gt;B, meaning A has to be finished before B starts</li>
+			<li>Scope on certain process/processes, when a runnable is executed multiple times in different process contexts</li>
+			<li>Succession of runnables within a process (strict, loose)</li>
+			<li>Position of sequence within a process (start, end, any position)</li>
+		</ul>
+		<p>
+			<img src="images/model_constraints_runnable_sequencing.png"/>
+		</p>
+		<p>A 
+			<i>RunnableSequencingConstraint</i> contains a list of 
+			<i>ProcessRunnableGroup</i> elements and an enumeration 
+			<i>RunnableOrderType</i> describing the basic rule for the sequencing. In general, a runnable sequencing constraint is independent of the processes that execute the runnables. Via the attribute "processScope" it is possible to define that a sequencing constraint is only valid for runnables within just one process or a set of processes.
+		</p>
+		<p>The 
+			<i>ProcessRunnableGroups</i> contain references to runnables that should be sequenced. The sequence is defined by the order of the runnable groups within the sequencing constraint. The order of the runnable references within a group is undefined.
+			<br>To sequence two runnables it is consequently necessary to create a 
+			<i>RunnableSequencingConstraint</i> with two 
+			<i>ProcessRunnableGroups</i>, each referencing one of the runnables.
+			<br>To describe that a set of runnables have to be executed before or after another runnable or set of runnables, it is possible to put more than one runnable reference in a group. As already mentioned, the order of the referenced runnables within a 
+			<i>ProcessRunnableGroup</i> is unimportant. 
+		</p>
+		<p>The following picture visualises a 
+			<i>RunnableSequencingConstraint</i> and multiple possible runtime situations. The constraint has two runnable groups, each depicted by an ellipsis. In this example, there is just one runnable in each group. The runnables in the groups must be executed in the order of the group ("R1" before "R2"). There is no restriction in which process context the runnables are executed. It is important that the order is correct and that the runnable of one group terminates before the runnable of the next group starts. The exemplary runtime situations shown in the lower part of the figure visualise situations that satisfy this constraint (blue) and those who violate the constraint (red).
+		</p>
+		<p>
+			<img src="images/model_constraints_runnable_sequencing_basic.png"/>
+		</p>
+		<p>The 
+			<i>RunnableSequencingConstraint</i> in the next figure has two processes set as a scope in its second group. That means that the runnable "R3" is allowed to be executed on the processes "P1" or "P3" (blue). But it is only expected to be executed one time in between (red)!
+		</p>
+		<p>
+			<img src="images/model_constraints_runnable_sequencing_scope.png"/>
+		</p>
+		<p>Each 
+			<i>RunnableSequencingConstraint</i> has a 
+			<i>RunnableOrderType</i>. It provides the following sequencing modes:
+		</p>
+		<ul>
+			<li>successor</li>
+			<li>immediateSuccessorAnySequence</li>
+			<li>immediateSuccessorEndSequence</li>
+			<li>immediateSuccessorStartSequence</li>
+		</ul>
+		<p>The meaning of the mode "successor" is that the runnable groups of a sequencing constraint do not have to follow each other directly, i.e., runnables that are not part of the constraint can be executed in between.
+			<br>In contrast to this, the modes starting with "immediateSuccessor" express that the runnables referenced by the runnable groups must execute in direct order, so without any runnable in between. With "StartSequence", "AnySequence" and "EndSequence" it is further constrained that the runnables of the constraint have to be executed at the beginning, at the end or at any position in a process.
+			<br>Assuming that all runnables are executed on the same process, the mode "immediateSuccessorStartSequence" means that all runnables of the constraint have to be executed in the correct order at the beginning of the process.
+			<br>The mode "immediateSuccessorEndSequence" is like "immediateSuccessorStartSequence", but here the runnable sequence must be executed at the end of the process.
+		</p>
+
+
+<h3><a id="section3.5.3">3.5.3 </a>Data Age Constraints</h3>
+		<p>Data Age constraints are used to define when the information in a label becomes valid or invalid after its last update. Therefore a runnable and a label has to be set. The information update occurs when the runnable performs a write access on the label. It is possible to define the minimum time after the information of a label update becomes valid. This means that the information shall not be used for further calculations before this time is over. The maximum time on the other hand defines the time after the label update when the information becomes invalid. Beside of time it is possible to define a minimum and maximum cycle. The cycle is related to the activation of the process that executes the runnable. </p>
+		<p>
+			<img src="images/model_constraints_data_age.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li>DataAgeTime: The 
+				<em>Time</em> object in the role of 
+				<em>minimumTime</em> must not contain a negative value!
+			</li>
+			<li>DataAgeTime: The 
+				<em>Time</em> object in the role of 
+				<em>maximumTime</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h3><a id="section3.5.4">3.5.4 </a>Data Coherency Groups</h3>
+		<p>A 
+			<i>DataCoherencyGroup</i> is used to define data coherency requirements for a group of labels.
+			<br>The Direction hereby is used to specify if the labels have to be read or written coherently. Moreover, the scope attribute defines the context of the coherent read or write requirement. Possible scopes are components, processes, and runnables.
+		</p>
+		<p>
+			<img src="images/model_constraints_data_coherency.png"/>
+		</p>
+
+
+<h3><a id="section3.5.5">3.5.5 </a>Data Stability Groups</h3>
+		<p>A 
+			<i>DataStabilityGroup</i> is used to define that the values of labels have to be kept stable within a given execution context.
+			<br>Currently, the following execution contexts are covered by the scope:
+		</p>
+		<ul>
+			<li>Component</li>
+			<li>Process</li>
+			<li>Runnable</li>
+		</ul>
+		<p>This means that it has to be guaranteed that the values of labels are identical either within the runnable, the process, or the component in which the denoted labels are accessed.</p>
+		<p>
+			<img src="images/model_constraints_data_stability.png"/>
+		</p>
+
+
+<h3><a id="section3.5.6">3.5.6 </a>Event Chains</h3>
+		<p>The concept for event chains is based on the Timing Augmented Description Language. 
+			<br>The Timing Augmented Description Language (TADL) is coming from the 
+			<a href="https://itea3.org/project/timmo-2-use.html">TIMMO-2-USE </a> project.  
+		</p>
+		<p>
+			<img src="images/model_constraints_eventchain.png"/>
+		</p>
+		<p>The 
+			<i class="Abstract">EventChain</i> consists of 
+			<i>EventChainItems</i>. These items are classified in two types:
+		</p>
+		<ol>
+			<li>EventChainReferences -&gt; EventChain: Used to reference already global defined EvenChains in the root list of the model.</li>
+			<li>EventChainContainers -&gt; SubEventChain: Inner anonymous EventChains, which are only defined once and has no global meaning, but only in the context of the current defined EventChain.</li>
+		</ol>
+		<p>An Event Chain object references always two events, a stimulus event and a response event. To define a simple event chain that just contains two events, one event chain object is enough. In this case it would just be a chain that with its stimulus as first event and the response as second event. 
+			<br>If more events are required it is necessary to add sub event chains. The stimulus is always the first event of an event chain, the response is always the last event. The events that are defined in the sub event chains are the events in between. 
+		</p>
+		<p>The picture below shows a simple example for an event chain of four events in a row.
+			<br>The top level chain defines the first event (E1) and the last event (E4).
+			<br>It contains a number of event chains. They describe the way from E1 to E4. 
+			<br>These sub event chains are added as 
+			<i>segments</i> to the parent. 
+			<br>For this some rules has to be considered:
+			<br>The stimulus of the first child event chain has to be the same as the stimulus of the parent (red in picture).
+			<br>The stimulus of other child event chains have to be equal to the response of the previous chain (blue in picture).
+			<br>The response of the last child event chain has to be the same as the response of the parent (green in picture).
+		</p>
+		<p>
+			<img src="images/model_constraints_eventchain_segments.png" style="width: 500px"/>
+		</p>
+		<p>As a stimulus or response event it is either possible to use an Entity Event or an Event Set.
+			<br>An Entity Event is a single event regarding to an entity like a task or a runnable. So it can be e.g. the start of a runnable. 
+			<br>If a set of events is used, then all events of this group must occur fulfill the event chain. The order in which the events occur is not important. 
+		</p>
+		<p>
+			<img src="images/model_constraints_eventchain_eventgroups.png"/>
+		</p>
+
+
+<h3><a id="section3.5.7">3.5.7 </a>Timing Constraints</h3>
+
+
+<h4><a id="section3.5.7.1"></a>Synchronization Constraints</h4>
+		<p>An 
+			<i>EventSynchronizationConstraint</i> describes how tightly the occurrences of a group of events follow each other.
+			<br>There must exist a sequence of time windows of width tolerance, such that every occurrence of every event in events belongs to at least one window, and every window is populated by at least one occurrence of every event.
+			<br>The parameter 
+			<i>multipleOccurrencesAllowed</i> defines, whether for the constraint all occurrences have to be considered or just the subsequent ones.
+		</p>
+		<p>An 
+			<i>EventChainSynchronizationConstraint</i> describes how tightly the occurrences of an event chain follow the occurrences of a different event chain.
+			<br>The 
+			<i>SynchronizationType</i> defines which parts of the event chains have to be in sync, stimulus or response, and the width of a time window sets the allowed tolerance.
+			<br>The parameter 
+			<i>multipleOccurrencesAllowed</i> defines, whether for the constraint all occurrences have to be considered or just the subsequent ones.
+		</p>
+		<p>
+			<img src="images/model_constraints_timing_sync.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li>
+				<em>SynchronizationConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>tolerance</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h4><a id="section3.5.7.2"></a>Repetition Constraint</h4>
+		<p>A 
+			<i>RepetitionConstraint</i> describes the distribution of the occurrences of a single event, including jitter.
+			<br>Every sequence of span occurrences of event must have a length of at least lower and at most upper time units.
+		</p>
+		<p>
+			<img src="images/model_constraints_timing_repetition.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li>
+				<em>RepetitionConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>lower</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>RepetitionConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>upper</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>RepetitionConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>period</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>RepetitionConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>jitter</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h4><a id="section3.5.7.3"></a>Delay Constraint</h4>
+		<p>A Delay Constraint imposes limits between the occurrences of an event called source and an event called target.
+			<br>Every instance of source must be matched by an instance of target, within a time window starting at lower and ending at upper time units relative to the source occurrence.
+			<br>In addition, a 
+			<i>MappingType</i> defines whether there is a strong ( 
+			<i>OneToOne</i> ), neutral ( 
+			<i>Reaction</i> ), or weak ( 
+			<i>UniqueReaction</i> ) delay relation between the events.
+		</p>
+		<p>
+			<img src="images/model_constraints_timing_delay.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li>
+				<em>DelayConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>lower</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>DelayConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>upper</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h4><a id="section3.5.7.4"></a>Event Chain Latency Constraint</h4>
+		<p>An 
+			<i>EventChainLatencyConstraint</i> defines how long before each response a corresponding stimulus must have occurred ( 
+			<i>Age</i> ), or how long after a stimulus a corresponding response must occur ( 
+			<i>Reaction</i> ).
+			<br>It always refers to an EventChain.
+		</p>
+		<p>
+			<img src="images/model_constraints_timing_latency.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li>
+				<em>EventChainLatencyConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>minimum</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>EventChainLatencyConstraint</em>: The 
+				<em>Time</em> object in the role of 
+				<em>maximum</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h3><a id="section3.5.8">3.5.8 </a>Affinity Constraints</h3>
+		<p>Affinity constraints are used to define the mapping of executable objects to each other.
+			<br>The objects that can be mapped are:
+		</p>
+		<ul>
+			<li>Runnables</li>
+			<li>Processes (Task or ISR)</li>
+			<li>Labels</li>
+		</ul>
+		<p>
+			<img src="images/model_constraints_affinity.png"/>
+		</p>
+		<p>An affinity constraint can either be a pairing or a separation constraint. A pairing constraint contains one amount of objects and a target. The pairing constraints say "All these objects must run together on this target". A separation constraint contains two groups of objects and a target. It says "This group of objects is not allowed to be mapped with the other group of objects on the specific target". So the separation constraint can be used to forbid a combination of objects on a target. It can also be used to say "These objects are not allowed to be mapped on this target". In this case only one group of the separation constraint is used.</p>
+		<p>Each affinity constraint has one or more targets. The type of the target depends on the type that should be mapped.</p>
+
+
+<h4><a id="section3.5.8.1"></a>Data Affinity Constraints</h4>
+		<p>A 
+			<i>DataConstraint</i> is used to define the mapping of label objects to memory units.
+		</p>
+		<p>
+			<img src="images/model_constraints_affinity_data.png"/>
+		</p>
+
+
+<h4><a id="section3.5.8.2"></a>Process Affinity Constraints</h4>
+		<p>A 
+			<i>ProcessConstraint</i> is used to define the mapping of process (Task or ISR) objects to processing cores or scheduling units.
+		</p>
+		<p>
+			<img src="images/model_constraints_affinity_process.png"/>
+		</p>
+
+
+<h4><a id="section3.5.8.3"></a>Runnable Affinity Constraints</h4>
+		<p>A 
+			<i>RunnableConstraint</i> is used to define the mapping of runnable objects to processing cores or scheduling units.
+		</p>
+		<p>
+			<img src="images/model_constraints_affinity_runnable.png"/>
+		</p>
+
+
+<h3><a id="section3.5.9">3.5.9 </a>Physical Section Constraints</h3>
+		<p>A 
+			<i>PhysicalSectionConstraint</i> is used to to define the mapping of Section objects to Memories. This mapping of Section object to Memory objects specifies that corresponding 
+			<strong>PhysicalSectionMapping</strong> associated to this 
+			<strong>Section</strong> element can be allocated only in the mapped Memories.
+		</p>
+		<pre xml:space="preserve"><code>Example: PhysicalSectionConstraint with the below properties has the following semantic:
+	name: Ram1_Ram2_PhysicalSectionConstraint
+	Memories : RAM1, RAM2
+	Section : .abc.reini
+Semantic: PhysicalSectionMapping for .abc.reini section can only be allocated either in RAM1 or RAM2 or in both. But not in other Memories.
+</code></pre>
+
+
+<h2><a id="section3.6">3.6 </a>Event Model</h2>
+		<p>The event model provides the classes to describe the BTF-Events that can be used for the tracing configuration, for the modeling of event chains and for some timing constraints. </p>
+		<p>
+			<img class="scale" src="images/model_events.png"/>
+		</p>
+		<p>There are different event classes for the different entity types that can be traced: </p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Entity</th>
+				<th colspan="1" rowspan="1">Event Class</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Process (Task, ISR)</td>
+				<td colspan="1" rowspan="1">ProcessEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">ProcessChain</td>
+				<td colspan="1" rowspan="1">ProcessChainEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Stimulus</td>
+				<td colspan="1" rowspan="1">StimulusEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Runnable</td>
+				<td colspan="1" rowspan="1">RunnableEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Label</td>
+				<td colspan="1" rowspan="1">LabelEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Channel</td>
+				<td colspan="1" rowspan="1">ChannelEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Semaphore</td>
+				<td colspan="1" rowspan="1">SemaphoreEvent</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Component</td>
+				<td colspan="1" rowspan="1">ComponentEvent</td>
+			</tr>
+		</table>
+		<p>In a running system, each entity can have different states. An event trace consists of the events that are visualizing the state-transitions of the traced entities. To define such an event in the model, each kind of event class contains an event-type-enumeration that provides the event-types for the state-transitions of its entity. The following picture shows the possible states of a process: </p>
+		<p>
+			<img src="images/model_events_process.png"/>
+		</p>
+		<p>So for example the event-type-enumeration for a process event contains the events 
+			<i>activate</i>, 
+			<i>start</i>, 
+			<i>resume</i>, ...
+		</p>
+		<p>A description of the individual events can be found in the following table:</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Event Class</th>
+				<th colspan="1" rowspan="1">Event Type</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="12">ProcessEvent</td>
+				<td colspan="1" rowspan="1">activate</td>
+				<td colspan="1" rowspan="1">The process instance is activated by a stimulus.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">start</td>
+				<td colspan="1" rowspan="1">The process instance is allocated to the core and starts execution for the first time.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">resume</td>
+				<td colspan="1" rowspan="1">The preempted process instance continues execution on the same or other core.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">preempt</td>
+				<td colspan="1" rowspan="1">The executing process instance is stopped by the scheduler, e.g. because of a higher priority process which is activated.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">poll</td>
+				<td colspan="1" rowspan="1">The process instance has requested a resource by polling (active waiting) which is not available.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">run</td>
+				<td colspan="1" rowspan="1">The process instance resumes execution after polling (i.e. active waiting) for a resource.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">wait</td>
+				<td colspan="1" rowspan="1">The process has requested a non-set OS EVENT (see OSEK 2.2.3 Extended Task Model, WAIT_Event()).</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">poll_parking</td>
+				<td colspan="1" rowspan="1">The parking process instance is allocated to the core and again polls (i.e. actively waits) for a resource.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">park</td>
+				<td colspan="1" rowspan="1">The active waiting process instance is preemptedby another process.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">release_parking</td>
+				<td colspan="1" rowspan="1">The resource which is requested by a parking process instance becomes available, but the parking process stays preempted and changes to READY state.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">release</td>
+				<td colspan="1" rowspan="1">The OS EVENT which was requested by a process is set (see OSEK 2.2.3 Extended Task Model, SET_Event()) and the process is ready to proceed execution.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">terminate</td>
+				<td colspan="1" rowspan="1">The process instance has finished execution.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="4">RunnableEvent</td>
+				<td colspan="1" rowspan="1">start</td>
+				<td colspan="1" rowspan="1">The runnable instance is allocated to the core and starts execution for the first time.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">suspend</td>
+				<td colspan="1" rowspan="1">The executing runnable instance is stopped, because the calling process is suspended.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">resume</td>
+				<td colspan="1" rowspan="1">The suspended runnable instance continues execution on the same or another core.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">terminate</td>
+				<td colspan="1" rowspan="1">The runnable instance has finished execution.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="2">Component</td>
+				<td colspan="1" rowspan="1">start</td>
+				<td colspan="1" rowspan="1">The execution of the component started, i.e. the first runnable in the list of runnables of the component instance is started.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">end</td>
+				<td colspan="1" rowspan="1">The execution of the component completed, i.e. all runnables in the list of runnables of the component instance were executed at least once.</td>
+			</tr>
+		</table>
+		<p>If it is required to define an event like "start-event of 
+			<strong>some</strong> process" then it is enough to create a object of type 
+			<i>ProcessEvent</i> and set the event-type 
+			<i>start</i>.
+		</p>
+		<p>It is also possible to restrict the definition of an event to a special entity. So it can be defined like "start-event of task T_1". Therefore it is possible to reference a process from 
+			<i>ProcessEvent</i>. In general, each event class can reference an entity of the corresponding type. In addition to that, each event class provides individual restrictions. So it is possible for 
+			<i>ProcessEvent</i> that the event is not only restricted to a special process, it can be also restricted to a core. So that would be like "start-event of task T_1 on core C_2". Another example is the class 
+			<i>RunnableEvent</i>, it allows to restrict the event to a runnable, the process that executes the runnable and the core that executes the process. 
+		</p>
+
+
+<h2><a id="section3.7">3.7 </a>Hardware Model</h2>
+		<p>The AMALTHEA hardware model is used to describe hardware systems which usually consist of ECU, micro controllers, processing units, memories, connections etc. It is accessible through the 
+			<i>HWModel</i> element and contains following top level elements:
+		</p>
+		<ul>
+			<li>Definitions</li>
+			<li>Domains</li>
+			<li>Features</li>
+			<li>Structures</li>
+		</ul>
+
+
+<h3><a id="section3.7.1">3.7.1 </a>Class Diagrams</h3>
+
+
+<h4><a id="section3.7.1.1"></a>Hardware model elements</h4>
+		<p>
+			<img class="scale" src="images/model_hw_main.png"/>
+		</p>
+
+
+<h4><a id="section3.7.1.2"></a>Hardware definitions and features</h4>
+		<p>
+			<img class="scale" src="images/model_hw_definition.png"/>
+		</p>
+
+
+<h4><a id="section3.7.1.3"></a>Hardware modules and access elements</h4>
+		<p>
+			<img class="scale" src="images/model_hw_module.png"/>
+		</p>
+
+
+<h4><a id="section3.7.1.4"></a>Hardware paths and destinations</h4>
+		<p>
+			<img class="scale" src="images/model_hw_access.png"/>
+		</p>
+
+
+<h3><a id="section3.7.2">3.7.2 </a>Element description</h3>
+		<p>The following tables describe the different model elements and their attributes in detail. For different elements short examples are attached.</p>
+
+
+<h4><a id="section3.7.2.1"></a>HwModel</h4>
+		<p>The 
+			<em>HwModel</em> class is the root element of the hardware model. It always contains one or multiple 
+			<em>HwStructures, PowerDomains</em> and 
+			<em>FrequencyDomains</em> and optionally different 
+			<em>FeaturesCategories</em> for the 
+			<em>HwModule</em> definitions.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware model</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Definitions</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwDefinition</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Definitions of ProcessingUnits, Memories, Caches and ConnectionHandlers</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Domains</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwDomain</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Frequency- and PowerDomains</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FeatureCategories</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwFeatureCategory</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">FeatureCategory for the HwModel</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Structures</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwStructure</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Hierarchical structure of the hardware model</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.2"></a>HwDefinition</h4>
+
+
+<h5><a id="section3.7.2.2.1"></a>ProcessingUnitDefinition</h5>
+		<p>The example in figure xxx is representative for any kind of definition in the model. This means for specifying a compute resource a 
+			<em>ProcessingUnitDefinition</em> is created once which is then referenced by the number of 
+			<em>ProcessingUnit</em> instances of this kind. For a 
+			<em>ProcessingUnitDefinition</em> the references to 
+			<em>HwFeatures</em> is on of the key concepts of the hardware model.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the processing unit definition</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PuType</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">PuType</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Type of the processing unit e.g. (Core, GPU, etc.)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Features</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">HwFeature</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Hardware features of the definition</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.2.2"></a>MemoryDefinition</h5>
+		<p>The example in figure xxx is representative for any kind of definition in the model. This means for specifying a memory, a 
+			<em>MemoryDefinition</em> is created once which is then referenced by the number of 
+			<em>Memory</em> instances of this kind.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the memory definition</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">AccessLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant or distribution of access latency in cycles</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Max. data rate for the memory</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Size</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">Size</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Size of the memory</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.2.3"></a>CacheDefinition</h5>
+		<p>For specifying a cache, a 
+			<em>CacheDefinition</em> is created once which is then referenced by the number of 
+			<em>Cache</em> instances of this kind.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the memory definition</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">AccessLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant or distribution of access latency in cycles</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Size</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">Size</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Size of the memory</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">CacheType</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">CacheType</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Cache type (e.g. data, instruction)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">WriteStrategy</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">WriteStrategy</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Cache write strategy (e.g. write-back)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Coherency</td>
+				<td colspan="1" rowspan="1">Bool</td>
+				<td colspan="1" rowspan="1">Bool</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Cache coherency (default = false)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Exclusive</td>
+				<td colspan="1" rowspan="1">Bool</td>
+				<td colspan="1" rowspan="1">Bool</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Exclusive cache (default = false)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Line Size</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Line size in bits</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Hit Rate</td>
+				<td colspan="1" rowspan="1">Double</td>
+				<td colspan="1" rowspan="1">Double</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Percentag hit rate of the cache(default = 0.0)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">NWays</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">N ways associative (default = 0)</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.2.4"></a>ConnectionHandlerDefinition</h5>
+		<p>For specifying a bus or Interconnect etc., a 
+			<em>ConnectionHandlerDefinition</em> is created once which is then referenced by the number of 
+			<em>ConnectionHandler</em> instances of this kind.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the memory definition</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">SchedPolicy</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">SchedPolicy</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Enumeration of different scheduling policies</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">ReadLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant or distribution in cycles for a read access</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">WriteLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant or distribution in cycles for a write access</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Max. data rate of the connection (value and unit)</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.3"></a>HwStructure</h4>
+		<p>A 
+			<em>HwStructure</em> is a hierarchical element which can contain all kind of 
+			<em>HwModules</em>, 
+			<em>HwConnections</em> and other 
+			<em>HwStructures</em>. Different 
+			<em>HwStructures</em> can be connected via one or more 
+			<em>HwPorts</em> with other structures or modules of a top level 
+			<em>HwStructures</em>. By combining different 
+			<em>HwStructures</em> any kind if hierarchical systems can be expressed. By setting the structure type attribute (e.g. Cluster, ECU) the structural level in the hardware is directly expressible in the model.
+		</p>
+		<p>
+			<img class="scale" src="images/hw_structure_example.png"/>
+		</p>
+		<p>The figure shows an example for creating a hierarchy within an E/E-architecture. The 
+			<em>HwStructure System</em> (which is called "System") is created as top level structure within the HwModel. It contains three other structures which represents different ECUs. The structures are connected via 
+			<em>HwPorts</em>, 
+			<em>HwConnections</em> and a 
+			<em>ConnectionHandler</em>. Usually structures in the model can be viewed as black boxes on the top level. 
+			<em>ECU3</em> allows a look inside, where additional structures for two SoCs are visible.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware structure</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">StructureType</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">StructureType</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Defines the type of the structure (e.g. ECU)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Modules</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwModule</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Modules of the structure (e.g. Memory)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Ports</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Ports to connect the structure</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Structures</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwStructure</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Hardware structure to build hierarchical designs</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Connections</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwConnection</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Connections within a structure</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.4"></a>HwDomain</h4>
+		<p>
+			<img class="scale" src="images/hw_domain_example.png"/>
+		</p>
+		<p>The figure shows an example for 
+			<em>HwDomain</em> (
+			<em>FrequencyDomain</em> and a 
+			<em>PowerDomain</em>). They are always created at the top level in the root element 
+			<em>HwModel</em>. Every basic component is able to reference a 
+			<em>FrequencyDomain</em> and a 
+			<em>PowerDomain</em>. 
+			<em>(Note: The link between domains and modules are only references, there are no visible connections inside the model)</em>
+		</p>
+
+
+<h5><a id="section3.7.2.4.1"></a>FrequencyDomain</h5>
+		<p>A 
+			<em>FrequencyDomain</em> is inherited from 
+			<em>HwDomain</em>. This element describes a frequency domain which can be referenced by all elements of the type 
+			<em>HwModule</em> to define the default frequency value for operation. In future the 
+			<em>FrequencyDomain</em> should also contain possibleValues which should specify the different frequencies for different operation modes. For this extension a general Amalthea mode concept is necessary.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the frequency domain</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DefaultValue</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">Frequency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Default frequency value</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Clock Gating</td>
+				<td colspan="1" rowspan="1">Boolean</td>
+				<td colspan="1" rowspan="1">Boolean</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Possibility to power down the domain (default = false)</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.4.2"></a>PowerDomain</h5>
+		<p>A 
+			<em>PowerDomain</em> is inherited from 
+			<em>HwDomain</em>. This element describes a power domain which can be referenced by all elements of the type 
+			<em>HwModule</em>, to define the default voltage value for operation. In future the 
+			<em>PowerDomain</em> should also contain possibleValues which should specify the different voltages for different operation modes. For this extension a general Amalthea mode concept is necessary.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the power domain</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DefaultValue</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">Voltage</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Default voltage value</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PowerGating</td>
+				<td colspan="1" rowspan="1">Boolean</td>
+				<td colspan="1" rowspan="1">Boolean</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Possibility to power down the domain (default = false)</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.5"></a>HwFeature</h4>
+		<p>A 
+			<em>HwFeature</em> is an abstract element to represent any kind of special functionality. The cost function (
+			<em>Recipes</em>) of an algorithm will be placed in an intermediate layer outside of the hardware model in future. However the 
+			<em>HwFeatures</em> will be directly referenced by the 
+			<em>Recipes</em>. All 
+			<em>HwFeatures</em> are placed inside a_ProcessingUnitDefinition_, in Future we will extend the Feature concept for 
+			<em>MemoryDefinitions</em>, 
+			<em>CacheDefinitions</em> and 
+			<em>ConnectionHandlerDefinitions</em>. Specific definitions for the basic components are able to reference such 
+			<em>HwFeatures</em> to express their functionality. HwFeatures could be reused several times by different definitions. A 
+			<em>HwFeature</em> can contain a value to express static costs in a model. Figure �#fig:hwFeature_example shows an example how recipes are used in a model. <em>NOTE: The 
+			<em>Recipes</em> and the 
+			<em>HwFeatures</em> concept is still work in progress. Changes to the 
+			<em>HwFeatures</em> are probable.</em>
+		</p>
+		<p>
+			<img class="scale" src="images/hw_feature_example.png"/>
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware feature</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Value</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">Value</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">assigned factor to the corresponding feature</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.5.1"></a>HwFeatureCategory</h5>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware feature</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Type</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">HwFeatureType</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Type to express the purpose of the feature (performance, power, performance_and_power)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Description</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Textual description of the hardware feature</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">HwFeature</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwFeature</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Hardware feature with a factor</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.6"></a>HwModule</h4>
+
+
+<h5><a id="section3.7.2.6.1"></a>ProcessingUnit</h5>
+		<p>A 
+			<em>ProcessingUnit</em> is a 
+			<em>HwModule</em> that can be used to model a wide set of different hardware components like a GPU, hardware accelerator, CPU, etc. The capability and the functionality of a 
+			<em>ProcessingUnit</em> are represented by different 
+			<em>HwFeatures</em> within the 
+			<em>ProcessingUnitDefinition</em>. The 
+			<em>ProcessingUnit</em> can be referenced by 
+			<em>AccessPaths</em> and 
+			<em>HwAccessElements</em>. The 
+			<em>ProcessingUnits</em> are the master modules in the model and every 
+			<em>ProcessingUnit</em> can has their own access space.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the processing unit instance</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Ports</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Ports of the component</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Caches</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">Cache</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Included caches by the Processing Unit e.g. L1 Cache</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">AccessElements</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">AccessElement</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Access element for a specific memory or processing unit</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Frequency domain which supplies the module with a frequency</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Power domain which supplies the module with a voltage</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Definition</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">ProcessingUnitDefinition</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Definition with all features for the processing unit instance</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.6.2"></a>Memory</h5>
+		<p>A 
+			<em>Memory</em> is a component of type 
+			<em>HwModule</em> to express any kind memory like SRAM, DRAM, Flash, etc. in the model, caches are modeled separately. The 
+			<em>Memory</em> element can be referenced as destination by a 
+			<em>HwAccessElement</em>.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the memory instance</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Ports</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Ports of the component</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Frequency domain which supplies the module with a frequency</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Power domain which supplies the module with a voltage</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Definition</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">MemoryDefinition</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Definition with all features for the memory instance</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.6.3"></a>Cache</h5>
+		<p>A 
+			<em>Cache</em> is a component of type 
+			<em>HwModule</em> to express the special behavior of a 
+			<em>Cache</em>. It is used to create cache topologies within a system. The 
+			<em>Cache</em> can be referenced by 
+			<em>AccessPaths</em> to express if it is a cached or non-cached access. It is also the only 
+			<em>HwModule</em> which can be directly contained by a 
+			<em>ProcessingUnit</em>.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the cache instance</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Ports</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Ports of the component</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Frequency domain which supplies the module with a frequency</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Power domain which supplies the module with a voltage</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Definition</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">CacheDefinition</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Definition with all features for the cache instance</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.6.4"></a>ConnectionHandler</h5>
+		<p>A 
+			<em>ConnectionHandler</em> is a component of type HwModule which can be used whenever multiple 
+			<em>HwConnections, (HwPorts)</em> have to be combined. It is possible to represent whole bus systems or interconnects with a single 
+			<em>ConnectionHandler</em>, or elements like small routers within a NoC.
+		</p>
+		<p>
+			<img class="scale" src="images/hw_connection_handler_example.png"/>
+		</p>
+		<p>The figure shows an example where a 
+			<em>ConnectionHandler</em> is used as an interconnect within a SoC. Optional it is possible to model 
+			<em>InternalConnections</em> inside a 
+			<em>ConnectionHandler</em> to model explicit or restrict different connections. However it is also possible to use default read and write latencies of the whole 
+			<em>ConnectionHandlerDefinition</em>, individual latencies can be attached to_InternalConnections_. A short example where a 
+			<em>ConnectionHandler</em> is used as a CAN bus is illustrated in the structure example. For detailed models where all modules connected via 
+			<em>HwConnections</em> and different 
+			<em>ConnectionHandlers</em>, the 
+			<em>ConnectionHandlers</em> should be the only module where contentions in the hardware model can occur. A 
+			<em>ConnectionHandler</em> can be referenced by 
+			<em>HwAccessPaths</em>.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the connection handler instance</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Ports</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Ports of the component</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">InternalConnections</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwConnection</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Internal connection between the ports</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">FrequencyDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Frequency domain which supplies the module with a frequency</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">PowerDomain</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Power domain which supplies the module with a voltage</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Definition</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">ConnectionHandlerDefinition</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Definition with all features for the connection handler instance</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.7"></a>HwAccessElement</h4>
+		<p>A 
+			<em>HwAccessElement</em> can be used to specify the access relationship between two 
+			<em>ProcessingUnits</em> or a 
+			<em>ProcessingUnit</em> and a 
+			<em>Memory</em>. With multiple 
+			<em>HwAccessElements</em> the whole access or even address space of a 
+			<em>ProcessingUnit</em> can be represented. A 
+			<em>HwAccessElement</em> represents always the view from a specific 
+			<em>ProcessingUnit</em>. There exist two different approaches to express latency or an data rate for a 
+			<em>HwAccessElement</em>: 1. directly using latencies or data rates or 2. modeling the exact path to the destination by attaching a 
+			<em>HwAccessPath</em> which references the specific connection elements like 
+			<em>ConnectionHandlers</em>, 
+			<em>HwConnection</em>, etc. For the second approach it is also possible to work directly with addresses.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the address element</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Destination</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">HwDestination</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Destination for the processing unit</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">AccessPaths</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwAccessPath</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Access path to the destination</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">ReadLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Read latency to the destination</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">WriteLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Write latency to the destination</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Max. data rate to the destination</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.8"></a>HwPort</h4>
+		<p>
+			<em>HwPorts</em> are elements which can be connected via 
+			<em>HwConnections</em>. Every module can contain multiple 
+			<em>HwPorts</em>. Every communication, input or output is handled via a 
+			<em>HwPort</em> of a component. It is only allowed to have one 
+			<em>HwConnection</em> per 
+			<em>HwPort</em>, except the 
+			<em>HwPort</em> is categorized as delegated port which means it is just a hierarchical connection between 
+			<em>HwStructures</em>. In this case the ports can have two 
+			<em>HwConnections</em>. The second exception is if inside a 
+			<em>ConnectionHandler</em>, 
+			<em>InternalConnections</em> are used.In this case a 
+			<em>HwPort</em> can be directed with a 
+			<em>HwConnections</em> and an 
+			<em>InternalConnection</em>. The following figure shows an example with delegated 
+			<em>HwPorts</em> and 
+			<em>InternalConnections</em>.
+		</p>
+		<p>
+			<img class="scale" src="images/hw_port_example.png"/>
+		</p>
+		<p>For 
+			<em>HwPorts</em> it's always possible to select if the port is an 
+			<em>initiator</em> or a 
+			<em>responder</em> port. The following example shows that an initiator port is always connected to a responder port (comparable to TLM modeling).
+		</p>
+		<p>
+			<img class="scale" src="images/hw_port_example_i_r.png"/>
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware port</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">BitWidth</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Bit width e.g. 32 bit (default = 0)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Priority</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">Int</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Priority of the hardware port (default = 0)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Type</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">PortType</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Port type (initiator, responder)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Delegated</td>
+				<td colspan="1" rowspan="1">Bool</td>
+				<td colspan="1" rowspan="1">Bool</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Delegated ports are hierarchical structure ports</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PortInterface</td>
+				<td colspan="1" rowspan="1">Enum</td>
+				<td colspan="1" rowspan="1">PortInterface</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Type to express special interfaces for validation</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.9"></a>HwConnection</h4>
+		<p>A 
+			<em>HwConnection</em> is an element to model structural connections between two 
+			<em>HwPorts</em>. 
+			<em>HwConnections</em> are always placed within 
+			<em>HwStructures</em>. It is possible to directly annotate a read and write latency at a 
+			<em>HwConnection</em>. 
+			<em>HwConnections</em> can be referenced by 
+			<em>HwAccessPaths</em>. The HwConnection do not have a reference to a_FrequencyDomain_, the frequency is always provided by the element which is in front of the 
+			<em>HwConnection</em> in the 
+			<em>HwAccessPath</em>.
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware connection</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Port1</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Port1 for the connection</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Port2</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">HwPort</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Port2 for the connection</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">ReadLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant or distribution in cycles for a read access</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">WriteLatency</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">HwLatency</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant or distribution in cycles for a write access</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">Containment</td>
+				<td colspan="1" rowspan="1">DataRate</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Max. data rate of the connection (value and unit)</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.10"></a>HwAccessPath</h4>
+		<p>A 
+			<em>HwAccessPath</em> is an element to describe the connection route of a 
+			<em>ProcessingUnit</em> to its destination (
+			<em>Memory</em> or 
+			<em>ProcessingUnit</em>). The 
+			<em>HwAccessPath</em> is defined through an ordered list of IPaths interface elements (
+			<em>HWConnections, Caches</em> and 
+			<em>ConnectionHandlers</em>) and is a containment of an 
+			<em>HwAccessElement</em>. The figure shows an example of an 
+			<em>HwAccessPath</em>, how a 
+			<em>ProcessingUnit</em> is connected via two 
+			<em>HwConnections</em> and a 
+			<em>ConnectionHandler</em> with a 
+			<em>Memory</em>.
+		</p>
+		<p>
+			<img class="scale" src="images/hw_access_path_example.png"/>
+		</p>
+		<p>In the following example the possible memOffset attribute is explained. Every 
+			<em>ProcessingUnit</em> can access a 
+			<em>Memory</em> or other 
+			<em>ProcessingUnit</em> over a different address. The size of the 
+			<em>Memory</em> has to be equal or greater than 
+			<em>endAddress</em> minus the 
+			<em>startAddress</em>.
+		</p>
+		<ul>
+			<li>memory_size &gt;= endAddress – startAddress</li>
+		</ul>
+		<p>In the case the the 
+			<em>ProcessingUnit</em> should not start at address 0 (from the memory point of view) the 
+			<em>memOffset</em> attribute can be used. With help of this attribute the access area for the memory can be changed, the figure shows an example.
+		</p>
+		<p>
+			<img class="scale" src="images/hw_memory_address_example.png"/>
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Name</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">String</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Name of the hardware access path</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PathElements</td>
+				<td colspan="1" rowspan="1">Reference</td>
+				<td colspan="1" rowspan="1">HwPath</td>
+				<td colspan="1" rowspan="1">*</td>
+				<td colspan="1" rowspan="1">Path elements for the access path</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">StartAddress</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Start address for the memory</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">EndAddress</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">End address for the memory</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">MemOffset</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Offset for accessing only a partition of a memory</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.11"></a>HwLatency</h4>
+
+
+<h5><a id="section3.7.2.11.1"></a>LatencyConstant</h5>
+		<p>A 
+			<em>LatencyConstant</em> is used to determine a constant number of clock cycles and can be attached to various other elements e.g. access latencies for a 
+			<em>MemoryDefinition</em> or a read latency for a 
+			<em>ConnectionHandlerDefinition</em> .
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Cycles</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">Long</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Constant number of clock cycles (default = 0)</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.7.2.11.2"></a>LatencyDeviation</h5>
+		<p>A 
+			<em>LatencyDeviation</em> is an object which allows to create a distribution out of different possibilities e.g. Weibull, Gaussian etc. The_LatencyDeviation_ can be attached to various elements e.g. access latencies for a 
+			<em>MemoryDefinition</em> or a read latency for a 
+			<em>ConnectionHandlerDefinition</em> .
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Type</th>
+				<th colspan="1" rowspan="1">Value</th>
+				<th colspan="1" rowspan="1">Mul.</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Cycles</td>
+				<td colspan="1" rowspan="1">Deviation</td>
+				<td colspan="1" rowspan="1">Deviation</td>
+				<td colspan="1" rowspan="1">1</td>
+				<td colspan="1" rowspan="1">Deviation for a specific element in clock cycles</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.7.2.12"></a>Enumerations</h4>
+		<p>In the following all enums are listed. In the case an enum is used by any class the default value of that enum is always 
+			<em>undefined</em>. That means that in case of an enum there are no default values for interfaces or other kind of types.
+		</p>
+		<p>In future there will be an option to extend the predefined enums with further port interfaces, hardware structure types etc. by selecting the option 
+			<em>other</em>. Then a second attribute field will appear to specify a custom entry. Moreover only new enums are explicitly mentioned in this report. Enums and classes which are already part of the existing Amalthea meta model are not described.
+		</p>
+		<p>
+			<strong>StructureType:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, System, ECU, Microcontroller, SoC, Cluster, Group, Array, Area, Region</li>
+		</ul>
+		<p>
+			<strong>CacheType:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, instruction, data, unified</li>
+		</ul>
+		<p>
+			<strong>VoltageUnit:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, V, mV, uV</li>
+		</ul>
+		<p>
+			<strong>PortType:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, initiator, responder</li>
+		</ul>
+		<p>
+			<strong>SchedPolicy:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, RoundRobin, FCFS, PriorityBased</li>
+		</ul>
+		<p>
+			<strong>WriteStrategy:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, none, writeback, writethrough</li>
+		</ul>
+		<p>
+			<strong>PuType:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, GPU, CPU, Accelerator</li>
+		</ul>
+		<p>
+			<strong>PortInterfaces:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, custom, can, flexray, lin, most, ethernet, spi, i2c, axi, ahb, apb, swr</li>
+		</ul>
+		<p>
+			<strong>HwFeatureType:</strong>
+		</p>
+		<ul>
+			<li>_undefined_, performance, power, performance_and_power</li>
+		</ul>
+
+
+<h3><a id="section3.7.3">3.7.3 </a>Additional Documents</h3>
+		<ul>
+			<li>
+				<a href="docs/amalthea_hardware_model.pdf">HW Documentation (PDF)</a>
+			</li>
+		</ul>
+
+
+<h2><a id="section3.8">3.8 </a>Mapping Model</h2>
+		<p>The mapping model is intended to provide tools that use hardware and software models (e.g. code generators) information about the corresponding mappings and allocations. This information contains associations between</p>
+		<ul>
+			<li>schedulers and executable software: A scheduler manages and distributes executable software like runnables or tasks on its managed processing units</li>
+			<li>schedulers and processing units: A scheduler can manage one or more processing units and deploy computations on these</li>
+			<li>data and memories: Data (such as functions, variables, heap etc) is mapped on static and volatile memories</li>
+		</ul>
+
+
+<h3><a id="section3.8.1">3.8.1 </a>Overview</h3>
+		<p>The Meta Model specifying the Mapping Model is shown below. </p>
+		<p>
+			<img class="scale" src="images/model_mapping_overview.png"/>
+		</p>
+
+
+<h4><a id="section3.8.1.1"></a>MappingModel</h4>
+		<p>The 
+			<i>MappingModel</i> serves as a container for each of the mapping rules, i.e. 
+			<i>Allocations</i> (executable software and processing units which are allocated to schedulers) and 
+			<i>Mappings</i> (labels and software which is mapped to memories).
+		</p>
+
+
+<h3><a id="section3.8.2">3.8.2 </a>Allocations</h3>
+		<p>
+			<img class="scale" src="images/model_mapping_allocation.png"/>
+		</p>
+
+
+<h4><a id="section3.8.2.1"></a>SchedulerAllocation</h4>
+		<p>The 
+			<i>SchedulerAllocation</i> describes the allocation of  a 
+			<i>Scheduler</i> to processing units. This class consists of references to the respective 
+			<i>Scheduler</i>, which is specified within an existing OS model, and a processing units, which is specified in a hardware model. Schedulers with algorithm "Grouping" are not allocated since they take no decisions and produce no overhead. 
+		</p>
+		<table class="minimal" style="padding:10px; border:1px solid black; background:#f8f8f8">
+			<tr>
+				<th colspan="1" rowspan="1">Name</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>scheduler</i>
+				</td>
+				<td colspan="1" rowspan="1">The scheduler (that is specified in more detail).</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>responsibility</i>
+				</td>
+				<td colspan="1" rowspan="1">Defines the processing units the scheduler is responsible for. On these units the scheduler takes decisions. Multiple schedulers can be responsible for one processing unit because of hierarchies. Child-schedulers only take decisions, if they parent-schedulers allows them to (e.g. hypervisors with virtual machines which execute an own operating system). Tasks allocated to this scheduler execute on the intersection between affinity and the responsibility of the scheduler. If this is null the configuration is invalid. If the intersection results in multiple cores, the task can migrate.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>executingPU</i>
+				</td>
+				<td colspan="1" rowspan="1">Defines on which processing unit the scheduling algorithm is actually executed to consider the overhead.</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.8.2.2"></a>RunnableAllocation</h4>
+		<p>The 
+			<i>RunnableAllocation</i> is a specialization of the 
+			<i>ExecutableAllocation</i>. It is used to associate a 
+			<i>Runnable</i>, specified within an existing software model, with a 
+			<i>Scheduler</i>.
+		</p>
+
+
+<h4><a id="section3.8.2.3"></a>TaskAllocation</h4>
+		<p>The 
+			<i>TaskAllocation</i> is used to associate a 
+			<i>Task</i> with its 
+			<i>TaskScheduler</i>.
+		</p>
+		<table class="minimal" style="padding:10px; border:1px solid black; background:#f8f8f8">
+			<tr>
+				<th colspan="1" rowspan="1">Name</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>task</i>
+				</td>
+				<td colspan="1" rowspan="1">The task  (that is specified in more detail).</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>scheduler</i>
+				</td>
+				<td colspan="1" rowspan="1">Specifies the unique allocation to the scheduler of the task.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>affinity</i>
+				</td>
+				<td colspan="1" rowspan="1">Specifies the possible processing units the task can run. If only one unit is specified, the task runs on this core. If multiple cores are specified, the task can migrate between the units. The task executes on the intersection between affinity and the responsibility of the scheduler. If this is null the configuration is invalid. If the intersection results in multiple cores, the task can migrate.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>schedulingParameters</i>
+				</td>
+				<td colspan="1" rowspan="2">Used to assign scheduling parameters for this specific allocation. For details see chapter "Scheduling Parameters" in OS Model.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>parameterExtensions</i>
+				</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.8.2.4"></a>ISRAllocation</h4>
+		<p>The 
+			<i>ISRAllocation</i> is used to associate an 
+			<i>ISR</i> with an 
+			<i>InterruptConroller</i>. The attribute 'priority' can be used to assign a value for this specific allocation.
+		</p>
+
+
+<h3><a id="section3.8.3">3.8.3 </a>Mappings</h3>
+
+
+<h4><a id="section3.8.3.1"></a>MemoryMapping</h4>
+		<p>The 
+			<i>MemoryMapping</i> is a class, describing the mapping of parts of the software model to 
+			<i>Memory</i>. It is used to associate specializations of the 
+			<i>AbstractMemoryElement</i> (i.e. 
+			<i>Label</i>, 
+			<i>Runnable</i>, 
+			<i>TaskPrototype</i> and 
+			<i>Process</i>). The target memory is specified by a reference to an explicit 
+			<i>Memory</i> within an existing hardware model. The position in memory can also be defined as address here. If the address is a absolute memory address, a offset address from the memories first address, or if the address information is not expected at all is defined by the 
+			<i>Memory Address Mapping Type</i> enumeration in the root element of the 
+			<i>Mapping Model</i>. The  Additional attributes, e.g. to supply further information for a code generator, may be described by the containment attributeList.
+		</p>
+
+
+<h4><a id="section3.8.3.2"></a>PhysicalSectionMapping</h4>
+		<p>The 
+			<em>PhysicalSectionMapping</em> class (can also be called as 
+			<strong>Physical Memory Section</strong> ) describes the following:
+		</p>
+		<ul>
+			<li>mapping of various 
+				<strong>Section</strong> elements to a specific 
+				<strong>Memory</strong>
+			</li>
+			<li>mapping various 
+				<strong>Label and Runnable</strong> elements to a Physical Memory Section
+			</li>
+			<li>description of memory address location where the Physical Memory Section is allocated </li>
+		</ul>
+
+
+<h2><a id="section3.9">3.9 </a>Measurement Model</h2>
+		<p>The measurement model provides the possibility to store runtime measurements. The main purpose is to exchange measured times, either as a series of single values or as derived statistical data.</p>
+		<p>Measurements refer to given elements of other model parts and can easily be exchanged (added, removed, updated).</p>
+		<p>Additional info like "creator", "date" or "hardware" should be entered as custom attributes of 
+			<i>MeasurementModel</i>.
+		</p>
+		<p>
+			<img src="images/model_measurement.png"/>
+		</p>
+
+
+<h2><a id="section3.10">3.10 </a>OS Model</h2>
+		<p>This part of the AMALTHEA model describes the provided functionality of an operating system. It mainly provides a way to specify how access is given to certain system resources. Therefore the concepts of scheduling, buffering, and semaphores are supported, which are described in detail in the following chapter.</p>
+		<p>
+			<img src="images/model_os_overview.png"/>
+		</p>
+
+
+<h3><a id="section3.10.1">3.10.1 </a>Operating System</h3>
+		<p>The basic element in the OS Model is the operating system. There can multiple operating systems in one model. The operating system type can be used to describe a generic operating system. It is also possible to use the vendor operating system type to define a vendor specific OS. An operating system contains a number of task schedulers and interrupt controllers. A task scheduler controls the execution of a task on one or multiple processor cores. An interrupt controller is the controller for the execution of ISRs and can be also mapped to multiple cores. The mapping of tasks and ISRs to their controller and the mapping of the controller to the cores can be done in the Mapping Model. An operating system can also contain a description of the overhead it produces. For this there is a more detailed explanation below.  </p>
+		<p>
+			<img src="images/model_os_operatingsystem.png"/>
+		</p>
+
+
+<h3><a id="section3.10.2">3.10.2 </a>Scheduler</h3>
+		<p>Interrupt controller and task scheduler have a scheduling algorithm. The picture below shows that both types are inherited of the scheduler type. Each scheduler has computation items. These items (a subset of the runnable items) characterize the runtime behavior of the scheduler.</p>
+		<p>
+			<img src="images/model_os_scheduler.png"/>
+		</p>
+
+
+<h4><a id="section3.10.2.1"></a>Scheduling Algorithm</h4>
+		<p>This is an abstract class for the different scheduling algorithms.</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Scheduling Algorithm</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">Grouping</td>
+				<td colspan="1" rowspan="1">This scheduler is a logical grouping of tasks/child-schedulers, e.g. a partition with attached budget for all tasks. This scheduler does not take any scheduling decisions and a parent scheduler is mandatory.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">UserSpecificSchedulingAlgorithm</td>
+				<td colspan="1" rowspan="1">This class contains a list of algorithm parameters. Each parameter has a key and a value (both Strings). A user can store all information for its own specific scheduling algorithm here.</td>
+			</tr>
+			<tr>
+				<td colspan="2" rowspan="1" style="background:#e6ffe6;">Fixed Priority</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">OSEK</td>
+				<td colspan="1" rowspan="1">OSEK compliant Scheduling</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FixedPriorityPreemptive</td>
+				<td colspan="1" rowspan="1">Fixed Priority Preemptive Scheduling (e.g. AUTOSAR)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">FixedPriorityPreemptiveWithBudgetEnforcement</td>
+				<td colspan="1" rowspan="1">Fixed Priority Preemptive Scheduling (with budget enforcement)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DeadlineMonotonic</td>
+				<td colspan="1" rowspan="1">Deadline Monotonic Scheduling (DMS): Task with the shortest period gets the lowest priority.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">RateMonotonic</td>
+				<td colspan="1" rowspan="1">Rate Monotonic Scheduling (RMS): Task with the shortest period gets the highest priority.</td>
+			</tr>
+			<tr>
+				<td colspan="2" rowspan="1" style="background:#e6ffe6;">Dynamic Priority</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">EarliestDeadlineFirst</td>
+				<td colspan="1" rowspan="1">Earliest Deadline First (EDF): Task with the earliest deadline gets the highest priority.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">LeastLocalRemainingExecutionTimeFirst</td>
+				<td colspan="1" rowspan="1">Least Local Remaining Execution-time First (LLREF): Task with the smallest local remaining execution time gets the highest priority.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PriorityBasedRoundRobin</td>
+				<td colspan="1" rowspan="1">Round Robin Scheduling Algorithm with prioritized processes.</td>
+			</tr>
+			<tr>
+				<td colspan="2" rowspan="1" style="background:#e6ffe6;">Proportionate Fair (Pfair)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PfairPD2</td>
+				<td colspan="1" rowspan="1">Proportionate Fair PD<sup>2</sup> Scheduling (Pfair-PD<sup>2</sup>)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PartlyPfairPD2</td>
+				<td colspan="1" rowspan="1">Partly Proportionate Fair PD<sup>2</sup> Scheduling (PPfair-PD<sup>2</sup>)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">EarlyReleaseFairPD2</td>
+				<td colspan="1" rowspan="1">Early Release Fair PD<sup>2</sup> Scheduling (ERfair-PD<sup>2</sup>)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PartlyEarlyReleaseFairPD2</td>
+				<td colspan="1" rowspan="1">Partly Early Release Fair PD<sup>2</sup> Scheduling (P-ERfair-PD<sup>2</sup>)</td>
+			</tr>
+			<tr>
+				<td colspan="2" rowspan="1" style="background:#e6ffe6;">Reservation Based Server</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">DeferrableServer</td>
+				<td colspan="1" rowspan="1">Deferrable Server (DS): provides a fixed budget, in which the budget replenishment is done periodically.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">PollingPeriodicServer</td>
+				<td colspan="1" rowspan="1">Polling Server (PS): provides a fixed budget periodically that is only available at pre-defined times.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">SporadicServer</td>
+				<td colspan="1" rowspan="1">Sporadic Server (SS): provides a fixed budget, in which the budget replenishment is performed only if it was consumed.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">ConstantBandwidthServer</td>
+				<td colspan="1" rowspan="1">Constant Bandwidth Server (CBS): provides a fixed utilization for executing jobs, in which the deadline for execution is independent on the execution time of jobs.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">ConstantBandwidthServerWithCASH</td>
+				<td colspan="1" rowspan="1">Constant Bandwidth Server (CBS) with capacity sharing (CASH). Consumes residual slack from other servers (work conserving).</td>
+			</tr>
+		</table>
+
+
+<h5><a id="section3.10.2.1.1"></a>Further information</h5>
+		<p>Details regarding proportionate fair (
+			<strong>Pfair</strong>) scheduling and the variants of the 
+			<strong>PD<sup>2</sup> Pfair</strong> algorithm can be found in the dissertation "Effcient and Flexible Fair Scheduling of Real-time Tasks on Multiprocessors" by Anand Srinivasan (see 
+			<a href="https://www.cs.unc.edu/~anderson/diss/srinidiss.pdf">dissertation</a> at University of North Carolina at Chapel Hill).
+		</p>
+		<p>An overview regarding 
+			<strong>Reservation Servers</strong> is given in the lecture "Resource Reservation Servers" by Jan Reineke (see 
+			<a href="https://embedded.cs.uni-saarland.de/lectures/realtimesystems/resourceReservationServers.pdf">lecture</a> at Saarland University).
+		</p>
+
+
+<h4><a id="section3.10.2.2"></a>Scheduling Parameters</h4>
+		<p>The class SchedulingParameters contains predefined parameters that are relevant for many scheduling algorithms. If a parameter is not used in a given context the value is null. Additional parameters can be added as key-value pairs of class ParameterExtensions.</p>
+		<p>
+			<img src="images/model_os_scheduling_parameters.png"/>
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>priority</i>
+				</td>
+				<td colspan="1" rowspan="1">Specifies the priority for the child-scheduler for priority based scheduling algorithms like FPP.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>minBudget</i>
+				</td>
+				<td colspan="1" rowspan="2">In budget-based scheduling algorithms like sporadic servers the runtime in a periodic time-interval must be given. The budget can be defined via min/max budgets. If no intervals are possible, the maxBudget is the key value.</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>maxBudget</i>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>replenishment</i>
+				</td>
+				<td colspan="1" rowspan="1">The replenishment time defines period in which the budget is restored.</td>
+			</tr>
+		</table>
+
+
+<h4><a id="section3.10.2.3"></a>Scheduler Association</h4>
+		<p>A hierarchy of schedulers can be specified with intermediate objects of class 
+			<i>SchedulerAssociation</i>. If set, the parent scheduler takes the initial decision who is executing.  If the child-scheduler is not a grouping of tasks, it can take scheduling decisions if permission is granted by the parent. The association also contains the relevant parameters of the scheduler in the hierarchical context.
+		</p>
+		<p>
+			<img src="images/model_os_scheduler_association.png"/>
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>parent</i>
+				</td>
+				<td colspan="1" rowspan="1">Refers to the parent scheduler</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>child</i>
+				</td>
+				<td colspan="1" rowspan="1">Derived attribute that is computed based on the containment reference "parentAssociation" from 
+					<i>Scheduler</i> to 
+					<i>SchedulerAssociation</i>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>schedulingParameters</i>
+				</td>
+				<td colspan="1" rowspan="2">See chapter "Scheduling Parameters"</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>parameterExtensions</i>
+				</td>
+			</tr>
+		</table>
+
+
+<h3><a id="section3.10.3">3.10.3 </a>Os Overhead</h3>
+		<p>It is possible to define the overhead that is produced by an operating system. The defined overhead can be assigned to an operating system definition. Each overhead information is defined as a set of instructions that has to be executed when the corresponding OS function is used. The instructions can be either a constant set or a deviation of instructions. It is possible to define the overhead for the ISR category one and two and for a number of operating system API functions.</p>
+		<p>
+			<img src="images/model_os_osoverhead.png"/>
+		</p>
+
+
+<h4><a id="section3.10.3.1"></a>ISR Overhead</h4>
+		<ul>
+			<li>ISR category 1 &amp; 2: Describes the overhead for ISRs of category one and two by adding a set of instructions that is executed at start and terminate of the ISR </li>
+		</ul>
+
+
+<h4><a id="section3.10.3.2"></a>API Overhead</h4>
+		<p>There exists also an overhead for API calls. The following API calls are considered:</p>
+		<ul>
+			<li>API Activate Task: Runtime overhead for the activation of a task or ISR by another task or ISR (inside the activating process)</li>
+			<li>API Terminate Task: Runtime for explicit task termination call (inside a task)</li>
+		</ul>
+		<ul>
+			<li>API Schedule: Runtime for task scheduling (on scheduling request)</li>
+		</ul>
+		<ul>
+			<li>API Request Resource: Runtime overhead for requesting a semaphore (inside a runnable)</li>
+			<li>API Release Resource: Runtime overhead for releasing a semaphore (inside a runnable)</li>
+		</ul>
+		<ul>
+			<li>API Set Event: Runtime overhead for requesting an OS event (inside a task or ISR)</li>
+			<li>API Wait Event: Runtime overhead for waiting for an OS event (inside a task or ISR)</li>
+			<li>API Clear Event: Runtime overhead for clearing an OS event (inside a task or ISR)</li>
+		</ul>
+		<ul>
+			<li>API Send Message: Runtime overhead for cross-core process activation or event (inside a task or ISR) </li>
+			<li>API Enforced Migration: Runtime overhead for migrating from one scheduler to another scheduler (inside a task or ISR)</li>
+		</ul>
+		<ul>
+			<li>API Suspend OsInterrupts</li>
+			<li>API Resume OsInterrupts</li>
+		</ul>
+		<ul>
+			<li>API Request Spinlock</li>
+			<li>API Release Spinlock</li>
+		</ul>
+		<ul>
+			<li>API SenderReceiver Read</li>
+			<li>API SenderReceiver Write</li>
+		</ul>
+		<ul>
+			<li>API SynchronousServerCallPoint</li>
+		</ul>
+		<ul>
+			<li>API IOC Read</li>
+			<li>API IOC Write</li>
+		</ul>
+
+
+<h3 id="os-data-consistency"><a id="section3.10.4">3.10.4 </a>OS Data Consistency</h3>
+		<p>The 
+			<i>OsDataConsistency</i> class provides a way to configure an automatic data consistency mechanism of an operating system. It is used to cover the following two use cases:
+		</p>
+		<ul>
+			<li>Provide a configuration for external tools that perform a data consistency calculation based on the stated information.</li>
+			<li>Provide the results of a performed data consistency calculation which then have to be considered by external tools (e.g. by timing simulation).</li>
+		</ul>
+		<p>
+			<img src="images/model_os_data_consistency.png"/>
+		</p>
+		<p>To distinguish the different use cases and to consequently also indicate the workflow progress for achieving data consistency, 
+			<i>OsDataConsistencyMode</i> allows to define the general configuration of the data consistency. The following modes are available:
+		</p>
+		<ol>
+			<li>noProtection: data stability and coherency is NOT automatically ensured.</li>
+			<li>automaticProtection: data stability and coherency HAS TO BE ensured according configuration either via custom protection or via model elements.
+				<ol>
+					<li>customProtection: data stability and coherency IS ensured according configuration but not via model elements.</li>
+					<li>handeldByModelElements: data stability and coherency IS ensured via model elements.</li>
+				</ol>
+			</li>
+		</ol>
+		<p>The 
+			<i>DataStability</i> class defines for which sequence of runnables data has to be kept stable. Furthermore, it can be stated whether all data is considered for stability or just those accessed multiple times.
+		</p>
+		<p>DataStabilityLevel:</p>
+		<ul>
+			<li>
+				<i>period</i>			- between consecutive activations
+			</li>
+			<li>
+				<i>process</i>			- within a Task or ISR
+			</li>
+			<li>
+				<i>scheduleSection</i>	- between Schedule points (explizit schedule points, begin and end of process)
+			</li>
+			<li>
+				<i>runnable</i>			- within a Runnable
+			</li>
+		</ul>
+		<p>The 
+			<i>NonAtomicDataCoherency</i> class defines for which sequence of runnables data has to be kept coherent. Like for data stability it can be stated whether all data is considered for coherency or just those accessed multiple times.
+		</p>
+
+
+<h3><a id="section3.10.5">3.10.5 </a>Semaphore</h3>
+		<p>With this object, a semaphore can be described which limits the access of several processes to one resource at the same time.</p>
+		<p>
+			<img src="images/model_os_semaphore.png"/>
+		</p>
+		<table class="classic">
+			<tr>
+				<th colspan="1" rowspan="1">Attribute</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>name</i>
+				</td>
+				<td colspan="1" rowspan="1">Name of semaphore (inherited from ReferableBaseObject)</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>semaphoreType</i>
+				</td>
+				<td colspan="1" rowspan="1">Defines how the semaphore is implemented</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>initialValue</i>
+				</td>
+				<td colspan="1" rowspan="1">Initial number of processes that access the semaphore</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>maxValue</i>
+				</td>
+				<td colspan="1" rowspan="1">Maximum number of processes that can concurrently access the semaphore</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>priorityCeilingPrototcol</i>
+				</td>
+				<td colspan="1" rowspan="1">Defines if the priority ceiling protocol is activated. If it is activated, a process that accesses the semaphore gets a higher priority as the processes that can also access the same semaphore</td>
+			</tr>
+		</table>
+
+
+<h2><a id="section3.11">3.11 </a>PropertyConstraints Model</h2>
+		<p>The scope of the Property Constraints model is to limit the design space by providing information about the specific hardware properties that parts of the software rely on, i.e. what properties or features have to be supplied by the respective hardware in order to be a valid mapping or allocation target.</p>
+		<p>This information comprises</p>
+		<ul>
+			<li>Core allocation constraints, which describe the constraints on cores.</li>
+			<li>Memory mapping constraints, which describe the constraints on memories.</li>
+		</ul>
+
+
+<h3><a id="section3.11.1">3.11.1 </a>Structure</h3>
+		<p>The figure below shows the Property Constraints model. In order to provide a better understanding of the model, interconnections between software model elements are not shown in this figure.</p>
+		<p>
+			<img src="images/model_propertyconstraints_overview.png"/>
+		</p>
+
+
+<h3><a id="section3.11.2">3.11.2 </a>CoreAllocationConstraint</h3>
+		<p>The 
+			<i>CoreAllocationConstraint</i> is an abstract class for describing constraints which affect the selection of a suitable 
+			<i>Core</i>.
+		</p>
+
+
+<h4><a id="section3.11.2.1"></a>RunnableAllocationConstraint</h4>
+		<p>The 
+			<i>RunnableAllocationConstraint</i> is a specialization of the 
+			<i>CoreAllocationConstraint</i>. It is used to specify constraints on 
+			<i>Core</i> elements which are used in 
+			<i>Runnable</i> to 
+			<i>Core</i> allocations.
+		</p>
+
+
+<h4><a id="section3.11.2.2"></a>ProcessAllocationConstraint</h4>
+		<p>The 
+			<i>ProcessAllocationConstraint</i> is a specialization of the 
+			<i>CoreAllocationConstraint</i>. It is used to specify constraints on 
+			<i>Core</i> elements which are used in the allocation of Process's specializations (i.e. 
+			<i>Task</i> and 
+			<i>ISR</i>), to 
+			<i>Cores</i>.
+		</p>
+
+
+<h4><a id="section3.11.2.3"></a>ProcessPrototypeAllocationConstraint</h4>
+		<p>Tha same as ProcessAllocationConstraint but for process prototypes in an earlier phase of the development.</p>
+
+
+<h3><a id="section3.11.3">3.11.3 </a>MemoryMappingConstraint</h3>
+		<p>The 
+			<i>MemoryMappingConstraint</i> is an abstract class for describing constraints which affect the selection of a suitable 
+			<i>Memory</i>. The actual constraint on the core is described by the 
+			<i>HwMemoryConstraint</i>.
+		</p>
+
+
+<h4><a id="section3.11.3.1"></a>AbstractElementMappingConstraint</h4>
+		<p>The 
+			<i>AbstractElementMappingConstaint</i> is a specialization of the 
+			<i>MappingConstraint</i>. It is used to specify constraints on 
+			<i>Memory</i> elements which are used in the mapping of 
+			<i>AbstractMemoryElement</i> specializations (i.e. 
+			<i>Label</i>, 
+			<i>Runnable</i>, 
+			<i>TaskPrototype</i> or 
+			<i>Process</i>) to 
+			<i>Memories</i>.
+		</p>
+
+
+<h3><a id="section3.11.4">3.11.4 </a>Classifications</h3>
+		<p>The specializations 
+			<i>CoreClassification</i> and 
+			<i>MemoryClassification</i> are used to describe the features that a hardware element (
+			<i>Core</i> or 
+			<i>Memory</i>) needs to provide in order to be a valid target. This is done by references to Classifiers, conditions (requires vs. excludes) and the kind of grouping (all of them vs. at least one of them).
+		</p>
+
+
+<h3><a id="section3.11.5">3.11.5 </a>Example</h3>
+		<p>
+			<img src="images/model_propertyconstraints_example.png"/>
+		</p>
+
+
+<h2><a id="section3.12">3.12 </a>Stimuli Model</h2>
+		<p>The Stimuli Model contains stimulus and clock objects.</p>
+		<p>
+			<img class="scale" src="images/model_stimuli.png"/>
+		</p>
+
+
+<h3><a id="section3.12.1">3.12.1 </a>Stimuli</h3>
+		<p>
+			<img class="scale" src="images/model_stimuli_stimuli.png"/>
+		</p>
+		<p>A stimulus is responsible to activate processes. The following different types are available:</p>
+		<ul>
+			<li>
+				<strong>SingleStimulus</strong>: Activates the process only once.
+			</li>
+			<li>
+				<strong>ArrivalCurveStimulus</strong>: A list of time-borders in which a specified number of occurrences are expected.
+			</li>
+			<li>
+				<strong>PeriodicStimulus</strong>: Periodic activations based on an offset, a recurrence and (optionally) a jitter.
+			</li>
+			<li>
+				<strong>PeriodicSyntheticStimulus</strong>: Defines a periodically triggered stimuli depending on a defined list of occurrence times.
+			</li>
+			<li>
+				<strong>PeriodicBurstStimulus</strong>: Defines a periodic burst pattern of the process.
+			</li>
+			<li>
+				<strong>RelativePeriodicStimulus</strong>: Periodic activation based on offset and a recurrence.<br>In contrast to PeriodicStimulus the recurrence is relative to the last occurrence and a deviation is mandatory. 
+			</li>
+			<li>
+				<strong>VariableRateStimulus</strong>: Periodic activations based on other events, like rotation speed.
+			</li>
+			<li>
+				<strong>InterProcessStimulus</strong>: Activations based on an explicit inter-process activation.<br>Contains a Counter element if activation is either shifted and / or happening every n<sup>th</sup> time.
+			</li>
+			<li>
+				<strong>EventStimulus</strong>: Activation triggered by an event, defined in the event model.<br>Contains a Counter element if activation is either shifted and / or happening every n<sup>th</sup> time.
+			</li>
+			<li>
+				<strong>CustomStimulus</strong>: To describe own custom types of activations, including properties.
+			</li>
+		</ul>
+		<ul class="validation-rule">
+			<li>
+				<em>PeriodicStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>offset</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>PeriodicStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>recurrence</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>PeriodicBurstStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>offset</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>PeriodicBurstStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>recurrence</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>PeriodicSyntheticStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>offset</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>PeriodicSyntheticStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>recurrence</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>TimestampList</em>: The 
+				<em>Time</em> objects in the role of 
+				<em>timestamps</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>SingleStimulus</em>: The 
+				<em>Time</em> object in the role of 
+				<em>occurrence</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>ArrivalCurveEntry</em>: The 
+				<em>Time</em> object in the role of 
+				<em>lowerTimeBorder</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>ArrivalCurveEntry</em>: The 
+				<em>Time</em> object in the role of 
+				<em>upperTimeBorder</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h4><a id="section3.12.1.1"></a>Single</h4>
+		<p>
+			<em>Single</em> allows to specify an activation at a single relative point in time. The single activation occurs after the time units specified by 
+			<em>occurrence</em>.
+		</p>
+		<p>
+			<img src="images/model_stimuli_single.png" style="width:600px"/>
+		</p>
+
+
+<h4><a id="section3.12.1.2"></a>Arrival Curves</h4>
+		<p>An arrival curve is described as a list of time-borders in which a specified number of activations are expected. The picture below shows an example for this. In the first picture there is a number of occurrences on a timeline.</p>
+		<p>
+			<img src="images/model_stimuli_arrival_curve_1.png" style="width:500px"/>
+		</p>
+		<p>In the picture below every distance between two activations is measured. The minimum and the maximum distance is added to the table as time-border for the occurrence of two activations. This means that after one activations there has to be at least a gap of one time-unit before the next activations can occur. It also means that there will be always a second activations within eight time units after the last activations. Basically this would be enough to describe an Arrival Curve Stimulus. But it is possible to create a more precise stimulus by describing additional time borders for greater number of occurrences. This is shown in the steps below. </p>
+		<p>
+			<img src="images/model_stimuli_arrival_curve_2.png" style="width:400px"/>
+		</p>
+		<p>The same as for two activations in the picture above is done here for three activations. Like already mentioned above, this is an additional restriction for occurrence of an activations. </p>
+		<p>
+			<img src="images/model_stimuli_arrival_curve_3.png" style="width:400px"/>
+		</p>
+		<p>And for four activations:</p>
+		<p>
+			<img src="images/model_stimuli_arrival_curve_4.png" style="width:400px"/>
+		</p>
+		<p>The picture below shows the table as arrival curve graph. The red line is the upper-time-border that shows the latest time where the activations will occur. The green line shows the earliest possible time where the activations can occur. </p>
+		<p>
+			<img src="images/model_stimuli_arrival_curve_5.png" style="width:600px"/>
+		</p>
+
+
+<h4><a id="section3.12.1.3"></a>FixedPeriodic</h4>
+		<p>In general all period based Stimuli specify periodic activations based on an offset and a recurrence. The first activation occurs after the time units specified by 
+			<em>offset</em>, and then every following activation occurs after the time units specified by 
+			<em>recurrence</em>. This means, in general, an activation of instance i is triggered at time t = 
+			<em>offset</em> + i * 
+			<em>recurrence</em>.
+		</p>
+		<p>The following figure shows a 
+			<em>Periodic</em> Stimulus example with only a fix offset and recurrence time. 
+		</p>
+		<p>
+			<img src="images/model_stimuli_periodic.png" style="width:650px"/>
+		</p>
+
+
+<h4><a id="section3.12.1.4"></a>Periodic </h4>
+		<p>In addition to the standard periodic behavior the 
+			<em>Periodic</em> Stimulus can be extended by a 
+			<em>Jitter</em> e.g. an Gaussian deviation. The activation time of each occurrence jitters according to the values of the distribution as depicted in the following figure. Depending on the 
+			<em>Jitter</em> distribution the upper bound of the current and the lower bound of the next activation can be close to each other or even overlap. The 
+			<em>minDistance</em> value allows the user to define the minimum distance between the current and the next activation.
+		</p>
+		<p>
+			<img src="images/model_stimuli_periodic_jitter.png" style="width:650px"/>
+		</p>
+		<p>The recurrence of a 
+			<em>Periodic</em> Stimulus is absolute. This means that a recurrence of 10ms points exactly to the next activation every 10ms. The 
+			<em>Jitter</em> describes the deviation of the occurrence around this absolute value.     
+		</p>
+
+
+<h4><a id="section3.12.1.5"></a>PeriodicSynthetic</h4>
+		<p>
+			<em>PeriodicSynthetic</em> allows to specify a periodic activation of trigger patterns. It is defined by a list of List of 
+			<em>occurrenceTimes</em>, a period 
+			<em>recurrence</em>, and an 
+			<em>offset</em>. Each time value in 
+			<em>occurrenceTimes</em> specifies a single activation at a relative point in time. The moment in time these time values are relative and is defined the following way: an activation of instance i is triggered at time t = 
+			<em>offset</em> + floor(i / m) * 
+			<em>recurrence</em> + 
+			<em>occurrenceTimes</em>[i modulo m].
+		</p>
+		<p>The following figure shows a 
+			<em>Synthetic</em> Stimulus example with two periodic activations after the time units T1 and T2.
+		</p>
+		<p>
+			<img src="images/model_stimuli_synthetic.png"/>
+		</p>
+
+
+<h4><a id="section3.12.1.6"></a>PeriodicBurst</h4>
+		<p>The 
+			<em>PeriodicBurst</em> Stimulus specifies a set of burst activations that are periodically repeated. This means that multiple activations occur very close to each other and this recurs in a periodic matter. The burst pattern has a fixed recurrence period and every burst results in multiple activations. 
+		</p>
+		<p>
+			<img src="images/model_stimuli_periodic_burst.png" style="width:700px"/>
+		</p>
+		<p>The number of occurrences per burst are specified via 
+			<em>occurrenceCount</em>. The 
+			<em>occurrenceMinDinstance</em> defines the minimal distance between them. The 
+			<em>burstLength</em> defines the maximum time the burst pattern can last. If the number of occurrences multiplied with the minimum distance between activations is bigger than the 
+			<em>burstLength</em> only the number of activations that fit into the 
+			<em>burstLength</em> are executed. 
+		</p>
+
+
+<h4><a id="section3.12.1.7"></a>RelativePeriodic </h4>
+		<p>In contrast to the 
+			<em>Periodic</em> Stimulus the 
+			<em>RelativePeriodic</em> Stimulus allows to specify relative recurrences. The next activation depends on the current activation time and the added deviation for the next step. The 
+			<em>lower</em> and 
+			<em>upperBound</em> are specified in the 
+			<em>nextOccurrence</em> deviation similar to the 
+			<em>Jitter</em> specification in the 
+			<em>Periodic</em> Stimulus.       
+		</p>
+		<p>
+			<img src="images/model_stimuli_periodic_relative.png" style="width:700px"/>
+		</p>
+
+
+<h4><a id="section3.12.1.8"></a>VariableRateStimulus</h4>
+		<p>With the 
+			<em>VariableRate</em> Stimulus the description of task activation based on e.g. the crankshaft rotation speed or other adaptive variable rate activations.
+		</p>
+		<p>The 
+			<em>step</em> has to be defined as a base value for the following specifications.<br>
+			<br>In the deviation 
+			<em>occurrencesPerStep</em> the lower and upper frequency of the variable rate are described. The distribution can be used to describe the standard frequency occurrences. The user can describe that the frequency is distributed e.g. uniformly over the complete frequency band or as another example the occurrences happens mostly at the 
+			<em>Boundaries</em> of the frequency band that can be specfied with the 
+			<em>CornerCase</em> 
+			<em>samplingType</em> in the distribution.<br>
+			<br>The user can set 
+			<em>maxDecrease</em> and 
+			<em>maxIncrease</em> values to describe the number of additional respectively reduced task activations that can occur within a predefined time 
+			<em>step</em>. With these values, the maximum acceleration and maximum deceleration of the stimuli can be calculated.
+		</p>
+		<p>
+			<img src="images/model_stimuli_variablerate.png" style="width:700px"/>
+		</p>
+		<p>An additional feature for the 
+			<em>variableRate</em> Stimulus is the description of 
+			<em>simulationScenario</em> that specifies the progression of the 
+			<em>variableRate</em> over time.
+			<br>In contract to the generic specification via statistical values the scenario defines the computation via the 
+			<em>recurrence</em> property that is modified by a factor based on a 
+			<em>clock</em>.
+		</p>
+
+
+<h3><a id="section3.12.2">3.12.2 </a>Clocks</h3>
+		<p>The 
+			<em>clock</em> is a time base which describes the progress of time for one or more variable rate stimuli in relation to global time.
+			<br>If two equal stimuli have a different time base, the time of task activation can be different. There are different kind of clock functions, the clock sinus function, the clock triangle function and the clock multiplier list. The clock multiplier list is a list of timestamp-multiplier value pairs. Is a specified timestamp arrived, the clock changes to the corresponding multiplier value.
+		</p>
+		<p>
+			<img class="scale" src="images/model_stimuli_clocks.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li>
+				<em>ClockTriangleFunction</em>: The 
+				<em>Time</em> object in the role of 
+				<em>period</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>ClockSinusFunction</em>: The 
+				<em>Time</em> object in the role of 
+				<em>period</em> must not contain a negative value!
+			</li>
+			<li>
+				<em>ClockMultiplierListEntry</em>: The 
+				<em>Time</em> object in the role of 
+				<em>time</em> must not contain a negative value!
+			</li>
+		</ul>
+
+
+<h3><a id="section3.12.3">3.12.3 </a>Mode label lists</h3>
+		<p>It is possible to define lists of mode label values for a stimulus. An entry in this list is always a pair of a mode label and a mode literal.</p>
+		<p>
+			<img class="scale" src="images/model_stimuli_modevaluelist.png"/>
+		</p>
+		<ul class="validation-rule">
+			<li> 
+				<em>ModeValue</em>: The 
+				<em>Mode</em> objects referenced via 
+				<em>valueProvider</em> and 
+				<em>value</em> must be equal!
+			</li>
+		</ul>
+		<p>The 
+			<strong>set-mode-labels-list</strong> indicates: Each time the stimulus is triggered all mode labels in this list are set to the corresponding value. 
+		</p>
+		<p>The 
+			<strong>enabling-mode-label-list</strong> and the 
+			<strong>disabling-mode-label-list</strong> can be used to enable or disable a stimulus by setting the mode label to a specific value (e.g. by a write access with a runnable).
+		</p>
+		<p>Meaning:</p>
+		<ul>
+			<li>If there are no list entries at all, the stimulus is enabled.</li>
+			<li>If only the disabling-list has entries, the stimulus is disabled if the condition is fulfilled, otherwise enabled.</li>
+			<li>If only the enabling-list has entries, the stimuli is enabled if the condition is fulfilled, otherwise disabled.  </li>
+			<li>If there are entries in both lists, disabling has precedence.</li>
+		</ul>
+		<table class="classic" style="text-align:center;margin-left:50px">
+			<tr>
+				<td colspan="2" rowspan="2"/>
+				<td colspan="2" rowspan="1">
+					<em>disabling-list</em>
+				</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">true</td>
+				<td colspan="1" rowspan="1">false</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="2">
+					<em>enabling-list</em>
+				</td>
+				<td colspan="1" rowspan="1">true</td>
+				<td colspan="1" rowspan="1" style="color:red">disabled</td>
+				<td colspan="1" rowspan="1" style="color:green">enabled</td>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">false</td>
+				<td colspan="1" rowspan="1" style="color:red">disabled</td>
+				<td colspan="1" rowspan="1" style="color:red">disabled</td>
+			</tr>
+		</table>
+
+
+<h2><a id="section3.13">3.13 </a>Software Model</h2>
+		<p>The AMALTHEA software model is central accessible through the 
+			<i>SWModel</i> element. 
+		</p>
+
+
+<h3><a id="section3.13.1">3.13.1 </a>Memory Information</h3>
+		<p>Analyzing and mapping the software structure to available memories needs additional information of the included elements. This type of information targets the consumed size of memory of an element, represented by the 
+			<i>size</i> attribute of type 
+			<i>DataUnit</i>. The element 
+			<i>AbstractMemoryElement</i> is a generalized element that provides this data. The following image shows the structure and also the elements of the software model that are extending 
+			<i>AbstractMemoryElement</i> (the overview picture is only showing the hierarchy and not possible relationships between the elements):
+		</p>
+		<p>
+			<img class="scale" src="images/model_sw_memory_inf.png"/>
+		</p>
+
+
+<h3><a id="section3.13.2">3.13.2 </a>Labels</h3>
+		<p>The label element represents a data element. It is directly located in a defined area of a given memory.
+			<br>It can be used as a parameter, a temporarily existing variable or representing a  constant value.
+		</p>
+		<p>
+			<img src="images/model_sw_label.png"/>
+		</p>
+		<p>The following attributes are describing a label:</p>
+		<table class="minimal" style="padding:10px; border:1px solid black; background:#f8f8f8">
+			<tr>
+				<th colspan="1" rowspan="1">Name</th>
+				<th colspan="1" rowspan="1">Description</th>
+			</tr>
+			<tr>
+				<td colspan="1" rowspan="1">
+					<i>name</i>
+