Update ARM support.
diff --git a/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/InstructionParserARM.java b/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/InstructionParserARM.java
index b8056ba..50b193d 100644
--- a/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/InstructionParserARM.java
+++ b/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/InstructionParserARM.java
@@ -210,7 +210,7 @@
/**
* Disassemble a 32-bit ARM instruction
* Reference manual citations (e.g., "A8.6.16") refer to sections in the ARM Architecture
- * Reference Manual ARMv7-A and ARMv7-R Edition with errata markup
+ * Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
* @return disassembled instruction
*/
private String parseARMOpcode() {
@@ -263,7 +263,6 @@
isSubroutineAddress = (opcodeIndex == OpcodeARM.Index.arm_bl); // only bl is a subroutine call
jumpToAddr = address.add(offset); // immediate address known
instruction = mnemonic + condString + "\t" + jumpToAddr.toHexAddressString();
- // No pc check: not applicable
break;
case arm_blx__imm: // A8.6.23 BL, BLX (immediate)
@@ -273,7 +272,6 @@
isSubroutineAddress = true;
jumpToAddr = address.add(offset); // immediate address known
instruction = mnemonic + "\t" + jumpToAddr.toHexAddressString();
- // No pc check: not applicable
break;
case arm_blx__reg: // A8.6.24 BLX (register)
@@ -284,7 +282,6 @@
isSoleDestination = (condString.length() == 0); // true if unconditional blx
isSubroutineAddress = true;
addrExpression = tempStr; // branches to the address in Rm register
- // No pc check: not applicable
break;
case arm_bx: // A8.6.25 BX
@@ -297,7 +294,6 @@
isSoleDestination = (condString.length() == 0); // true if unconditional bx
isSubroutineAddress = false;
addrExpression = tempStr; // branches to the address in Rm register
- // No pc check: not applicable
break;
case arm_adc__imm: // A8.6.1 ADC (immediate)
@@ -306,8 +302,12 @@
// adc{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
case arm_add__imm: // A8.6.5 ADD (immediate, ARM)
// add{s}<c> <Rd>,<Rn>,#<const>
+ // A8.6.8 ADD (SP plus immediate)
+ // add{s}<c> <Rd>,sp,#<const>
case arm_add__reg: // A8.6.6 ADD (register)
// add{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
+ // A8.6.9 ADD (SP plus register)
+ // add{s}<c> <Rd>,sp,<Rm>{,<shift>}
case arm_and__imm: // A8.6.11 AND (immediate)
// and{s}<c> <Rd>,<Rn>,#<const>
case arm_and__reg: // A8.6.12 AND (register)
@@ -330,7 +330,7 @@
// rsb{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
case arm_rsc__imm: // A8.6.145 RSC (immediate)
// rsc{s}<c> <Rd>,<Rn>,#<const>
- case arm_rsc__reg: // A8.6.146 RSC (register)
+ case arm_rsc__reg: // A8.6.146 RSC (register)
// rsc{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
case arm_sbc__imm: // A8.6.151 SBC (immediate)
// sbc{s}<c> <Rd>,<Rn>,#<const>
@@ -338,8 +338,12 @@
// sbc{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
case arm_sub__imm: // A8.6.212 SUB (immediate, ARM)
// sub{s}<c> <Rd>,<Rn>,#<const>
+ // A8.6.215 SUB (SP minus immediate)
+ // sub{s}<c> <Rd>,sp,#<const>
case arm_sub__reg: // A8.6.213 SUB (register)
// sub{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
+ // A8.6.216 SUB (SP minus register)
+ // sub{s} <Rd>,sp,<Rm>{,<shift>}
condString = getArmCondition(opcode);
tempStr = getR_12(opcode);
instruction = mnemonic + getS(opcode) + condString + "\t"
@@ -371,7 +375,7 @@
// sub{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getShifterOperand(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_adr__higher: // A8.6.10 ADR
@@ -419,7 +423,7 @@
// ror{s}<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd, Rn, or Rm is PC, the instruction is unpredictable
+ // No PC check: if Rd, Rn, or Rm is PC, the instruction is UNPREDICTABLE
break;
case arm_bfc: // A8.6.17 BFC
@@ -433,7 +437,7 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",#" + lsb + ",#" + width;
}
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_bfi: // A8.6.18 BFI
@@ -447,13 +451,13 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode) + ",#" + lsb + ",#" + width;
}
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_bkpt: // A8.6.22 BKPT
// bkpt #<imm16>
instruction = mnemonic + "\t" + "#" + getHexValue((((opcode >> 4) & 0xfff0) | (opcode & 0xf)));
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_cdp: // A8.6.28 CDP, CDP2
@@ -462,7 +466,7 @@
case arm_cdp2: // A8.6.28 CDP, CDP2
// cdp2<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
instruction = mnemonic + "\t" + getCo_cdp_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_clrex: // A8.6.30 CLREX
@@ -472,7 +476,7 @@
break;
}
instruction = mnemonic;
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_clz: // A8.6.31 CLZ
@@ -486,7 +490,7 @@
case arm_revsh: // A8.6.137 REVSH
// revsh<c> <Rd>,<Rm>
instruction = mnemonic + getArmCondition(opcode) + "\t" + getR_12(opcode) + "," + getR_0(opcode);
- // No pc check: if Rd or Rm is PC, the instruction is unpredictable
+ // No PC check: if Rd or Rm is PC, the instruction is UNPREDICTABLE
break;
case arm_cmn__imm: // A8.6.32 CMN (immediate)
@@ -499,7 +503,7 @@
// tst<c> <Rn>,#<const>
imm = opcode & 0xfff;
instruction = mnemonic + getArmCondition(opcode) + "\t" + getR_16(opcode) + "," + getShifterOperand(opcode);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
case arm_cmn__reg: // A8.6.33 CMN (register)
@@ -520,14 +524,14 @@
// tst<c> <Rn>,<Rm>,<type> <Rs>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getShifterOperand(opcode);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
case arm_cps: // B6.1.1 CPS
- // cps #<mode>
// cps<effect> <iflags>{,#<mode>}
+ // cps #<mode>
instruction = mnemonic + getCo_cps_instruction(opcode, false);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_dbg: // A8.6.40 DBG
@@ -538,7 +542,7 @@
instruction = "nop" + getArmCondition(opcode);
else
instruction = mnemonic + getArmCondition(opcode) + "\t" + "#" + (opcode & 0xf);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
case arm_dmb: // A8.6.41 DMB
@@ -549,7 +553,7 @@
instruction = IDisassembler.INVALID_OPCODE;
else
instruction = mnemonic + "\t" + getDataBarrierOption(opcode);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
case arm_isb: // A8.6.49 ISB
@@ -558,7 +562,7 @@
instruction = IDisassembler.INVALID_OPCODE;
else
instruction = mnemonic + "\t" + getInstructionBarrierOption(opcode);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
case arm_ldc__imm: // A8.6.51 LDC, LDC2 (immediate)
@@ -587,7 +591,7 @@
// stc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
instruction = mnemonic + getL(opcode) + getArmCondition(opcode) + "\t"
+ getCoprocessor(opcode) + "," + getCR_12(opcode) + "," + getAddrModeImm8(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_ldr__imm: // A8.6.58 LDR (immediate, ARM)
@@ -600,7 +604,8 @@
tempStr = getR_12(opcode);
instruction = mnemonic + condString + "\t" + tempStr + "," + getAddrMode2(opcode, 24);
- if (tempStr.equals("pc"))
+ // only the load can change the PC
+ if (isBitEnabled(opcode, 20) && tempStr.equals("pc"))
setDefaultPCJumpProperties(condString.length() == 0); // true if unconditional
break;
@@ -612,6 +617,7 @@
imm = opcode & 0xfff;
instruction = mnemonic + condString + "\t"
+ tempStr + "," + getAddrModePCImm(opcode, imm);
+
if (tempStr.equals("pc"))
setDefaultPCJumpProperties(condString.length() == 0); // true if unconditional
break;
@@ -633,7 +639,7 @@
// strb<c> <Rt>,[<Rn>],#+/-<imm12>
// strb<c> <Rt>,[<Rn>,#+/-<imm12>]!
instruction = mnemonic + getArmCondition(opcode) + "\t" + getR_12(opcode) + "," + getAddrMode2(opcode, 24);
- // No pc check: for non-str, if Rt is PC, the instruction is unpredictable;
+ // No PC check: for non-str, if Rt is PC, the instruction is UNPREDICTABLE;
// for str, the destination is memory - not a register
break;
@@ -643,7 +649,7 @@
imm = opcode & 0xfff;
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getAddrModePCImm(opcode, imm);
- // No pc check: if Rt is PC, the instruction is unpredictable;
+ // No PC check: if Rt is PC, the instruction is UNPREDICTABLE;
break;
case arm_ldrd__imm: // A8.6.66 LDRD (immediate)
@@ -654,7 +660,7 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getRegName(startReg) + "," + getRegName(startReg + 1) + ","
+ getAddrModeSplitImm8(opcode);
- // No pc check: if Rt is odd or is LR (register 14), the instruction is unpredictable
+ // No PC check: if Rt is odd or is LR (register 14), the instruction is UNPREDICTABLE
break;
case arm_ldrd__lit: // A8.6.67 LDRD (literal)
@@ -665,7 +671,7 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getRegName(startReg) + "," + getRegName(startReg + 1) + ","
+ getAddrModePCImm(opcode, imm);
- // No pc check: if Rt is odd or is LR (register 14), the instruction is unpredictable
+ // No PC check: if Rt is odd or is LR (register 14), the instruction is UNPREDICTABLE
break;
case arm_ldrh__imm: // A8.6.75 LDRH (literal)
@@ -686,7 +692,7 @@
// strh<c> <Rt>,[<Rn>,#+/-<imm8>]!
instruction = mnemonic + getArmCondition(opcode) + "\t" + getR_12(opcode)
+ "," + getAddrModeSplitImm8(opcode);
- // No pc check: if Rt is PC, the instruction is unpredictable
+ // No PC check: if Rt is PC, the instruction is UNPREDICTABLE
break;
case arm_ldrh__lit: // A8.6.75 LDRH (literal)
@@ -701,7 +707,7 @@
imm = ((opcode >> 4) & 0xf0) | (opcode & 0xf);
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getAddrModePCImm(opcode, imm);
- // No pc check: if Rt is PC, the instruction is unpredictable
+ // No PC check: if Rt is PC, the instruction is UNPREDICTABLE
break;
case arm_ldm: // A8.6.53 LDM / LDMIA / LDMFD
@@ -725,9 +731,10 @@
instruction = mnemonic + condString + "\t"
+ getR_16(opcode) + getW(opcode) + "," + tempStr;
- if (tempStr.contains("pc"))
+ // only the loads can change the PC
+ if (isBitEnabled(opcode, 20) && tempStr.contains("pc"))
setDefaultPCJumpProperties(condString.length() == 0); // true if unconditional
- // Note: having PC (register 15) in the list is deprecated
+ // Note: having PC (register 15) in the register list is deprecated
break;
case arm_ldm__exc_ret: // B6.1.2 LDM (exception return)
@@ -747,7 +754,7 @@
// stm{amode}<c> <Rn>,<registers>^
instruction = mnemonic + getAddrMode(opcode) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getRegList(opcode) + "^";
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_ldr__reg: // A8.6.60 LDR (register)
@@ -775,7 +782,7 @@
// strt<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getAddrMode2(opcode, 24);
- // No pc check: for non-str, if Rt is PC, the instruction is unpredictable
+ // No PC check: for non-str, if Rt is PC, the instruction is UNPREDICTABLE
// for str, the destination is memory - not a register
break;
@@ -788,7 +795,7 @@
startReg = (opcode >> 12) & 0xf;
instruction = mnemonic + getArmCondition(opcode) + "\t" + getRegName(startReg)
+ "," + getRegName(startReg + 1) + "," + getAddrModeSplitImm8(opcode);
- // No pc check: if Rt is odd or is LR (register 14), the instruction is unpredictable
+ // No PC check: if Rt is odd or is LR (register 14), the instruction is UNPREDICTABLE
break;
case arm_ldrex: // A8.6.69 LDREX
@@ -799,7 +806,7 @@
// ldrexh<c> <Rt>, [<Rn>]
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",[" + getR_16(opcode) + "]";
- // No pc check: if Rt is PC, the instruction is unpredictable
+ // No PC check: if Rt is PC, the instruction is UNPREDICTABLE
break;
case arm_ldrexd: // A8.6.71 LDREXD
@@ -807,7 +814,7 @@
startReg = (opcode >> 12) & 0xf;
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getRegName(startReg) + "," + getRegName(startReg + 1) + ",[" + getR_16(opcode) + "]";
- // No pc check: if Rt is odd or is LR (register 14), the instruction is unpredictable
+ // No PC check: if Rt is odd or is LR (register 14), the instruction is UNPREDICTABLE
break;
case arm_ldrh__reg: // A8.6.76 LDRH (register)
@@ -824,7 +831,7 @@
// strh<c> <Rt>,[<Rn>],+/-<Rm>
instruction = mnemonic + getArmCondition(opcode) + "\t" + getR_12(opcode)
+ "," + getAddrModeSplitImm8(opcode);
- // No pc check: for non-str, if Rt is PC, the instruction is unpredictable;
+ // No PC check: for non-str, if Rt is PC, the instruction is UNPREDICTABLE;
// for str, the destination is memory - not a register
break;
@@ -845,7 +852,7 @@
if (offset != 0)
instruction += ",#" + ((isBitEnabled(opcode, 23)) ? "" : "-") + getHexValue(offset);
}
- // No pc check: for non-str, if Rt is PC, the instruction is unpredictable;
+ // No PC check: for non-str, if Rt is PC, the instruction is UNPREDICTABLE;
// for str, the destination is memory - not a register
break;
@@ -860,7 +867,7 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",[" + getR_16(opcode)
+ (isBitEnabled(opcode, 23) ? "]," : "],-") + getR_0(opcode);
- // No pc check: for non-str, if Rt is PC, the instruction is unpredictable;
+ // No PC check: for non-str, if Rt is PC, the instruction is UNPREDICTABLE;
// for str, the destination is memory - not a register
break;
@@ -871,7 +878,7 @@
case arm_mcr2: // A8.6.92 MCR, MCR2
// mcr2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
instruction = mnemonic + getCo_mcr_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_mcrr: // A8.6.93 MCRR, MCRR2
@@ -885,14 +892,14 @@
case arm_mrrc2: // A8.6.101 MRRC, MRRC2
// mrrc2<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
instruction = mnemonic + getCo_mrr_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_mla: // A8.6.94 MLA
// mla{s}<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode) + "," + getR_12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_mls: // A8.6.95 MLS
@@ -901,7 +908,7 @@
// usada8<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode) + "," + getR_12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_mov__imm: // A8.6.96 MOV (immediate)
@@ -936,7 +943,7 @@
imm = ((opcode >> 4) & 0xf000) | (opcode & 0xfff);
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",#" + getHexValue(imm);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_mrc: // A8.6.100 MRC, MRC2
@@ -946,14 +953,14 @@
case arm_mrc2: // A8.6.100 MRC, MRC2
// mrc2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
instruction = mnemonic + getCo_mrc_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_mrs: // A8.6.102 MRS
// mrs<c> <Rd>,<spec_reg>
instruction = mnemonic + getArmCondition(opcode) + "\t" + getR_12(opcode)
- + "," + getStatusReg(opcode, 22);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ + "," + getStatusReg(opcode, 22);
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_msr__imm: // A8.6.103 MSR (immediate)
@@ -969,7 +976,7 @@
instruction += getShifterOperand(opcode);
else
instruction += getR_0(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_msr__sys_imm: // B6.1.6 MSR (immediate)
@@ -982,13 +989,14 @@
instruction += "," + getShifterOperand(opcode);
else
instruction += "," + getR_0(opcode);
+ // No PC check: not applicable
break;
case arm_mul: // A8.6.105 MUL
// mul{s}<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd, Rn, or Rm is PC, the instruction is unpredictable
+ // No PC check: if Rd, Rn, or Rm is PC, the instruction is UNPREDICTABLE
break;
case arm_mvn__reg: // A8.6.107 MVN (register)
@@ -1006,7 +1014,7 @@
// mvn{s}<c> <Rd>,<Rm>,<type> <Rs>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getShifterOperand(opcode);
- // No pc check: if Rn, Rm, or Rs is PC, the instruction is unpredictable
+ // No PC check: if Rn, Rm, or Rs is PC, the instruction is UNPREDICTABLE
break;
case arm_nop: // A8.6.110 NOP
@@ -1015,7 +1023,7 @@
instruction = IDisassembler.INVALID_OPCODE;
else
instruction = mnemonic + getArmCondition(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_pkh: // A8.6.116 PKH
@@ -1035,7 +1043,7 @@
if (imm != 0)
instruction += ",lsl #" + imm;
}
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_pld__lit: // A8.6.118 PLD (literal)
@@ -1043,20 +1051,20 @@
// pld [pc,#+/-<imm>] Alternative form
imm = opcode & 0xfff;
instruction = mnemonic + "\t" + getAddrModePCImm(opcode, imm);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_pld__imm: // A8.6.117 PLD, PLDW (immediate)
// pld{w} [<Rn>,#+/-<imm12>]
instruction = mnemonic + (isBitEnabled(opcode, 22) ? "\t" : "w\t") + getAddrMode2(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_pld__reg: // A8.6.119 PLD, PLDW (register)
// pld{w}<c> [<Rn>,+/-<Rm>{, <shift>}]
mnemonic += (isBitEnabled(opcode, 22) ? "\t" : "w\t") + getArmCondition(opcode);
instruction = mnemonic + "\t" + getAddrMode2(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_pli__imm_lit: // A8.6.120 PLI (immediate, literal)
@@ -1068,17 +1076,17 @@
+ (getR_16(opcode).equals("pc")
? getAddrModePCImm(opcode, imm)
: getAddrMode2(opcode, 20)); // picked bit 20 because it is 1
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_pli__reg: // A8.6.121 PLI (register)
// pli [<Rn>,+/-<Rm>{, <shift>}]
instruction = mnemonic + "\t" + getAddrMode2(opcode, 20); // picked bit 20 because it is 1
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_pop__regs: // A8.6.122 POP
- // pop<c> <registers> <registers> has more than one register
+ // pop<c> <registers> <registers> contains more than one register
condString = getArmCondition(opcode);
tempStr = getRegList(opcode);
instruction = mnemonic + condString + "\t" + tempStr;
@@ -1088,25 +1096,25 @@
break;
case arm_pop__reg: // A8.6.122 POP
- // pop<c> <registers> <registers> has one register, <Rt>
+ // pop<c> <registers> <registers> contains one register, <Rt>
condString = getArmCondition(opcode);
tempStr = getR_12(opcode);
instruction = mnemonic + condString + "\t{" + tempStr + "}";
-
+
if (tempStr.equals("pc"))
- setDefaultPCJumpProperties(condString.length() == 0); // true if unconditional
+ setDefaultPCJumpProperties(condString.length() == 0); // true if unconditional
break;
case arm_push__reg: // A8.6.123 PUSH
- // push<c> <registers> <registers> has one register, <Rt>
+ // push<c> <registers> <registers> contains one register, <Rt>
instruction = mnemonic + getArmCondition(opcode) + "\t{" + getR_12(opcode) + "}";
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_push__regs: // A8.6.123 PUSH
- // push<c> <registers> <registers> has more than one register
+ // push<c> <registers> <registers> contains more than one register
instruction = mnemonic + getArmCondition(opcode) + "\t" + getRegList(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_qadd: // A8.6.124 QADD
@@ -1119,82 +1127,81 @@
// qsub<c> <Rd>,<Rm>,<Rn>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode) + "," + getR_16(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
-// case arm_qadd16: // A8.6.125 QADD16
-// // qadd16<c> <Rd>,<Rn>,<Rm>
-// case arm_qadd8: // A8.6.126 QADD8
-// // qadd8<c> <Rd>,<Rn>,<Rm>
-// case arm_qasx: // A8.6.127 QASX
-// // qasx<c> <Rd>,<Rn>,<Rm>
-// case arm_qsax: // A8.6.130 QSAX
-// // qsax<c> <Rd>,<Rn>,<Rm>
-// case arm_qsub16: // A8.6.132 QSUB16
-// // qsub16<c> <Rd>,<Rn>,<Rm>
-// case arm_qsub8: // A8.6.133 QSUB8
-// // qsub8<c> <Rd>,<Rn>,<Rm>
-// case arm_sadd16: // A8.6.148 SADD16
-// // sadd16<c> <Rd>,<Rn>,<Rm>
-// case arm_sadd8: // A8.6.149 SADD8
-// // sadd8<c> <Rd>,<Rn>,<Rm>
-// case arm_sasx: // A8.6.150 SASX
-// // sasx<c> <Rd>,<Rn>,<Rm>
-// case arm_shadd16: // A8.6.159 SHADD16
-// // shadd16<c> <Rd>,<Rn>,<Rm>
-// case arm_shadd8: // A8.6.160 SHADD8
-// // shadd8<c> <Rd>,<Rn>,<Rm>
-// case arm_shasx: // A8.6.161 SHASX
-// // shasx<c> <Rd>,<Rn>,<Rm>
-// case arm_shsax: // A8.6.162 SHSAX
-// // shsax<c> <Rd>,<Rn>,<Rm>
-// case arm_shsub16: // A8.6.163 SHSUB16
-// // shsub16<c> <Rd>,<Rn>,<Rm>
-// case arm_shsub8: // A8.6.164 SHSUB8
-// // shsub8<c> <Rd>,<Rn>,<Rm>
-// case arm_ssax: // A8.6.185 SSAX
-// // ssax<c> <Rd>,<Rn>,<Rm>
-// case arm_ssub16: // A8.6.186 SSUB16
-// // ssub16<c> <Rd>,<Rn>,<Rm>
-// case arm_ssub8: // A8.6.187 SSUB8
-// // ssub8<c> <Rd>,<Rn>,<Rm>
-// case arm_uadd16: // A8.6.233 UADD16
-// // uadd16<c> <Rd>,<Rn>,<Rm>
-// case arm_uadd8: // A8.6.234 UADD8
-// // uadd8<c> <Rd>,<Rn>,<Rm>
-// case arm_uasx: // A8.6.235 UASX
-// // uasx<c> <Rd>,<Rn>,<Rm>
-// case arm_uhadd16: // A8.6.238 UHADD16
-// // uhadd16<c> <Rd>,<Rn>,<Rm>
-// case arm_uhadd8: // A8.6.239 UHADD8
-// // uhadd8<c> <Rd>,<Rn>,<Rm>
-// case arm_uhasx: // A8.6.240 UHASX
-// // uhasx<c> <Rd>,<Rn>,<Rm>
-// case arm_uhsax: // A8.6.241 UHSAX
-// // uhsax<c> <Rd>,<Rn>,<Rm>
-// case arm_uhsub16: // A8.6.242 UHSUB16
-// // uhsub16<c> <Rd>,<Rn>,<Rm>
-// case arm_uhsub8: // A8.6.243 UHSUB8
-// // uhsub8<c> <Rd>,<Rn>,<Rm>
-// case arm_uqadd16: // A8.6.247 UQADD16
-// // uqadd16<c> <Rd>,<Rn>,<Rm>
-// case arm_uqadd8: // A8.6.248 UQADD8
-// // uqadd8<c> <Rd>,<Rn>,<Rm>
-// case arm_uqasx: // A8.6.249 UQASX
-// // uqasx<c> <Rd>,<Rn>,<Rm>
-// case arm_uqsax: // A8.6.250 UQSAX
-// // uqsax<c> <Rd>,<Rn>,<Rm>
-// case arm_uqsub16: // A8.6.251 UQSUB16
-// // uqsub16<c> <Rd>,<Rn>,<Rm>
-// case arm_uqsub8: // A8.6.252 UQSUB8
-// // uqsub8<c> <Rd>,<Rn>,<Rm>
-// case arm_usax: // A8.6.257 USAX
-// // usax<c> <Rd>,<Rn>,<Rm>
-// case arm_usub16: // A8.6.258 USUB16
-// // usub16<c> <Rd>,<Rn>,<Rm>
-// case arm_usub8: // A8.6.259 USUB8
-// // usub8<c> <Rd>,<Rn>,<Rm>
- case arm__r_dnm_math:
+ case arm__r_dnm_math: // A8.6.125 QADD16
+ // qadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.126 QADD8
+ // qadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.127 QASX
+ // qasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.130 QSAX
+ // qsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.132 QSUB16
+ // qsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.133 QSUB8
+ // qsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.148 SADD16
+ // sadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.149 SADD8
+ // sadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.150 SASX
+ // sasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.159 SHADD16
+ // shadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.160 SHADD8
+ // shadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.161 SHASX
+ // shasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.162 SHSAX
+ // shsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.163 SHSUB16
+ // shsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.164 SHSUB8
+ // shsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.185 SSAX
+ // ssax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.186 SSUB16
+ // ssub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.187 SSUB8
+ // ssub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.233 UADD16
+ // uadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.234 UADD8
+ // uadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.235 UASX
+ // uasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.238 UHADD16
+ // uhadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.239 UHADD8
+ // uhadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.240 UHASX
+ // uhasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.241 UHSAX
+ // uhsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.242 UHSUB16
+ // uhsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.243 UHSUB8
+ // uhsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.247 UQADD16
+ // uqadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.248 UQADD8
+ // uqadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.249 UQASX
+ // uqasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.250 UQSAX
+ // uqsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.251 UQSUB16
+ // uqsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.252 UQSUB8
+ // uqsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.257 USAX
+ // usax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.258 USUB16
+ // usub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.259 USUB8
+ // usub8<c> <Rd>,<Rn>,<Rm>
switch (opcode >> 20 & 7) {
case 1: mnemonic = "s"; break;
case 2: mnemonic = "q"; break;
@@ -1217,7 +1224,7 @@
// sel<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode);
- // No pc check: if Rd, Rn, or Rm is PC, the instruction is unpredictable
+ // No PC check: if Rd, Rn, or Rm is PC, the instruction is UNPREDICTABLE
break;
case arm_rfe: // B6.1.8 RFE
@@ -1239,7 +1246,7 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode) + ",#" + lsb + ",#" +width;
}
- // No pc check: for non-str, if Rd is PC, the instruction is unpredictable;
+ // No PC check: for non-str, if Rd is PC, the instruction is UNPREDICTABLE;
// for str, the destination is memory - not a register
break;
@@ -1250,6 +1257,7 @@
instruction = instruction + "le";
else
instruction = instruction + "be";
+ // No PC check: not applicable
break;
case arm_sev: // A8.6.158 SEV
@@ -1266,20 +1274,20 @@
instruction = "nop" + getArmCondition(opcode);
else
instruction = mnemonic + getArmCondition(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_smc: // B6.1.9 SMC (previously SMI)
// smc<c> #<imm4>
instruction = mnemonic + getArmCondition(opcode) + "\t#" + getHexValue((opcode & 0xf));
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_smla: // A8.6.166 SMLABB, SMLABT, SMLATB, SMLATT
// smla<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getBorT(opcode, 5) + getBorT(opcode, 6) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode) + "," + getR_12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smlad: // A8.6.167 SMLAD
@@ -1288,21 +1296,21 @@
// smlsd{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getX(opcode, 5) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode) + "," + getR_12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smlal: // A8.6.168 SMLAL
// smlal{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if RdLo or RdHi is PC, the instruction is unpredictable
+ // No PC check: if RdLo or RdHi is PC, the instruction is UNPREDICTABLE
break;
case arm_smlalxy: // A8.6.169 SMLALBB, SMLALBT, SMLALTB, SMLALTT
// smlal<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getBorT(opcode, 5) + getBorT(opcode, 6) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if RdLo or RdHi is PC, the instruction is unpredictable
+ // No PC check: if RdLo or RdHi is PC, the instruction is UNPREDICTABLE
break;
case arm_smlald: // A8.6.170 SMLALD
@@ -1311,14 +1319,14 @@
// smlsld{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getX(opcode, 5) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smlaw: // A8.6.171 SMLAWB, SMLAWT
// smlaw<y><c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getBorT(opcode, 6) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode) + "," + getR_12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smmla: // A8.6.174 SMMLA
@@ -1327,14 +1335,14 @@
// smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getR(opcode, 5) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode) + "," + getR_12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smmul: // A8.6.176 SMMUL
// smmul{r}<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getR(opcode, 5) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smuad: // A8.6.177 SMUAD
@@ -1343,34 +1351,35 @@
// smusd{x}<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getX(opcode, 5) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smul: // A8.6.178 SMULBB, SMULBT, SMULTB, SMULTT
// smul<x><y><c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getBorT(opcode, 5) + getBorT(opcode, 6) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_smull: // A8.6.179 SMULL
// smull{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if RdLo or RdHi is PC, the instruction is unpredictable
+ // No PC check: if RdLo or RdHi is PC, the instruction is UNPREDICTABLE
break;
case arm_smulw: // A8.6.180 SMULWB, SMULWT
// smulw<y><c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getBorT(opcode, 6) + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_srs: // B6.1.10 SRS
// srs{<amode>} sp{!},#<mode>
instruction = mnemonic + getAddrMode(opcode) + "\t"
+ "sp" + getW(opcode) + ",#" + getHexValue((opcode & 0x1f));
+ // No PC check: not applicable
break;
case arm_ssat: // A8.6.183 SSAT
@@ -1380,7 +1389,7 @@
imm = ((opcode >> 16) & 0x1f);
if ((opcode & (1 << 22)) == 0)
imm++;
-
+
if (((opcode >> 6) & 0x3f) != 0) {
int shiftCnt = (opcode >> 7) & 0x1f;
if ((opcode & (1 << 6)) == 0)
@@ -1393,7 +1402,7 @@
}
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",#" + imm + "," + getR_0(opcode) + tempStr;
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_ssat16: // A8.6.184 SSAT16
@@ -1401,7 +1410,7 @@
imm = ((opcode >> 16) & 0xf) + 1;
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",#" + imm + "," + getR_0(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_str__reg: // A8.6.195 STR (register)
@@ -1414,7 +1423,7 @@
// strbt<c> <Rt>,[<Rn>],#+/-<imm12>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + "\t" + getR_12(opcode) + "," + getAddrMode2(opcode, 24);
- // No pc check: if Rt is PC, the instruction is unpredictable;
+ // No PC check: if Rt is PC, the instruction is UNPREDICTABLE;
break;
case arm_strd__imm: // A8.6.200 STRD (immediate)
@@ -1424,7 +1433,7 @@
reg = (opcode >> 12) & 0xf;
instruction = mnemonic + getArmCondition(opcode) + "\t" + getRegName(reg)
+ "," + getRegName(reg + 1) + "," + getAddrModeSplitImm8(opcode);
- // No pc check: if Rt is odd or is LR (register 14), the instruction is unpredictable
+ // No PC check: if Rt is odd or is LR (register 14), the instruction is UNPREDICTABLE
break;
case arm_strex: // A8.6.202 STREX
@@ -1435,7 +1444,7 @@
// strexh<c> <Rd>,<Rt>,[<Rn>]
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode) + ",[" + getR_16(opcode) + "]";
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_strexd: // A8.6.204 STREXD
@@ -1444,20 +1453,20 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getRegName(startReg) + ","
+ getRegName(startReg + 1) + ",[" + getR_16(opcode) + "]";
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_svc: // A8.6.218 SVC (previously SWI)
// svc<c> #<imm24>
instruction = mnemonic + getArmCondition(opcode) + "\t" + getImmediate24(opcode);
- // No pc check: the destination is memory - not a register
+ // No PC check: the destination is memory - not a register
break;
case arm_swp: // A8.6.219 SWP, SWPB
// swp{b}<c> <Rt>,<Rt2>,[<Rn>]
instruction = mnemonic + getB(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode) + ",[" + getR_16(opcode) + "]";
- // No pc check: if Rt or Rt2 is PC, the instruction is unpredictable
+ // No PC check: if Rt or Rt2 is PC, the instruction is UNPREDICTABLE
break;
case arm_sxtab: // A8.6.220 SXTAB
@@ -1475,7 +1484,7 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode)
+ getRotationOperand(opcode, 10);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_sxtb: // A8.6.223 SXTB
@@ -1493,14 +1502,14 @@
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_0(opcode)
+ getRotationOperand(opcode, 10);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_umaal: // A8.6.244 UMAAL
// umaal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if RdLo or RdHi is PC, the instruction is unpredictable
+ // No PC check: if RdLo or RdHi is PC, the instruction is UNPREDICTABLE
break;
case arm_umlal: // A8.6.245 UMLAL
@@ -1509,26 +1518,26 @@
// umull{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getS(opcode) + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if RdLo or RdHi is PC, the instruction is unpredictable
+ // No PC check: if RdLo or RdHi is PC, the instruction is UNPREDICTABLE
break;
case arm_usad8: // A8.6.253 USAD8
// usad8<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_16(opcode) + "," + getR_0(opcode) + "," + getR_8(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_usat16: // A8.6.256 USAT16
// usat16<c> <Rd>,#<imm4>,<Rn>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + ",#" + ((opcode >> 16) & 0xf) + "," + getR_0(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
case arm_undefined:
instruction = mnemonic;
- // No pc check: not applicable
+ // No PC check: not applicable
break;
// VFP instructions
@@ -1561,7 +1570,7 @@
// vqsub<c>.<type><size> <Qd>, <Qn>, <Qm>
// vqsub<c>.<type><size> <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFPSorUDataType(opcode, 24) + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vqdml__vec: // A8.6.358 VQDMLAL, VQDMLSL
@@ -1579,9 +1588,9 @@
// bit24 == 0, so can use getVFPSorUDataType
instruction = mnemonic + getVFPSorUDataType(opcode, 24)
+ TAB + getVFPQdDnDmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
-
+
case arm_vabd__f32: // A8.6.268 VABD (floating-point)
// vabd<c>.f32 <Qd>, <Qn>, <Qm>
// vabd<c>.f32 <Dd>, <Dn>, <Dm>
@@ -1612,7 +1621,7 @@
// vsub<c>.f32 <Qd>, <Qn>, <Qm>
// vsub<c>.f32 <Dd>, <Dn>, <Dm>
instruction = mnemonic + ".f32\t" + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vabs: // A8.6.269 VABS
@@ -1622,7 +1631,7 @@
// vneg<c>.<dt> <Qd>, <Qm>
// vneg<c>.<dt> <Dd>, <Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 10, 4); // chose bit 4 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vabs__f: // A8.6.269 VABS
@@ -1638,7 +1647,7 @@
// vsqrt<c>.f64 <Dd>, <Dm>
// vsqrt<c>.f32 <Sd>, <Sm>
instruction = mnemonic + getArmCondition(opcode) + getVFPSzF64F32dmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vacge_vacgt: // A8.6.270 VACGE, VACGT, VACLE, VACLT
@@ -1647,7 +1656,7 @@
// vacgt<c>.f32 <Qd>, <Qn>, <Qm>
// vacgt<c>.f32 <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFP_vacge_vacgt(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vadd__int: // A8.6.271 VADD (integer)
@@ -1662,7 +1671,7 @@
// vsub<c>.<dt> <Qd>, <Qn>, <Qm>
// vsub<c>.<dt> <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFPIDataTypeQorDdnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vnml: // A8.6.343 VNMLA, VNMLS, VNMUL
@@ -1688,7 +1697,7 @@
// vsub<c>.f64 <Dd>, <Dn>, <Dm>
// vsub<c>.f32 <Sd>, <Sn>, <Sm>
instruction = mnemonic + getArmCondition(opcode) + getVFPSzF64F32dnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vaddhn: // A8.6.273 VADDHN
@@ -1700,7 +1709,7 @@
case arm_vsubhn: // A8.6.403 VSUBHN
// vsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
instruction = mnemonic + getVFPIDataType2DdQnDmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vaddl_vaddw: // A8.6.274 VADDL, VADDW
@@ -1710,7 +1719,7 @@
// vsubl<c>.<dt> <Qd>, <Dn>, <Dm>
// vsubw<c>.<dt> {<Qd>,} <Qn>, <Dm>
instruction = mnemonic + getVFP_vXXXl_vXXXw(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vbif_vbit_vbsl_veor: // A8.6.279 VBIF, VBIT, VBSL
@@ -1734,11 +1743,24 @@
case arm_vorn: // A8.6.345 VORN (register)
// vorn<c> <Qd>, <Qn>, <Qm>
// vorn<c> <Dd>, <Dn>, <Dm>
- case arm_vorr: // A8.6.347 VORR (register)
+ instruction = mnemonic + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
+ break;
+
+ case arm_vmov_vorr: // A8.6.327 VMOV (register)
+ // vmov<c> <Qd>, <Qm>
+ // vmov<c> <Dd>, <Dm>
+ // A8.6.347 VORR (register)
// vorr<c> <Qd>, <Qn>, <Qm>
// vorr<c> <Dd>, <Dn>, <Dm>
- instruction = mnemonic + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // mnemonic is "vmov" by default
+ if (getBit(opcode, 7) == getBit(opcode, 5) &&
+ (opcode & 0xf) == (opcode >> 16 & 0xf)) {
+ instruction = mnemonic + TAB + getVFPQorDdmRegs(opcode);
+ } else {
+ instruction = "vorr" + getVFPQorDdnmRegs(opcode);
+ }
+ // No PC check: not applicable
break;
case arm_vmov_vbitwise: // A8.6.277 VBIC (immediate)
@@ -1754,14 +1776,14 @@
// vorr<c>.<dt> <Qd>, #<imm>
// vorr<c>.<dt> <Dd>, #<imm>
instruction = getVFP_vmov_vbitwise_instruction(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vceq__imm0: // A8.6.281 VCEQ (immediate #0)
// vceq<c>.<dt> <Qd>, <Qm>, #0
// vceq<c>.<dt> <Dd>, <Dm>, #0
instruction = mnemonic + getVFPIorFQorDdmOperands(opcode, 10) + ",#0";
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcge__imm0: // A8.6.283 VCGE (immediate #0)
@@ -1777,7 +1799,7 @@
// vclt<c>.<dt> <Qd>, <Qm>, #0
// vclt<c>.<dt> <Dd>, <Dm>, #0
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 10, 11) + ",#0"; // chose bit 11 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcls: // A8.6.288 VCLS
@@ -1790,14 +1812,14 @@
// vqneg<c>.<dt> <Qd>,<Qm>
// vqneg<c>.<dt> <Dd>,<Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 4, 11); // chose bit 11 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vclz: // A8.6.291 VCLZ
// vclz<c>.<dt> <Qd>, <Qm>
// vclz<c>.<dt> <Dd>, <Dm>
- instruction = mnemonic + getVFPIorFQorDdmOperands(opcode, 11); // chose bit 11 because it is 0
- // No pc check: not applicable
+ instruction = mnemonic + getVFPIorFQorDdmOperands(opcode, 11); // chose bit 11 because it is 0
+ // No PC check: not applicable
break;
case arm_vcmp__reg: // A8.6.292 VCMP, VCMPE
@@ -1805,7 +1827,7 @@
// vcmp{e}<c>.f32 <Sd>, <Sm>
instruction = mnemonic + getE(opcode) + getArmCondition(opcode)
+ getVFPSzF64F32dmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcmp__to_0: // A8.6.292 VCMP, VCMPE
@@ -1813,7 +1835,7 @@
// vcmp{e}<c>.f32 <Sd>, #0.0
instruction = mnemonic + getE(opcode) + getArmCondition(opcode)
+ getVFP_vcmpTo0Operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcnt: // A8.6.293 VCNT
@@ -1823,21 +1845,18 @@
case arm_vmvn: // A8.6.341 VMVN (register)
// vmvn<c> <Qd>, <Qm>
// vmvn<c> <Dd>, <Dm>
- case arm_vmov__reg: // A8.6.327 VMOV (register)
- // vmov<c> <Qd>, <Qm>
- // vmov<c> <Dd>, <Dm>
case arm_vswp: // A8.6.405 VSWP
// vswp<c> <Qd>, <Qm>
// vswp<c> <Dd>, <Dm>
instruction = mnemonic + getVFPQorDdmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__fp_i_vec: // A8.6.294 VCVT (between floating-point and integer, Advanced SIMD)
// vcvt<c>.<Td>.<Tm> <Qd>, <Qm>
// vcvt<c>.<Td>.<Tm> <Dd>, <Dm>
instruction = mnemonic + getVFP_vcvtFpIVecOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__fp_i_reg: // A8.6.295 VCVT, VCVTR (between floating-point and integer, VFP)
@@ -1850,14 +1869,14 @@
if (isBitEnabled(opcode, 18) && !isBitEnabled(opcode, 7))
mnemonic += "r";
instruction = mnemonic + getArmCondition(opcode) + getVFP_vcvtFpIRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__fp_fix_vec: // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
// vcvt<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits>
// vcvt<c>.<Td>.<Tm> <Dd>, <Dm>, #<fbits>
instruction = mnemonic + getVFP_vcvtFpFixVecOperands(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__fp_fix_reg: // A8.6.297 VCVT (between floating-point and fixed-point, VFP)
@@ -1866,21 +1885,21 @@
// vcvt<c>.f64.<Td> <Dd>, <Dd>, #<fbits>
// vcvt<c>.f32.<Td> <Sd>, <Sd>, #<fbits>
instruction = mnemonic + getArmCondition(opcode) + getVFP_vcvtFpFixRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__dp_sp: // A8.6.298 VCVT (between double-precision and single-precision)
// vcvt<c>.f64.f32 <Dd>, <Sm>
// vcvt<c>.f32.f64 <Sd>, <Dm>
instruction = mnemonic + getArmCondition(opcode) + getVFP_vcvtDpSpOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__hp_sp_vec: // A8.6.299 VCVT (between half-precision and single-precision, Advanced SIMD)
// vcvt<c>.f32.f16 <Qd>, <Dm>
// vcvt<c>.f16.f32 <Dd>, <Qm>
instruction = mnemonic + getVFP_vcvtHpSpVecOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vcvt__hp_sp_reg: // A8.6.300 VCVTB, VCVTT (between half-precision and single-precision, VFP)
@@ -1888,14 +1907,14 @@
// vcvt<y><c>.f16.f32 <Sd>, <Sm>
mnemonic += isBitEnabled(opcode, 7) ? "t" : "b";
instruction = mnemonic + getArmCondition(opcode) + getVFP_vcvtHpSpRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vdup__scalar: // A8.6.302 VDUP (scalar)
// vdup<c>.<size> <Qd>, <Dm[x]>
// vdup<c>.<size> <Dd>, <Dm[x]>
instruction = mnemonic + getVFP_vdupScalarOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vdup__reg: // A8.6.303 VDUP (ARM core register)
@@ -1903,7 +1922,7 @@
// vdup<c>.<size> <Dd>, <Rt>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + getVFP_vdupRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vext: // A8.6.305 VEXT
@@ -1911,7 +1930,7 @@
// vext<c>.8 <Dd>, <Dn>, <Dm>, #<imm>
instruction = mnemonic + ".8" + getVFPQorDdnmRegs(opcode)
+ ",#" + (opcode >> 8 & 0xf);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vld__multi: // A8.6.307 VLD1 (multiple single elements)
@@ -1939,7 +1958,7 @@
// vst4<c>.<size> <list>, [<Rn>{@<align>}]{!}
// vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
instruction = mnemonic + getVFP_vXX_multi(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vld__xlane: // A8.6.308 VLD1 (single element to one lane)
@@ -1979,7 +1998,7 @@
// vst4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
// vst4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
instruction = mnemonic + getVFP_vXX_Xlane(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vldm__64: // A8.6.319 VLDM
@@ -1991,8 +2010,8 @@
case arm_vstm__32: // A8.6.399 VSTM
// vstm{mode}<c> <Rn>{!}, <list> <list> is consecutive 32-bit registers
instruction = mnemonic + getVFPIncDec(opcode) + getArmCondition(opcode)
- + getVFP_vXXm(opcode);
- // No pc check: not applicable
+ + getVFP_vXXm(opcode);
+ // No PC check: not applicable
break;
case arm_vldr__64: // A8.6.320 VLDR
@@ -2008,7 +2027,7 @@
case arm_vstr__32: // A8.6.400 VSTR
// vstr<c> <Sd>, [<Rn>{, #+/-<imm>}]
instruction = mnemonic + getArmCondition(opcode) + getVFP_vXXr(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmax_vmin__int: // A8.6.321 VMAX, VMIN (integer)
@@ -2018,10 +2037,10 @@
// vmin<c>.<dt> <Dd>, <Dn>, <Dm>
case arm_vpmax_vpmin__int: // A8.6.352 VPMAX, VPMIN (integer)
// vp<op><c>.<dt> <Dd>, <Dn>, <Dm>
- // (this works despite no Q version because Q==1 is UNDEFEIND)
+ // (this works despite no Q version because Q==1 is UNDEFINED)
instruction = mnemonic + (isBitEnabled(opcode, 4) ? "min" : "max")
- + getVFPSorUDataType(opcode, 24) + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ + getVFPSorUDataType(opcode, 24) + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
break;
case arm_vmax_vmin__fp: // A8.6.322 VMAX, VMIN (floating-point)
@@ -2032,8 +2051,8 @@
case arm_vpmax_vpmin__fp: // A8.6.353 VPMAX, VPMIN (floating-point)
// vp<op><c>.f32 <Dd>, <Dn>, <Dm>
instruction = mnemonic + (isBitEnabled(opcode, 21) ? "min.f32" : "max.f32")
- + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
break;
case arm_vml__int: // A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
@@ -2041,7 +2060,7 @@
// v<op><c>.<dt> <Dd>, <Dn>, <Dm>
mnemonic += isBitEnabled(opcode, 24) ? 's' : 'a';
instruction = mnemonic + getVFPIDataType(opcode, 20) + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vml__int_long: // A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
@@ -2049,7 +2068,7 @@
mnemonic += isBitEnabled(opcode, 9) ? "sl" : "al";
instruction = mnemonic + getVFPSorUDataType(opcode, 24)
+ TAB + getVFPQdDnDmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vml__f32: // A8.6.324 VMLA, VMLS (floating-point)
@@ -2057,7 +2076,7 @@
// v<op><c>.f32 <Dd>, <Dn>, <Dm>
mnemonic += isBitEnabled(opcode, 21) ? "s.f32" : "a.f32";
instruction = mnemonic + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vml__fp: // A8.6.324 VMLA, VMLS (floating-point)
@@ -2065,7 +2084,7 @@
// v<op><c>.f32 <Sd>, <Sn>, <Sm>
mnemonic += isBitEnabled(opcode, 6) ? 's' : 'a' + getArmCondition(opcode);
instruction = mnemonic + getVFPSzF64F32dnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vml__scalar: // A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
@@ -2076,35 +2095,36 @@
case arm_vmul__scalar: // A8.6.339 VMUL, VMULL (by scalar)
// vmul<c>.<dt> <Qd>, <Qn>, <Dm[x]>
// vmul<c>.<dt> <Dd>, <Dn>, <Dm[x]>
+ // vmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
case arm_vqdmull__scalar: // A8.6.360 VQDMULL
// vqdmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
// bit 9 == 1, so getVFP_vmXXScalar() works
instruction = mnemonic + getVFP_vmXXScalar(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmov__imm: // A8.6.326 VMOV (immediate)
// vmov<c>.f64 <Dd>, #<imm>
// vmov<c>.f32 <Sd>, #<imm>
- mnemonic += getArmCondition(opcode) + getVFPSzF64F32Type(getBit(opcode, 8));
+ mnemonic += getArmCondition(opcode) + getVFPSzF64F32Type(getBit(opcode, 8));
imm = (opcode >> 16 & 0xf) << 4 | opcode & 0xf;
instruction = mnemonic + TAB + getVFPDorSReg(opcode, getBit(opcode, 8), 12, 22)
- + ",#" + getHexValue(imm);
- // No pc check: not applicable
+ + ",#" + getHexValue(imm);
+ // No PC check: not applicable
break;
case arm_vmov_5: // A8.6.328 VMOV (ARM core register to scalar)
// vmov<c>.<size> <Dd[x]>, <Rt>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + getVFP_vmovArmCoreRegToScalar(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmov_6: // A8.6.329 VMOV (scalar to ARM core register)
// vmov<c>.<dt> <Rt>, <Dn[x]>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + getVFP_vmovScalarToArmCoreReg(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmov_7: // A8.6.330 VMOV (between ARM core register and
@@ -2113,7 +2133,7 @@
// vmov<c> <Rt>, <Sn>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + getVFP_vmovBetweenArmCoreAndSinglePrecReg(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmov_8: // A8.6.331 VMOV (between two ARM core registers and
@@ -2122,7 +2142,7 @@
// vmov<c> <Rt>, <Rt2>, <Sm>, <Sm1>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + getVFP_vmovBetween2ArmCoreAndSinglePrecRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmov_9: // A8.6.332 VMOV (between two ARM core registers and
@@ -2131,7 +2151,7 @@
// vmov<c> <Rt>, <Rt2>, <Dm>
mnemonic += getArmCondition(opcode);
instruction = mnemonic + getVFP_vmovBetween2ArmCoreAnd1DoublewordExtensionRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmovl: // A8.6.333 VMOVL
@@ -2139,7 +2159,7 @@
case arm_vshll__various: // A8.6.384 VSHLL
// vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (0 < <imm> < <size>)
instruction = mnemonic + getVFP_vmovl_vshll_operands(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmovn: // A8.6.334 VMOVN
@@ -2154,7 +2174,7 @@
instruction = mnemonic + tempStr + "\t"
+ getVFPQorDReg(opcode, 0, 12, 22) + "," +getVFPQorDReg(opcode, 1, 0, 5);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmrs: // A8.6.335 VMRS
@@ -2163,7 +2183,7 @@
// vmrs<c> <Rt>,<spec_reg>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getR_12(opcode) + "," + getVFPSpecialReg(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmsr: // A8.6.336 VMSR
@@ -2172,7 +2192,7 @@
// vmsr<c> <spec_reg>,<Rt>
instruction = mnemonic + getArmCondition(opcode) + "\t"
+ getVFPSpecialReg(opcode) + "," + getR_12(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmul_1: // A8.6.337 VMUL, VMULL (integer and polynomial)
@@ -2181,14 +2201,14 @@
// 1 1 1 1 0 0 1 op_24_24 0 D_22_22 size_21_20 Vn_19_16 Vd_15_12 1 0 0 1 N_7_7 Q_6_6 M_5_5 1 Vm_3_0
mnemonic += (isBitEnabled(opcode, 24) ? ".p" : ".i") + getVFPDataTypeSize(opcode, 20);
instruction = mnemonic + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vmull: // A8.6.337 VMUL, VMULL (integer and polynomial)
// vmull<c>.<dt> <Qd>, <Dn>, <Dm>
mnemonic += isBitEnabled(opcode, 9) ? getVFPPDataType(opcode, 20) : getVFPSorUDataType(opcode, 24);
instruction = mnemonic + TAB + getVFPQdDnDmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vpadal: // A8.6.348 VPADAL
@@ -2198,7 +2218,7 @@
// vpaddl<c>.<dt> <Qd>, <Qm>
// vpaddl<c>.<dt> <Dd>, <Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 4, 7); // chose bit 4 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vpop: // A8.6.354 VPOP
@@ -2208,14 +2228,14 @@
// vpush<c> <list> (<list> is consecutive 64-bit registers)
// vpush<c> <list> (<list> is consecutive 32-bit registers)
instruction = mnemonic + getArmCondition(opcode) + getVFP_vpop_vpush_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vqdml__scalar: // A8.6.358 VQDMLAL, VQDMLSL
// vqd<op><c>.<dt> <Qd>,<Dn>,<Dm[x]>
mnemonic += isBitEnabled(opcode, 10) ? "sl.s" : "al.s";
instruction = mnemonic + getVFPScalarOperands(opcode, 1, 0);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vqdmulh__vec: // A8.6.359 VQDMULH
@@ -2226,7 +2246,7 @@
// vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
mnemonic += isBitEnabled(opcode, 20) ? ".s16" : ".s32";
instruction = mnemonic + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vqdmulh__scalar: // A8.6.359 VQDMULH
@@ -2237,28 +2257,13 @@
// vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
q = getBit(opcode, 24);
instruction = mnemonic + ".s" + getVFPScalarOperands(opcode, q, q);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vqmov: // A8.6.361 VQMOVN, VQMOVUN
// vqmov{u}n<c>.<type><size> <Dd>,<Qm>
instruction = mnemonic + getVFP_vqmov_instruction(opcode);
- // No pc check: not applicable
- break;
-
- case arm_vqrshr: // A8.6.365 VQRSHRN, VQRSHRUN
- // vqrshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- case arm_vqshr:
- // vqshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- instruction = mnemonic + getVFP_vqXshr_instruction(opcode, 24);
- // No pc check: not applicable
- break;
-
- case arm_vqshl__imm: // A8.6.367 VQSHL, VQSHLU (immediate)
- // vqshl{u}<c>.<type><size> <Qd>,<Qm>,#<imm>
- // vqshl{u}<c>.<type><size> <Dd>,<Dm>,#<imm>
- instruction = mnemonic + getVFP_vqshl_instruction(opcode, 24);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vqrshl: // A8.6.364 VQRSHL
@@ -2271,10 +2276,25 @@
// vrshl<c>.<type><size> <Qd>,<Qm>,<Qn>
// vrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
case arm_vshl__reg: // A8.6.383 VSHL (register)
- // vshl<c>.<type><size> <Qd>,<Qm>,<Qn>
- // vshl<c>.<type><size> <Dd>,<Dm>,<Dn>
+ // vshl<c>.<type><size> <Qd>,<Qm>,<Qn>
+ // vshl<c>.<type><size> <Dd>,<Dm>,<Dn>
instruction = mnemonic + getVFPSorUDataType(opcode, 24) + getVFPQorDdmnRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
+ break;
+
+ case arm_vqrshr: // A8.6.365 VQRSHRN, VQRSHRUN
+ // vqrshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
+ case arm_vqshr: // A8.6.368 VQSHRN, VQSHRUN
+ // vqshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
+ instruction = mnemonic + getVFP_vqXshr_instruction(opcode, 24);
+ // No PC check: not applicable
+ break;
+
+ case arm_vqshl__imm: // A8.6.367 VQSHL, VQSHLU (immediate)
+ // vqshl{u}<c>.<type><size> <Qd>,<Qm>,#<imm>
+ // vqshl{u}<c>.<type><size> <Dd>,<Dm>,#<imm>
+ instruction = mnemonic + getVFP_vqshl_instruction(opcode, 24);
+ // No PC check: not applicable
break;
case arm_vrecpe: // A8.6.371 VRECPE
@@ -2284,14 +2304,14 @@
// vrsqrte<c>.<dt> <Qd>, <Qm>
// vrsqrte<c>.<dt> <Dd>, <Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 8, 10);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vrev: // A8.6.373 VREV16, VREV32, VREV64
// vrev<n><c>.<size> <Qd>,<Qm>
// vrev<n><c>.<size> <Dd>,<Dm>
instruction = mnemonic + getVFP_vrev_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vrshr: // A8.6.376 VRSHR
@@ -2312,7 +2332,7 @@
// vsri<c>.<size> <Qd>, <Qm>, #<imm>
// vsri<c>.<size> <Dd>, <Dm>, #<imm>
instruction = mnemonic + getVFP_vXrX_instruction(opcode, true);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vrshrn: // A8.6.377 VRSHRN
@@ -2320,7 +2340,7 @@
case arm_vshrn: // A8.6.386 VSHRN
// vshrn<c>.i<size> <Dd>, <Qm>, #<imm>
instruction = mnemonic + getVFP_vXshrn_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vshl__imm: // A8.6.382 VSHL (immediate)
@@ -2330,7 +2350,7 @@
// vsli<c>.<size> <Qd>, <Qm>, #<imm>
// vsli<c>.<size> <Dd>, <Dm>, #<imm>
instruction = mnemonic + getVFP_vXrX_instruction(opcode, false);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vshll__max: // A8.6.384 VSHLL
@@ -2338,13 +2358,13 @@
mnemonic += getVFPIDataType3(opcode, 18);
instruction = mnemonic + TAB + getVFPQorDReg(opcode, 1, 12, 22)
+ ',' + getVFPQorDReg(opcode, 0, 0, 5) + ",#" + (8 << (opcode >> 18 & 3));
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vtb: // A8.6.406 VTBL, VTBX
// v<op><c>.8 <Dd>, <list>, <Dm>
instruction = mnemonic + getVFP_vtb_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vtrn: // A8.6.407 VTRN
@@ -2357,14 +2377,14 @@
// vzip<c>.<size> <Qd>, <Qm>
// vzip<c>.<size> <Dd>, <Dm>
instruction = mnemonic + getVFPSzQorDdmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case arm_vtst: // A8.6.408 VTST
// vtst<c>.<size> <Qd>, <Qn>, <Qm>
// vtst<c>.<size> <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFPSzQorDdnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
default:
@@ -2378,7 +2398,7 @@
/**
* Disassemble a 16-bit Thumb instruction
* Reference manual citations (e.g., "A8.6.2") refer to sections in the ARM Architecture
- * Reference Manual ARMv7-A and ARMv7-R Edition with errata markup
+ * Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
* @return disassembled instruction
*/
private String parseThumbOpcode() throws BufferUnderflowException {
@@ -2425,29 +2445,34 @@
// adcs <Rdn>,<Rm> Outside IT block.
// adc<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rdn cannot be PC
+ // No PC check: Rdn cannot be PC
break;
case thumb_add__imm: // A8.6.4 ADD (immediate, Thumb)
// adds <Rdn>,#<imm8> Outside IT block.
// add<c> <Rdn>,#<imm8> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 8) + "," + getThumbImmediate8(opcode, 1);
- // No pc check: Rdn cannot be PC
+ // No PC check: Rdn cannot be PC
break;
case thumb_add__imm_to_sp: // A8.6.8 ADD (SP plus immediate)
// add<c> sp,sp,#<imm>
instruction = mnemonic + "\tsp,sp," + getThumbImmediate7(opcode, 4);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_add__reg: // A8.6.6 ADD (register)
// add<c> <Rdn>,<Rm> If <Rdn> is PC, must be outside or last in IT block.
+ // A8.6.9 ADD (SP plus register)
+ // add<c> <Rdm>, sp, <Rdm>
+ // A8.6.9 ADD (SP plus register)
+ // add<c> sp,<Rm>
regOp = getThumbRegHigh(opcode, 0, 7);
instruction = mnemonic + "\t" + regOp + "," + getThumbRegHigh(opcode, 3, 6);
if (regOp.equals("pc"))
setDefaultPCJumpProperties(true);
+ // Note: having PC (register 15) as the destination register is deprecated
break;
case thumb_add__reg_imm: // A8.6.4 ADD (immediate, Thumb)
@@ -2455,7 +2480,7 @@
// add<c> <Rd>,<Rn>,#<imm3> Inside IT block.
instruction = mnemonic + "s\t"
+ getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + "," + getThumbImmediate3(opcode);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_add__reg_reg: // A8.6.6 ADD (register)
@@ -2463,14 +2488,14 @@
// add<c> <Rd>,<Rn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t"
+ getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + "," + getThumbReg(opcode, 6);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_add__sp_imm: // A8.6.8 ADD (SP plus immediate)
// add<c> <Rd>,sp,#<imm>
instruction = mnemonic + "\t"
+ getThumbReg(opcode, 8) + ",sp," + getThumbImmediate8(opcode, 4);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_adr: // A8.6.10 ADR
@@ -2478,14 +2503,14 @@
// add <Rd>,pc,imm8 Alternative form
instruction = mnemonic + "\t"
+ getThumbReg(opcode, 8) + ",pc," + getThumbImmediate8(opcode, 4);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_and: // A8.6.12 AND (register)
// ands <Rdn>,<Rm> Outside IT block.
// and<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rdn cannot be PC
+ // No PC check: Rdn cannot be PC
break;
case thumb_asr__imm: // A8.6.14 ASR (immediate)
@@ -2493,14 +2518,14 @@
// asr<c> <Rd>,<Rm>,#<imm> Inside IT block.
instruction = mnemonic + "s\t"
+ getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + "," + getThumbImmediate5(opcode, 1);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_asr__reg: // A8.6.15 ASR (register)
// asrs <Rdn>,<Rm> Outside IT block.
// asr<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rdn cannot be PC
+ // No PC check: Rdn cannot be PC
break;
case thumb_b_1: // A8.6.16 B
@@ -2526,7 +2551,7 @@
// bics <Rdn>,<Rm> Outside IT block.
// bic<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rdn cannot be PC
+ // No PC check: Rdn cannot be PC
break;
case thumb_bkpt: // A8.6.22 BKPT
@@ -2534,7 +2559,7 @@
case thumb_svc: // A8.6.218 SVC (previously SWI)
// svc<c> #<imm8>
instruction = mnemonic + "\t" + getThumbImmediate8(opcode, 1);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_blx: // A8.6.24 BLX (register)
@@ -2562,43 +2587,44 @@
jumpToAddr = address.add(offset);
instruction = mnemonic + addN + "z\t"
+ getThumbReg(opcode, 0) + "," + jumpToAddr.toHexAddressString();
+ // No PC check: not applicable
break;
case thumb_cmn: // A8.6.33 CMN (register)
// cmn<c> <Rn>,<Rm>
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_cmp__imm: // A8.6.35 CMP (immediate)
// cmp<c> <Rn>,#<imm8>
instruction = mnemonic + "\t" + getThumbReg(opcode, 8) + "," + getThumbImmediate8(opcode, 1);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_cmp__reg: // A8.6.36 CMP (register)
// cmp<c> <Rn>,<Rm> <Rn> and <Rm> both from R0-R7
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_cmp__reg_hi: // A8.6.36 CMP (register)
// cmp<c> <Rn>,<Rm> <Rn> and <Rm> not both from R0-R7
instruction = mnemonic + "\t" + getThumbRegHigh(opcode, 0, 7) + "," + getThumbRegHigh(opcode, 3, 6);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_cps: // B6.1.1 CPS
// cps<effect> <iflags> Not permitted in IT block.
instruction = mnemonic + getThumbEffect(opcode) + "\t" + getThumbIFlags(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_eor: // A8.6.45 EOR (register)
// eors <Rdn>,<Rm> Outside IT block.
// eor<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_it: // A8.6.50 IT
@@ -2640,7 +2666,7 @@
else if ((mask3 != cond0) && (mask2 != cond0) && (mask1 != cond0) && (mask0 == 1))
xyz = "eee";
instruction = mnemonic + xyz + "\t" + getCondition(cond);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_ldm: // A8.6.53 LDM / LDMIA / LDMFD
@@ -2650,7 +2676,7 @@
regList = getThumbRegList(opcode, null);
String addExclaim = regList.contains(regOp)? "" : "!";
instruction = mnemonic + "\t" + regOp + addExclaim + "," + regList;
- // No pc check: Rn cannot be PC and regList cannot contain PC
+ // No PC check: Rn cannot be PC and regList cannot contain PC
break;
case thumb_ldr__imm: // A8.6.57 LDR (immediate, Thumb)
@@ -2659,7 +2685,7 @@
if (((opcode >> 6) & 0x1f) != 0)
instruction += "," + getThumbImmediate5(opcode, 4);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_ldr__imm_sp: // A8.6.57 LDR (immediate, Thumb)
@@ -2668,7 +2694,7 @@
if ((opcode & 0xff) != 0)
instruction += "," + getThumbImmediate8(opcode, 4);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_ldr__lit: // A8.6.59 LDR (literal)
@@ -2683,14 +2709,14 @@
instruction = mnemonic + "\t" + getThumbReg(opcode, 8) + ",[pc,#" + getHexValue(imm) + "] ; 0x" + addr;
}
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_ldr__reg: // A8.6.60 LDR (register)
// ldr<c> <Rt>,[<Rn>,<Rm>]
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + ",[" + getThumbReg(opcode, 3) + ","
+ getThumbReg(opcode, 6) + "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_ldrb__imm: // A8.6.61 LDRB (immediate, Thumb)
@@ -2699,7 +2725,7 @@
if (((opcode >> 6) & 0x1f) != 0)
instruction += "," + getThumbImmediate5(opcode, 1);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_ldrb__reg: // A8.6.64 LDRB (register)
@@ -2712,7 +2738,7 @@
// ldrsh<c> <Rt>,[<Rn>,<Rm>]
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + ",[" + getThumbReg(opcode, 3) + ","
+ getThumbReg(opcode, 6) + "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_ldrh__imm: // A8.6.73 LDRH (immediate, Thumb)
@@ -2721,7 +2747,7 @@
if (((opcode >> 6) & 0x1f) != 0)
instruction += "," + getThumbImmediate5(opcode, 2);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_lsl__imm: // A8.6.88 LSL (immediate)
@@ -2732,7 +2758,7 @@
// lsr<c> <Rd>,<Rm>,#<imm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3)
+ ",#" + ((opcode >> 6) & 0x1f);
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_lsl__reg: // A8.6.89 LSL (register)
@@ -2742,14 +2768,14 @@
// lsrs <Rdn>,<Rm> Outside IT block.
// lsr<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_mov__imm: // A8.6.96 MOV (immediate)
// movs <Rd>,#<imm8> Outside IT block.
// mov<c> <Rd>,#<imm8> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 8) + "," + getThumbImmediate8(opcode, 1);
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_mov__reg: // A8.6.97 MOV (register)
@@ -2767,7 +2793,7 @@
case thumb_movs: // A8.6.97 MOV (register)
// movs <Rd>,<Rm> Not permitted in IT block
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_mul: // A8.6.105 MUL
@@ -2775,7 +2801,7 @@
// mul<c> <Rdm>,<Rn>,<Rdm> Inside IT block.
instruction = mnemonic + "s\t"
+ getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + "," + getThumbReg(opcode, 0);
- // No pc check: Rdm cannot be PC
+ // No PC check: Rdm cannot be PC
break;
case thumb_mvn: // A8.6.107 MVN (register)
@@ -2785,7 +2811,7 @@
// orrs <Rdn>,<Rm> Outside IT block.
// orr<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd or Rdn cannot be PC
+ // No PC check: Rd or Rdn cannot be PC
break;
case thumb_nop: // A8.6.110 NOP
@@ -2799,7 +2825,7 @@
case thumb_yield: // A8.6.413 YIELD
// yield<c>
instruction = mnemonic;
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_pop: // A8.6.122 POP
@@ -2825,7 +2851,7 @@
regList = getThumbRegList(opcode, null);
}
instruction = mnemonic + "\t" + regList;
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_rev: // A8.6.135 REV
@@ -2835,7 +2861,7 @@
case thumb_revsh: // A8.6.137 REVSH
// revsh<c> <Rd>,<Rm>
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_ror: // A8.6.140 ROR (register)
@@ -2845,27 +2871,27 @@
// sbcs <Rdn>,<Rm> Outside IT block.
// sbc<c> <Rdn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd or Rdn cannot be PC
+ // No PC check: Rd or Rdn cannot be PC
break;
case thumb_rsb: // A8.6.142 RSB (immediate)
// rsbs <Rd>,<Rn>,#0 Outside IT block.
// rsb<c> <Rd>,<Rn>,#0 Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + ",#0";
- // No pc check: Rd or Rdn cannot be PC
+ // No PC check: Rd or Rdn cannot be PC
break;
case thumb_setend: // A8.6.157 SETEND
// setend <endian_specifier> Not permitted in IT block
String endian = (((opcode >> 3) & 1) == 1) ? "be" : "le";
instruction = mnemonic + "\t" + endian;
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_stm: // A8.6.189 STM / STMIA / STMEA
// stm<c> <Rn>!,<registers>
instruction = mnemonic + "\t" + getThumbReg(opcode, 8) + "!," + getThumbRegList(opcode, null);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_str__imm: // A8.6.193 STR (immediate, Thumb)
@@ -2874,20 +2900,20 @@
if (((opcode >> 6) & 0x1f) != 0)
instruction += "," + getThumbImmediate5(opcode, 4);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_str__imm_sp: // A8.6.193 STR (immediate, Thumb)
// str<c> <Rt>,[sp,#<imm>]
instruction = mnemonic + "\t" + getThumbReg(opcode, 8) + ",[sp," + getThumbImmediate8(opcode, 4) + "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_str__reg: // A8.6.195 STR (register)
// str<c> <Rt>,[<Rn>,<Rm>]
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + ",[" + getThumbReg(opcode, 3) + ","
+ getThumbReg(opcode, 6) + "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_strb__imm: // A8.6.196 STRB (immediate, Thumb)
@@ -2896,14 +2922,14 @@
if (((opcode >> 6) & 0x1f) != 0)
instruction += "," + getThumbImmediate5(opcode, 1);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_strb__reg: // A8.6.198 STRB (register)
// strb<c> <Rt>,[<Rn>,<Rm>]
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + ",[" + getThumbReg(opcode, 3) + ","
+ getThumbReg(opcode, 6) + "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_strh__imm: // A8.6.206 STRH (immediate, Thumb)
@@ -2912,27 +2938,27 @@
if (((opcode >> 6) & 0x1f) != 0)
instruction += "," + getThumbImmediate5(opcode, 2);
instruction += "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_strh__reg: // A8.6.208 STRH (register)
// strh<c> <Rt>,[<Rn>,<Rm>]
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + ",[" + getThumbReg(opcode, 3) + ","
+ getThumbReg(opcode, 6) + "]";
- // No pc check: Rt cannot be PC
+ // No PC check: Rt cannot be PC
break;
case thumb_sub__imm: // A8.6.211 SUB (immediate, Thumb)
// subs <Rdn>,#<imm8> Outside IT block.
// sub<c> <Rdn>,#<imm8> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 8) + "," + getThumbImmediate8(opcode, 1);
- // No pc check: Rdn cannot be PC
+ // No PC check: Rdn cannot be PC
break;
case thumb_sub__imm_from_sp: // A8.6.215 SUB (SP minus immediate)
// sub<c> sp,sp,#<imm>
instruction = mnemonic + "\tsp,sp," + getThumbImmediate7(opcode, 4);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
case thumb_sub__reg_imm: // A8.6.211 SUB (immediate, Thumb)
@@ -2940,7 +2966,7 @@
// sub<c> <Rd>,<Rn>,#<imm3> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + ","
+ getThumbImmediate3(opcode);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_sub__reg_reg: // A8.6.213 SUB (register)
@@ -2948,7 +2974,7 @@
// sub<c> <Rd>,<Rn>,<Rm> Inside IT block.
instruction = mnemonic + "s\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3) + ","
+ getThumbReg(opcode, 6);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_sxtb: // A8.6.223 SXTB
@@ -2962,12 +2988,12 @@
case thumb_uxth: // A8.6.265 UXTH
// uxth<c> <Rd>,<Rm>
instruction = mnemonic + "\t" + getThumbReg(opcode, 0) + "," + getThumbReg(opcode, 3);
- // No pc check: Rd cannot be PC
+ // No PC check: Rd cannot be PC
break;
case thumb_undefined:
instruction = mnemonic;
- // No pc check: not applicable
+ // No PC check: not applicable
break;
default:
@@ -2981,8 +3007,8 @@
/**
* Disassemble a 32-bit Thumb instruction
* Reference manual citations (e.g., "A8.6.4") refer to sections in the ARM Architecture
- * Reference Manual ARMv7-A and ARMv7-R Edition with errata markup
- * @param opcode instruction to parse
+ * Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
+ * @param opcode instruction to parse
* @return disassembled instruction
*/
private String parseThumb2Opcode(int opcode) throws BufferUnderflowException {
@@ -3010,102 +3036,134 @@
boolean checkPC = false;
switch (opcodeIndex) {
- case thumb2_add__imm: // A8.6.4 ADD (immediate) // add{s}<c>.w <Rd>,<Rn>,#<const>
- case thumb2_rsb__imm: // A8.6.142 RSB (immediate) // rsb{s}<c>.w <Rd>,<Rn>,#<const>
- case thumb2_sub__imm: // A8.6.211 SUB (immediate) // sub{s}<c>.w <Rd>,<Rn>,#<const>
+ case thumb2_add__imm: // A8.6.4 ADD (immediate)
+ // add{s}<c>.w <Rd>,<Rn>,#<const>
+ // A8.6.8 ADD (SP plus immediate)
+ // addw <Rd>,sp,#<imm12>
+ case thumb2_rsb__imm: // A8.6.142 RSB (immediate)
+ // rsb{s}<c>.w <Rd>,<Rn>,#<const>
+ case thumb2_sub__imm: // A8.6.211 SUB (immediate)
+ // sub{s}<c>.w <Rd>,<Rn>,#<const>
instruction = ".w";
// no break!
- case thumb2_adc__imm: // A8.6.1 ADC (immediate) // adc{s}<c> <Rd>,<Rn>,#<const>
- case thumb2_and__imm: // A8.6.11 AND (immediate) // and{s}<c> <Rd>,<Rn>,#<const>
- case thumb2_bic__imm: // A8.6.19 BIC (immediate) // bic{s}<c> <Rd>,<Rn>,#<const>
- case thumb2_eor__imm: // A8.6.44 EOR (immediate) // eor{s}<c> <Rd>,<Rn>,#<const>
- case thumb2_orn__imm: // A8.6.111 ORN (immediate) // orn{s}<c> <Rd>,<Rn>,#<const>
- case thumb2_orr__imm: // A8.6.113 ORR (immediate) // orr{s}<c> <Rd>,<Rn>,#<const>
- case thumb2_sbc__imm: // A8.6.151 SBC (immediate) // sbc{s}<c> <Rd>,<Rn>,#<const>
- // . . . . . i_1_10_10 . . . . . S_1_4_4 Rn_1_3_0 . imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
+ case thumb2_adc__imm: // A8.6.1 ADC (immediate)
+ // adc{s}<c> <Rd>,<Rn>,#<const>
+ case thumb2_and__imm: // A8.6.11 AND (immediate)
+ // and{s}<c> <Rd>,<Rn>,#<const>
+ case thumb2_bic__imm: // A8.6.19 BIC (immediate)
+ // bic{s}<c> <Rd>,<Rn>,#<const>
+ case thumb2_eor__imm: // A8.6.44 EOR (immediate)
+ // eor{s}<c> <Rd>,<Rn>,#<const>
+ case thumb2_orn__imm: // A8.6.111 ORN (immediate)
+ // orn{s}<c> <Rd>,<Rn>,#<const>
+ case thumb2_orr__imm: // A8.6.113 ORR (immediate)
+ // orr{s}<c> <Rd>,<Rn>,#<const>
+ case thumb2_sbc__imm: // A8.6.151 SBC (immediate)
+ // sbc{s}<c> <Rd>,<Rn>,#<const>
mnemonic += getS(opcode) + instruction;
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode)
- + ",#" + getThumb2ExpandImm12(opcode);
- // No pc check: if Rd is PC, the instruction translates to another enumeral or is unpredictable
+ + ",#" + getThumb2ExpandImm12(opcode);
+ // No PC check: if Rd is PC, the instruction translates to another enumeral or is UNPREDICTABLE
break;
- case thumb2_addw: // A8.6.4 ADD (immediate, Thumb) // addw<c> <Rd>,<Rn>,#<imm12>
- case thumb2_subw: // A8.6.211 SUB (immediate, Thumb) // subw<c> <Rd>,<Rn>,#<imm12>
- // . . . . . i_1_10_10 . . . . . . Rn_1_3_0 . imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
+ case thumb2_addw: // A8.6.4 ADD (immediate, Thumb)
+ // addw<c> <Rd>,<Rn>,#<imm12>
+ case thumb2_subw: // A8.6.211 SUB (immediate, Thumb)
+ // subw<c> <Rd>,<Rn>,#<imm12>
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode)
- + ",#" + getHexValue(getThumb2RawImm12(opcode));
- // No pc check: if Rd is PC, the instruction translates to another enumeral or is unpredictable
+ + ",#" + getHexValue(getThumb2RawImm12(opcode));
+ // No PC check: if Rd is PC, the instruction translates to another enumeral or is UNPREDICTABLE
break;
- case thumb2_adc__reg: // A8.6.2 ADC (register) // adc{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_add__reg: // A8.6.6 ADD (register) // add{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_and__reg: // A8.6.12 AND (register) // and{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_bic__reg: // A8.6.20 BIC (register) // bic{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_eor__reg: // A8.6.45 EOR (register) // eor{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_orr__reg: // A8.6.114 ORR (register) // orr{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_sbc__reg: // A8.6.152 SBC (register) // sbc{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_sub__reg: // A8.6.213 SUB (register) // sub{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_adc__reg: // A8.6.2 ADC (register)
+ // adc{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_add__reg: // A8.6.6 ADD (register)
+ // add{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ // A8.6.9 ADD (SP plus register)
+ // add{s}<c>.w <Rd>,sp,<Rm>{,<shift>}
+ case thumb2_and__reg: // A8.6.12 AND (register)
+ // and{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_bic__reg: // A8.6.20 BIC (register)
+ // bic{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_eor__reg: // A8.6.45 EOR (register)
+ // eor{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_orr__reg: // A8.6.114 ORR (register)
+ // orr{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_sbc__reg: // A8.6.152 SBC (register)
+ // sbc{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_sub__reg: // A8.6.213 SUB (register)
+ // sub{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
instruction = ".w";
// no break!
- case thumb2_orn__reg: // A8.6.112 ORN (register) // orn{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- case thumb2_rsb__reg: // A8.6.143 RSB (register) // rsb{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // . . . . . . . . . . . S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
+ case thumb2_orn__reg: // A8.6.112 ORN (register)
+ // orn{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
+ case thumb2_rsb__reg: // A8.6.143 RSB (register)
+ // rsb{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
mnemonic += getS(opcode) + instruction;
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode)
- + ',' + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
- // No pc check: if Rd is PC, the instruction translates to another enumeral or is unpredictable
+ + ',' + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
+ // No PC check: if Rd is PC, the instruction translates to another enumeral or is UNPREDICTABLE
break;
- case thumb2_mov__imm: // A8.6.96 MOV (immediate) // mov{s}<c>.w <Rd>,#<const>
+ case thumb2_mov__imm: // A8.6.96 MOV (immediate)
+ // mov{s}<c>.w <Rd>,#<const>
instruction = ".w";
// no break!
- case thumb2_mvn__imm: // A8.6.106 MVN (immediate) // mvn{s}<c> <Rd>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 1 1 S_1_4_4 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
+ case thumb2_mvn__imm: // A8.6.106 MVN (immediate)
+ // mvn{s}<c> <Rd>,#<const>
mnemonic += getS(opcode) + instruction;
instruction = mnemonic + TAB + getR_8(opcode)+ ",#" + getThumb2ExpandImm12(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
- case thumb2_mvn__reg: // A8.6.107 MVN (register) // mvn{s}<c>.w <Rd>,<Rm>{,<shift>}
- // . . . . . . . . . . . S_1_4_4 . . . . (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
+ case thumb2_mvn__reg: // A8.6.107 MVN (register)
+ // mvn{s}<c>.w <Rd>,<Rm>{,<shift>}
instruction = mnemonic + getS(opcode) + ".w\t" + getR_8(opcode) + ','
- + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
- case thumb2_adr__sub: // A8.6.10 ADR // adr<c>.w <Rd>,<label>
- // add<c> <Rd>,pc,#imm12 Alternate form
- case thumb2_adr__add: // A8.6.10 ADR // adr<c>.w <Rd>,<label>
- // sub<c> <Rd>,pc,#imm12 Alternate form
+ case thumb2_adr__sub: // A8.6.10 ADR
+ // adr<c>.w <Rd>,<label>
+ // add<c> <Rd>,pc,#imm12 Alternate form
+ case thumb2_adr__add: // A8.6.10 ADR
+ // adr<c>.w <Rd>,<label>
+ // sub<c> <Rd>,pc,#imm12 Alternate form
instruction = mnemonic + TAB + getR_8(opcode) + ",pc,#"
- + getHexValue(getThumb2RawImm12(opcode));
- // No pc check: if Rd is PC, the instruction is unpredictable
+ + getHexValue(getThumb2RawImm12(opcode));
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
- case thumb2_asr__imm: // A8.6.14 ASR (immediate) // asr{s}<c>.w <Rd>,<Rm>,#<imm>
- case thumb2_lsl__imm: // A8.6.88 LSL (immediate) // lsl{s}<c>.w <Rd>,<Rm>,#<imm>
- case thumb2_lsr__imm: // A8.6.90 LSR (immediate) // lsr{s}<c>.w <Rd>,<Rm>,#<imm>
+ case thumb2_asr__imm: // A8.6.14 ASR (immediate)
+ // asr{s}<c>.w <Rd>,<Rm>,#<imm>
+ case thumb2_lsl__imm: // A8.6.88 LSL (immediate)
+ // lsl{s}<c>.w <Rd>,<Rm>,#<imm>
+ case thumb2_lsr__imm: // A8.6.90 LSR (immediate)
+ // lsr{s}<c>.w <Rd>,<Rm>,#<imm>
instruction = ".w";
- case thumb2_ror__imm: // A8.6.139 ROR (immediate) // ror{s}<c> <Rd>,<Rm>,#<imm>
- // . . . . . . . . . . . S_1_4_4 . . . . (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 . . Rm_0_3_0
+ case thumb2_ror__imm: // A8.6.139 ROR (immediate)
+ // ror{s}<c> <Rd>,<Rm>,#<imm>
mnemonic += getS(opcode) + instruction;
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_0(opcode)
- + ",#" + getThumb2ShiftValue(opcode, opcode >> 4 & 3);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ + ",#" + getThumb2ShiftValue(opcode, opcode >> 4 & 3);
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
- case thumb2_asr__reg: // A8.6.15 ASR (register) // asr{s}<c>.w <Rd>,<Rn>,<Rm>
- case thumb2_lsl__reg: // A8.6.89 LSL (register) // lsl{s}<c>.w <Rd>,<Rm>,<Rm>
- case thumb2_lsr__reg: // A8.6.91 LSR (register) // lsr{s}<c>.w <Rd>,<Rn>,<Rm>
- case thumb2_ror__reg: // A8.6.140 ROR (register) // ror{s}<c>.w <Rd>,<Rn>,<Rm>
- // . . . . . . . . . . . S_1_4_4 Rn_1_3_0 . . . . Rd_0_11_8 . . . . Rm_0_3_0
+ case thumb2_asr__reg: // A8.6.15 ASR (register)
+ // asr{s}<c>.w <Rd>,<Rn>,<Rm>
+ case thumb2_lsl__reg: // A8.6.89 LSL (register)
+ // lsl{s}<c>.w <Rd>,<Rm>,<Rm>
+ case thumb2_lsr__reg: // A8.6.91 LSR (register)
+ // lsr{s}<c>.w <Rd>,<Rn>,<Rm>
+ case thumb2_ror__reg: // A8.6.140 ROR (register)
+ // ror{s}<c>.w <Rd>,<Rn>,<Rm>
mnemonic += getS(opcode) + ".w\t";
instruction = mnemonic + getR_8(opcode) + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
- case thumb2_b__cond: // A8.6.16 B // b<c>.w <label> Not permitted in IT block.
- // 1 1 1 1 0 S_1_10_10 cond_1_9_6 imm6_1_5_0 1 0 J1_0_13_13 0 J2_0_11_11 imm11_0_10_0
+ case thumb2_b__cond: // A8.6.16 B
+ // b<c>.w <label> Not permitted in IT block.
instruction = getThumb2Condition(opcode);
setDefaultPCJumpProperties(instruction.length() == 0); // true if unconditional b
offset = getThumb2_condB_Offset(opcode);
@@ -3113,29 +3171,31 @@
instruction = mnemonic + instruction + ".w\t" + jumpToAddr.toHexAddressString();
break;
- case thumb2_b__uncond: // A8.6.16 B // b<c>.w <label> Outside or last in IT block
+ case thumb2_b__uncond: // A8.6.16 B
+ // b<c>.w <label> Outside or last in IT block
if (ARMv6 > versionMode) {
instruction = IDisassembler.INVALID_OPCODE;
break;
}
// otherwise, no break!
- case thumb2_bl: // A8.6.23 BL (immediate) // bl<c> <label> Outside or last in IT block
+ case thumb2_bl: // A8.6.23 BL (immediate)
+ // bl<c> <label> Outside or last in IT block
// 1 1 1 1 0 S_1_10_10 imm10_1_9_0 1 1 J1_0_13_13 1 J2_0_11_11 imm11_0_10_0
// . . . . . S_1_10_10 imm10_1_9_0 . . J1_0_13_13 . J2_0_11_11 imm11_0_10_0
case thumb2_blx: // A8.6.23 BLX (immediate) // blx<c> <label> Outside or last in IT block
// 1 1 1 1 0 S_1_10_10 imm10H_1_9_0 1 1 J1_0_13_13 0 J2_0_11_11 imm10L_0_10_1 h_0_1_0
- // if you are reading this and confused that the above 3 are "the same",
- // my apologies. the ref manual used to state Encoding T2 bit 0
- // was always 0, and now has a late annotation that bit 0 is
- // supposed to be H, and that blx (immediate) is UNDEFINED for h==1.
- // since h must be 0, and SignExtend() for the 2 cases are:
+ // If you are confused that the above 3 opcode bit maps are "the same",
+ // my apologies. The manual used to state Encoding T2 bit 0
+ // was always 0, and now says that bit 0 is field h,
+ // and that blx (immediate) is UNDEFINED for h == 1.
+ // Since h must be 0, and SignExtend() for the 2 cases are:
// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); // Encoding T1
// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32) // Encoding T2
- // the conclusion is that pretending to get imm11_0_10_0
+ // The conclusion is that pretending to get imm11_0_10_0
// for the blx (immediate) T2 case is the same since the
// end '0' will match the left 0 in the '00' for T2.
- // thus it's okay to use the same code for both cases.
+ // Thus it's okay to use the same code for both cases.
{ // first, disallow this conditionally based on ref-manual rules if pre-ARMv6
@@ -3144,7 +3204,7 @@
instruction = IDisassembler.INVALID_OPCODE;
break;
}
-
+
offset = getThumb2_uncondB_Offset(opcode, j1, j2);
}
@@ -3154,65 +3214,74 @@
isSubroutineAddress = (opcodeIndex != OpcodeARM.Index.thumb2_b__uncond);
break;
- case thumb2_bfi: // A8.6.18 BFI // bfi<c> <Rd>,<Rn>,#<lsb>,#<width>
- // 1 1 1 1 0 (0) 1 1 0 1 1 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) msb_0_4_0
+ case thumb2_bfi: // A8.6.18 BFI
+ // bfi<c> <Rd>,<Rn>,#<lsb>,#<width>
instruction = "," + getR_16(opcode);
// no break!
- case thumb2_bfc: // A8.6.17 BFC // bfc<c> <Rd>,#<lsb>,#<width>
- // 1 1 1 1 0 (0) 1 1 0 1 1 0 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) msb_0_4_0
+ case thumb2_bfc: // A8.6.17 BFC
+ // bfc<c> <Rd>,#<lsb>,#<width>
{
int lsb = opcode >> 10 & 0x1c | opcode >> 6 & 3;
int width = (opcode & 0x1f) - lsb + 1;
instruction = mnemonic + TAB + getR_8(opcode) + instruction + ",#" + lsb + ",#" + width;
- // No pc check: if Rd is PC, the instruction is unpredictable
+ // No PC check: if Rd is PC, the instruction is UNPREDICTABLE
break;
}
- case thumb2_bfx: // A8.6.154 SBFX // sbfx<c> <Rd>,<Rn>,#<lsb>,#<width>
- // A8.6.236 UBFX // ubfx<c> <Rd>,<Rn>,#<lsb>,#<width>
- // . . . . . (0) . . U_1_7_7 . . . Rn_1_3_0 . imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) widthm1
+ case thumb2_bfx: // A8.6.154 SBFX
+ // sbfx<c> <Rd>,<Rn>,#<lsb>,#<width>
+ // A8.6.236 UBFX
+ // ubfx<c> <Rd>,<Rn>,#<lsb>,#<width>
mnemonic = (isBitEnabled(opcode, 23) ? "u" : "s") + mnemonic;
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode)
- + ",#" + getThumb2ShiftValue(opcode, 0) + ",#" + ((opcode & 0x1f) + 1);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ",#" + getThumb2ShiftValue(opcode, 0) + ",#" + ((opcode & 0x1f) + 1);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_bxj: // A8.6.26 BXJ // bxj<c> <Rm> Outside or last in IT block
- // 1 1 1 1 0 0 1 1 1 1 0 0 Rm_1_3_0 1 0 (0) 0 (1)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)
+ case thumb2_bxj: // A8.6.26 BXJ
+ // bxj<c> <Rm> Outside or last in IT block
instruction = mnemonic + TAB + getR_16(opcode);
setDefaultPCJumpProperties(true);
break;
- case thumb2_clrex: // A8.6.30 CLREX // clrex<c>
+ case thumb2_clrex: // A8.6.30 CLREX
+ // clrex<c>
if (ARMv7 > versionMode) {
instruction = IDisassembler.INVALID_OPCODE;
break;
}
- // else no break!
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 0 1 0 (1)(1)(1)(1)
- case thumb2_sev: // A8.6.158 SEV // sev<c>.w
- case thumb2_wfe: // A8.6.411 WFE // wfe<c>.w
- case thumb2_wfi: // A8.6.412 WFI // wfi<c>.w
- case thumb2_yield: // A8.6.413 YIELD // yield<c>.w
- // . . . . . . . . . . . . (1)(1)(1) (1) . . (0) . (0) . . . . . . . . . . .
+// else no break!
+ case thumb2_sev: // A8.6.158 SEV
+ // sev<c>.w
+ case thumb2_wfe: // A8.6.411 WFE
+ // wfe<c>.w
+ case thumb2_wfi: // A8.6.412 WFI
+ // wfi<c>.w
+ case thumb2_yield: // A8.6.413 YIELD
+ // yield<c>.w
if (ARMv6T2 == versionMode) {
mnemonic = "nop.w";
}
- // else no break!
- case thumb2_nop:
+// else no break!
+ case thumb2_nop: // A8.6.110 NOP
+ // nop<c>.w
case thumb2_undefined:
if (ARMv6K == versionMode) {
instruction = IDisassembler.INVALID_OPCODE;
} else if (ARMv6T2 <= versionMode) {
instruction = mnemonic;
}
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
- case thumb2_reverse: // A8.6.134 RBIT // rbit<c> <Rd>,<Rm>
- // A8.6.135 REV // rev<c>.w <Rd>,<Rm>
- // A8.6.136 REV16 // rev16<c>.w <Rd>,<Rm>
- // A8.6.137 REVSH // revsh<c>.w <Rd>,<Rm>
+ case thumb2_reverse: // A8.6.134 RBIT
+ // rbit<c> <Rd>,<Rm>
+ // A8.6.135 REV
+ // rev<c>.w <Rd>,<Rm>
+ // A8.6.136 REV16
+ // rev16<c>.w <Rd>,<Rm>
+ // A8.6.137 REVSH
+ // revsh<c>.w <Rd>,<Rm>
switch (opcode >> 4 & 3) {
case 0: mnemonic += "ev.w"; break;
case 1: mnemonic += "ev16.w"; break;
@@ -3220,35 +3289,41 @@
case 3: mnemonic += "evsh.w"; break;
}
// no break!
- case thumb2_clz: // A8.6.31 CLZ // clz<c> <Rd>,<Rm>
- // . . . . . . . . . . . . Rm_1_3_0 . . . . Rd_0_11_8 . . . . Rm_0_3_0
+ case thumb2_clz: // A8.6.31 CLZ
+ // clz<c> <Rd>,<Rm>
regDest = getR_8(opcode);
instruction = mnemonic + TAB + regDest + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_cmn__imm: // A8.6.32 CMN (immediate) // cmn<c> <Rn>,#<const>
- case thumb2_cmp__imm: // A8.6.35 CMP (immediate) // cmp<c>.w <Rn>,#<const>
- case thumb2_teq__imm: // A8.6.227 TEQ (immediate) // teq<c> <Rn>,#<const>
- case thumb2_tst__imm: // A8.6.230 TST (immediate) // tst<c> <Rn>,#<const>
- // . . . . . i_1_10_10 . . . . . . Rn_1_3_0 . imm3_0_14_12 . . . . imm8_0_7_0
+ case thumb2_cmn__imm: // A8.6.32 CMN (immediate
+ // cmn<c> <Rn>,#<const>
+ case thumb2_cmp__imm: // A8.6.35 CMP (immediate)
+ // cmp<c>.w <Rn>,#<const>
+ case thumb2_teq__imm: // A8.6.227 TEQ (immediate)
+ // teq<c> <Rn>,#<const>
+ case thumb2_tst__imm: // A8.6.230 TST (immediate)
+ // tst<c> <Rn>,#<const>
instruction = mnemonic + TAB + getR_16(opcode)
- + ",#" + getThumb2ExpandImm12(opcode);
- // No pc check: no registers changed
+ + ",#" + getThumb2ExpandImm12(opcode);
+ // No PC check: no registers changed
break;
- case thumb2_cmn__reg: // A8.6.33 CMN (register) // cmn<c> <Rn>,<Rm>{,<shift>}
- case thumb2_cmp__reg: // A8.6.36 CMP (register) // cmp<c>.w <Rn>,<Rm> {,<shift>}
- case thumb2_teq__reg: // A8.6.228 TEQ (register) // teq<c> <Rn>,<Rm>{,<shift>}
- case thumb2_tst__reg: // A8.6.231 TST (register) // tst<c> <Rn>,<Rm>{,<shift>}
- // . . . . . . . . . . . . Rn_1_3_0 (0) imm3_0_14_12 . . . . imm2_0_7_6 type_0_5_4 Rm_0_3_0
+ case thumb2_cmn__reg: // A8.6.33 CMN (register)
+ // cmn<c> <Rn>,<Rm>{,<shift>}
+ case thumb2_cmp__reg: // A8.6.36 CMP (register)
+ // cmp<c>.w <Rn>,<Rm> {,<shift>}
+ case thumb2_teq__reg: // A8.6.228 TEQ (register)
+ // teq<c> <Rn>,<Rm>{,<shift>}
+ case thumb2_tst__reg: // A8.6.231 TST (register)
+ // tst<c> <Rn>,<Rm>{,<shift>}
instruction = mnemonic + instruction + TAB + getR_16(opcode) + ','
- + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
- // No pc check: no registers changed
+ + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
+ // No PC check: no registers changed
break;
- case thumb2_dbg: // A8.6.40 DBG // dbg<c> #<option>
- // . . . . . . . . . . . . (1)(1)(1) (1) . . (0) . (1)(1)(1)(1) . . . . option_0_3_0
+ case thumb2_dbg: // A8.6.40 DBG
+ // dbg<c> #<option>
if (ARMv6T2 == versionMode) {
instruction = "nop.w";
} else if (ARMv7 > versionMode) {
@@ -3256,37 +3331,40 @@
} else {
instruction = mnemonic + "\t#" + (opcode & 0xf);
}
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
- case thumb2_dmb: // A8.6.41 DMB // dmb<c> #<option>
- case thumb2_dsb: // A8.6.42 DSB // dsb<c> #<option>
+ case thumb2_dmb: // A8.6.41 DMB
+ // dmb<c> #<option>
+ case thumb2_dsb: // A8.6.42 DSB
+ // dsb<c> #<option>
if (ARMv7 > versionMode)
instruction = IDisassembler.INVALID_OPCODE;
else
instruction = mnemonic + TAB + getDataBarrierOption(opcode);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
case thumb2_enterx_leavex: // A9.3.1 ENTERX, LEAVEX
- // enterx Not permitted in IT block. leavex Not permitted in IT block.
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 0 0 J_0_4_4 (1)(1)(1)(1)
- // . . . . . . . . . . . . (1)(1)(1) (1) . . (0) . (1)(1)(1)(1) . . . J_0_4_4 (1)(1)(1)(1)
+ // enterx Not permitted in IT block.
+ // leavex Not permitted in IT block.
instruction = isBitEnabled(opcode, 4) ? mnemonic : "leavex";
+ // No PC check: not applicable
break;
- case thumb2_isb: // A8.6.49 ISB // isb<c> #<option>
- // . . . . . . . . . . . . (1)(1)(1) (1) . . (0) . (1)(1)(1)(1) . . . . option_0_3_0
+ case thumb2_isb: // A8.6.49 ISB
+ // isb<c> #<option>
if (ARMv7 > versionMode)
instruction = IDisassembler.INVALID_OPCODE;
else
instruction = mnemonic + TAB + getInstructionBarrierOption(opcode);
- // No pc check: no registers changed
+ // No PC check: no registers changed
break;
- case thumb2_ldm: // A8.6.53 LDM / LDMIA / LDMFD // ldm<c>.w <Rn>{!},<registers>
- case thumb2_ldmdb: // A8.6.55 LDMDB / LDMEA // ldmdb<c> <Rn>{!},<registers>
- // . . . . . . . . . . W_1_5_5 . Rn_1_3_0 P_0_15_15 M_0_14_14 (0) register_list_0_12_0
+ case thumb2_ldm: // A8.6.53 LDM / LDMIA / LDMFD
+ // ldm<c>.w <Rn>{!},<registers>
+ case thumb2_ldmdb: // A8.6.55 LDMDB / LDMEA
+ // ldmdb<c> <Rn>{!},<registers>
regDest = getRegList(opcode);
instruction = mnemonic + TAB + getR_16(opcode) + getW(opcode) + ',' + regDest;
if (regDest.contains("pc"))
@@ -3294,8 +3372,13 @@
break;
case thumb2_ldr:
- if (isBitEnabled(opcode, 22))
- checkPC = true; // most other cases will end up in thumb2_pld or thumb2_pli
+ if (isBitEnabled(opcode, 22)) {
+ // exclude ldrt, which has bit 22 set but does not allow RT = PC
+ if (!((opcode >> 8 & 0xf) == 0xe) || !((opcode >> 20 & 0xfff) == 0xf85))
+ checkPC = true;
+ // most other cases of Rt = 15 end up as thumb2_pld or thumb2_pli
+ }
+// no break!
case thumb2_str:
regDest = getR_12(opcode);
{
@@ -3303,21 +3386,40 @@
boolean isPC = rn.equals("pc");
boolean isReg = 0 == (opcode >> 6 & 0x3f);
if (isBitEnabled(opcode, 22)) {
- // A8.6.57 LDR (immediate, Thumb) // ldr<c>.w
- // A8.6.59 LDR (literal) // ldr.w
- // A8.6.60 LDR (register) // ldr<c>.w
- // A8.6.193 STR (immediate, Thumb) // str<c>.w
- // A8.6.195 STR (register) // str<c>.w
+ // A8.6.57 LDR (immediate, Thumb)
+ // ldr<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // ldr<c> <Rt>,[<Rn>,#-<imm8>]
+ // ldr<c> <Rt>,[<Rn>],#+/-<imm8>
+ // ldr<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.59 LDR (literal)
+ // ldr<c>.w <Rt>,<label>
+ // ldr<c>.w <Rt>,[pc,#-0] Special case
+ // A8.6.60 LDR (register)
+ // ldr<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.193 STR (immediate, Thumb)
+ // str<c>.w <Rt>,[<Rn>,#<imm12>]
+ // str<c> <Rt>,[<Rn>,#-<imm8>]
+ // str<c> <Rt>,[<Rn>],#+/-<imm8>
+ // str<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.195 STR (register)
+ // str<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
if (isPC || isBitEnabled(opcode, 23) || isReg)
mnemonic += ".w";
else if (0xe == (opcode >> 8 & 0xf))
mnemonic += 't';
-
+
} else if (isBitEnabled(opcode, 24)) {
- // A8.6.78 LDRSB (immediate)
- // A8.6.82 LDRSH (immediate)
- // A8.6.80 LDRSB (register) // ldrsb<c>.w
- // A8.6.84 LDRSH (register) // ldrsh<c>.w
+ // A8.6.78 LDRSB (immediate)
+ // ldrsb<c> <Rt>,[<Rn>,#<imm12>]
+ // A8.6.82 LDRSH (immediate)
+ // ldrsh<c> <Rt>,[<Rn>,#<imm12>]
+ // ldrsb<c> <Rt>,[<Rn>,#-<imm8>]
+ // ldrsb<c> <Rt>,[<Rn>],#+/-<imm8>
+ // ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.80 LDRSB (register)
+ // ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.84 LDRSH (register)
+ // ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
mnemonic += isBitEnabled(opcode, 21) ? "sh" : "sb";
if (!isPC) {
if (0xe == (opcode >> 8 & 0xf))
@@ -3326,16 +3428,40 @@
mnemonic += ".w";
}
} else {
- // A8.6.61 LDRB (immediate, Thumb) // ldrb<c>.w
- // A8.6.63 LDRB (literal) // ldrb
- // A8.6.64 LDRB (register) // ldrb<c>.w
- // A8.6.75 LDRH (literal) // ldrh
- // A8.6.73 LDRH (immediate, Thumb) // ldrh<c>.w
- // A8.6.76 LDRH (register) // ldrh<c>.w
- // A8.6.196 STRB (immediate, Thumb) // strb<c>.w
- // A8.6.198 STRB (register) // strb<c>.w
- // A8.6.206 STRH (immediate, Thumb) // strh<c>.w
- // A8.6.208 STRH (register) // strh<c>.w
+ // A8.6.61 LDRB (immediate, Thumb)
+ // ldrb<c> <Rt>,[<Rn>,#-<imm8>]
+ // ldrb<c> <Rt>,[<Rn>],#+/-<imm8>
+ // ldrb<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.63 LDRB (literal)
+ // ldrb<c> <Rt>,<label>
+ // ldrb<c> <Rt>,[pc,#-0] Special case
+ // A8.6.64 LDRB (register)
+ // ldrb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.73 LDRH (immediate, Thumb)
+ // ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // ldrh<c> <Rt>,[<Rn>,#-<imm8>]
+ // ldrh<c> <Rt>,[<Rn>],#+/-<imm8>
+ // ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.75 LDRH (literal)
+ // ldrh<c> <Rt>,<label>
+ // ldrh<c> <Rt>,[pc,#-0] Special case
+ // A8.6.76 LDRH (register)
+ // ldrh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.196 STRB (immediate, Thumb)
+ // strb<c> <Rt>,[<Rn>,#-<imm8>]
+ // strb<c> <Rt>,[<Rn>],#+/-<imm8>
+ // strb<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.198 STRB (register)
+ // strb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.206 STRH (immediate, Thumb)
+ // strh<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // strh<c> <Rt>,[<Rn>,#-<imm8>]
+ // strh<c> <Rt>,[<Rn>],#+/-<imm8>
+ // strh<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.208 STRH (register)
+ // strh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.210 STRT
+ // strt<c> <Rt>,[<Rn>,#<imm8>]
mnemonic += isBitEnabled(opcode, 21) ? "h" : "b";
if (!isPC) {
if (isBitEnabled(opcode, 23) || isReg)
@@ -3346,51 +3472,60 @@
}
instruction = mnemonic + TAB + regDest + ',';
if (isPC) {
- // A8.6.59 LDR (literal) // ldr.w <Rt>,[pc,#+/-<imm>] Alternative form
- // A8.6.63 LDRB (literal) // ldrb <Rt>,[pc,#+/-<imm>] Alternative form
- // A8.6.75 LDRH (literal) // ldrh <Rt>,[pc,#+/-<imm>] Alternative form
- // A8.6.79 LDRSB (literal) // ldrsb <Rt>,[pc,#+/-<imm>] Alternative form
- // A8.6.83 LDRSH (literal) // ldrsh <Rt>,[pc,#+/-<imm>] Alternative form
+ // A8.6.59 LDR (literal)
+ // ldr.w <Rt>,[pc,#+/-<imm>] Alternative form
+ // A8.6.63 LDRB (literal)
+ // ldrb <Rt>,[pc,#+/-<imm>] Alternative form
+ // A8.6.75 LDRH (literal)
+ // ldrh <Rt>,[pc,#+/-<imm>] Alternative form
+ // A8.6.79 LDRSB (literal)
+ // ldrsb <Rt>,[pc,#+/-<imm>] Alternative form
+ // A8.6.83 LDRSH (literal)
+ // ldrsh <Rt>,[pc,#+/-<imm>] Alternative form
// appends addr as UAL comment
instruction += getAddrModePCImm(opcode, opcode & 0xfff);
} else if (isBitEnabled(opcode, 23)) {
- // A8.6.57 LDR (immediate, Thumb) // ldr<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // A8.6.61 LDRB (immediate, Thumb) // ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // A8.6.73 LDRH (immediate, Thumb) // ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // A8.6.78 LDRSB (immediate) // ldrsb<c> <Rt>,[<Rn>{,#<imm12>}]
- // A8.6.82 LDRSH (immediate) // ldrsh<c> <Rt>,[<Rn>,#<imm12>]
- // A8.6.193 STR (immediate, Thumb) // str<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // A8.6.196 STRB (immediate, Thumb) // strb<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // A8.6.206 STRH (immediate, Thumb) // strh<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // A8.6.57 LDR (immediate, Thumb)
+ // A8.6.61 LDRB (immediate, Thumb)
+ // A8.6.73 LDRH (immediate, Thumb)
+ // A8.6.78 LDRSB (immediate)
+ // A8.6.193 STR (immediate, Thumb)
+ // A8.6.196 STRB (immediate, Thumb)
+ // A8.6.206 STRH (immediate, Thumb)
+ // <mnemonic><c>.w <Rt>,[<Rn>{,#<imm12>}]
+ //
+ // A8.6.82 LDRSH (immediate)
+ // ldrsh<c> <Rt>,[<Rn>,#<imm12>]
instruction += '[' + rn;
offset = opcode & 0xfff;
if (offset != 0)
instruction += ",#" + getHexValue(offset);
instruction += ']';
} else if (isReg) {
- // A8.6.60 LDR (register) // ldr<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.64 LDRB (register) // ldrb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.76 LDRH (register) // ldrh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.80 LDRSB (register) // ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.84 LDRSH (register) // ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.195 STR (register) // str<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.198 STRB (register) // strb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // A8.6.208 STRH (register) // strh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.60 LDR (register)
+ // A8.6.64 LDRB (register)
+ // A8.6.76 LDRH (register)
+ // A8.6.80 LDRSB (register)
+ // A8.6.84 LDRSH (register)
+ // A8.6.195 STR (register)
+ // A8.6.198 STRB (register)
+ // A8.6.208 STRH (register)
+ // <mnemonic><c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
instruction += getThumb2AddrModeRegImm(opcode);
} else {
- // A8.6.57 LDR (immediate, Thumb)
- // A8.6.61 LDRB (immediate, Thumb)
- // A8.6.73 LDRH (immediate, Thumb)
- // A8.6.78 LDRSB (immediate)
- // A8.6.82 LDRSH (immediate)
- // A8.6.193 STR (immediate, Thumb)
- // A8.6.196 STRB (immediate, Thumb)
- // A8.6.206 STRH (immediate, Thumb)
- // <mnemonic><c> <Rt>,[<Rn>,#-<imm8>]
- // <mnemonic> <Rt>,[<Rn>],#+/-<imm8>
- // <mnemonic> <Rt>,[<Rn>,#+/-<imm8>]!
-
+ // A8.6.57 LDR (immediate, Thumb)
+ // A8.6.61 LDRB (immediate, Thumb)
+ // A8.6.73 LDRH (immediate, Thumb)
+ // A8.6.78 LDRSB (immediate)
+ // A8.6.82 LDRSH (immediate)
+ // A8.6.193 STR (immediate, Thumb)
+ // A8.6.196 STRB (immediate, Thumb)
+ // A8.6.206 STRH (immediate, Thumb)
+ // <mnemonic><c> <Rt>,[<Rn>,#-<imm8>]
+ // <mnemonic><c> <Rt>,[<Rn>],#+/-<imm8>
+ // <mnemonic><c> <Rt>,[<Rn>,#+/-<imm8>]!
+
instruction += getThumb2AddrModeImm8(opcode, 10, 9, 8, 0);
}
}
@@ -3398,42 +3533,45 @@
setDefaultPCJumpProperties(true);
break;
- case thumb2_ldrex: // A8.6.69 LDREX // ldrex<c> <Rt>,[<Rn>{,#<imm>}]
- // . . . . . . . . . . . . Rn_1_3_0 Rt_0_15_12 . . . . imm8_0_7_0
+ case thumb2_ldrex: // A8.6.69 LDREX
+ // ldrex<c> <Rt>,[<Rn>{,#<imm>}]
offset = opcode & 0xff;
instruction = mnemonic + TAB + getR_12(opcode) + ",[" + getR_16(opcode);
if (offset != 0)
instruction += ",#" + getHexValue(offset << 2);
instruction += ']';
- // No pc check: PC at Rt location will generate different instruction or UNPREDICTABLE
+ // No PC check: PC at Rt location will generate different instruction or UNPREDICTABLE
break;
- case thumb2_ldrd__imm: // A8.6.66 LDRD (immediate) // ldrd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}]
- // ldrd <Rt>,<Rt2>,[<Rn>],#+/-<imm>
- // ldrd <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
- case thumb2_strd: // A8.6.200 STRD (immediate)// strd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}]
- // strd <Rt>,<Rt2>,[<Rn>],#+/-<imm>
- // strd <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
- // . . . . . . . P_1_8_8 U_1_7_7 . W_1_5_5 . Rn_1_3_0 Rt_0_15_12 Rt2_0_11_8 imm8_0_7_0
+ case thumb2_ldrd__imm: // A8.6.66 LDRD (immediate)
+ // ldrd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}]
+ // ldrd <Rt>,<Rt2>,[<Rn>],#+/-<imm>
+ // ldrd <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
+ case thumb2_strd: // A8.6.200 STRD (immediate)
+ // strd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}]
+ // strd <Rt>,<Rt2>,[<Rn>],#+/-<imm>
+ // strd <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
instruction = mnemonic + TAB + getR_12(opcode) + ',' + getR_8(opcode)
- + ',' + getThumb2AddrModeImm8(opcode, 24, 23, 21, 2);
- // No pc check: PC in <Rt,Rt2> is UNPREDICTABLE
+ + ',' + getThumb2AddrModeImm8(opcode, 24, 23, 21, 2);
+ // No PC check: PC in <Rt,Rt2> is UNPREDICTABLE
break;
- case thumb2_ldrd__lit: // A8.6.67 LDRD (literal) // ldrd<c> <Rt>,<Rt2>,<label> ldrd <Rt>,<Rt2>,[pc,#-0] Special case
- // 1 1 1 0 1 0 0 P_1_8_8 U_1_7_7 1 (0) 1 1 1 1 1 Rt_0_15_12 Rt2_0_11_8 imm8_0_7_0
+ case thumb2_ldrd__lit: // A8.6.67 LDRD (literal)
+ // ldrd<c> <Rt>,<Rt2>,<label>
+ // ldrd <Rt>,<Rt2>,[pc,#-0] Special case
offset = opcode & 0xff;
instruction = mnemonic + TAB + getR_12(opcode) + ',' + getR_8(opcode)
- + ",[pc,#" + ((isBitEnabled(opcode, 23) && offset != 0) ? "" : "-")
- + getHexValue(offset<<2) + ']';
- // No pc check: PC at Rt is UNPREDICTABLE
+ + ",[pc,#" + ((isBitEnabled(opcode, 23) && offset != 0) ? "" : "-")
+ + getHexValue(offset<<2) + ']';
+ // No PC check: PC at Rt is UNPREDICTABLE
break;
- case thumb2_ldrexx:
- // A8.6.70 LDREXB // ldrexb<c> <Rt>, [<Rn>]
- // A8.6.71 LDREXD // ldrexd<c> <Rt>,<Rt2>,[<Rn>]
- // A8.6.72 LDREXH // ldrexh<c> <Rt>, [<Rn>]
- // . . . . . . . . . . . . Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) . . . . (1)(1)(1)(1)
+ case thumb2_ldrexx: // A8.6.70 LDREXB
+ // ldrexb<c> <Rt>, [<Rn>]
+ // A8.6.71 LDREXD
+ // ldrexd<c> <Rt>,<Rt2>,[<Rn>]
+ // A8.6.72 LDREXH
+ // ldrexh<c> <Rt>, [<Rn>]
if (isBitEnabled(opcode, 5)) {
mnemonic += 'd';
instruction = "," + getR_8(opcode);
@@ -3441,97 +3579,128 @@
mnemonic += isBitEnabled(opcode, 4) ? 'h' : 'b';
}
instruction = mnemonic + TAB + getR_12(opcode) + instruction
- + ",[" + getR_16(opcode) + ']';
- // No pc check: PC at Rt is UNPREDICTABLE
+ + ",[" + getR_16(opcode) + ']';
+ // No PC check: PC at Rt is UNPREDICTABLE
break;
- case thumb2_ml: // A8.6.94 MLA // mla<c> <Rd>,<Rn>,<Rm>,<Ra>
+ case thumb2_ml: // A8.6.94 MLA
+ // mla<c> <Rd>,<Rn>,<Rm>,<Ra>
mnemonic += isBitEnabled(opcode, 4) ? 's' : 'a';
- case thumb2_usada8: // A8.6.254 USADA8 // usada8<c> <Rd>,<Rn>,<Rm>,<Ra>
- // . . . . . . . . . . . . Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 . . . . Rm_0_3_0
+ case thumb2_usada8: // A8.6.254 USADA8
+ // usada8<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode)
- + ',' + getR_0(opcode) + ',' + getR_12(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_0(opcode) + ',' + getR_12(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_mov__reg: // A8.6.97 MOV (register) // mov{s}<c>.w <Rd>,<Rm>
+ case thumb2_mov__reg: // A8.6.97 MOV (register)
+ // mov{s}<c>.w <Rd>,<Rm>
instruction = ".w";
- checkPC = true;
// no break!
- case thumb2_rrx: // A8.6.141 RRX // rrx{s}<c> <Rd>,<Rm>
- // . . . . . . . . . . . S_1_4_4 . . . . (0) . . . Rd_0_11_8 . . . . Rm_0_3_0
+ case thumb2_rrx: // A8.6.141 RRX
+ // rrx{s}<c> <Rd>,<Rm>
regDest = getR_8(opcode);
instruction = mnemonic + getS(opcode) + instruction + TAB + regDest + "," + getR_0(opcode);
- if (checkPC && regDest.equals("pc"))
- setDefaultPCJumpProperties(true);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_movx: // A8.6.96 MOV (immediate) // movw<c> <Rd>,#<imm16>
- // A8.6.99 MOVT // movt<c> <Rd>,#<imm16>
- // . . . . . i_1_10_10 . . . . . . imm4_1_3_0 . imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
+ case thumb2_movx: // A8.6.96 MOV (immediate)
+ // movw<c> <Rd>,#<imm16>
+ // A8.6.99 MOVT
+ // movt<c> <Rd>,#<imm16>
mnemonic += isBitEnabled(opcode, 23) ? 't' : 'w';
instruction = mnemonic + TAB + getR_8(opcode) + ",#" + getThumb2ImmForMovX(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_mrs:
- // A8.6.102 MRS
- // mrs<c> <Rd>,<spec_reg>
- // 1 1 1 1 0 0 1 1 1 1 1 0 (1)(1)(1) (1) 1 0 (0) 0 Rd_0_11_8 (0)(0)(0)(0)(0)(0)(0)(0)
- // B6.1.5 MRS
- // mrs <Rd>,<spec_reg>
- // 1 1 1 1 0 0 1 1 1 1 1 R_1_4_4 (1)(1)(1) (1) 1 0 (0) 0 Rd_0_11_8 (0)(0)(0)(0)(0)(0)(0)(0)
+ case thumb2_mrs: // A8.6.102 MRS
+ // mrs<c> <Rd>,<spec_reg>
+ // B6.1.5 MRS
+ // mrs <Rd>,<spec_reg>
instruction = mnemonic + TAB + getR_8(opcode)
- + ',' + (isBitEnabled(opcode, 20) ? 's' : 'c') + "psr";
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + (isBitEnabled(opcode, 20) ? 's' : 'c') + "psr";
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_msr:
- // B6.1.7 MSR (register)
- // msr <spec_reg>,<Rn>
- // 1 1 1 1 0 0 1 1 1 0 0 R_1_4_4 Rn_1_3_0 1 0 (0) 0 mask_0_11_8 (0)(0)(0)(0)(0)(0)(0)(0)
+ case thumb2_msr: // B6.1.7 MSR (register)
+ // msr <spec_reg>,<Rn>
instruction = mnemonic + TAB + getStatusReg(opcode, 20)
- + getStatusRegFields(opcode, 8) + ',' + getR_16(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + getStatusRegFields(opcode, 8) + ',' + getR_16(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2__r_dnm_math:
- // A8.6.125 QADD16 // qadd16<c> <Rd>,<Rn>,<Rm>
- // A8.6.126 QADD8 // qadd8<c> <Rd>,<Rn>,<Rm>
- // A8.6.127 QASX // qasx<c> <Rd>,<Rn>,<Rm>
- // A8.6.130 QSAX // qsax<c> <Rd>,<Rn>,<Rm>
- // A8.6.132 QSUB16 // qsub16<c> <Rd>,<Rn>,<Rm>
- // A8.6.133 QSUB8 // qsub8<c> <Rd>,<Rn>,<Rm>
- // A8.6.148 SADD16 // sadd16<c> <Rd>,<Rn>,<Rm>
- // A8.6.149 SADD8 // sadd8<c> <Rd>,<Rn>,<Rm>
- // A8.6.150 SASX // sasx<c> <Rd>,<Rn>,<Rm>
- // A8.6.159 SHADD16 // shadd16<c> <Rd>,<Rn>,<Rm>
- // A8.6.160 SHADD8 // shadd8<c> <Rd>,<Rn>,<Rm>
- // A8.6.161 SHASX // shasx<c> <Rd>,<Rn>,<Rm>
- // A8.6.162 SHSAX // shsax<c> <Rd>,<Rn>,<Rm>
- // A8.6.163 SHSUB16 // shsub16<c> <Rd>,<Rn>,<Rm>
- // A8.6.164 SHSUB8 // shsub8<c> <Rd>,<Rn>,<Rm>
- // A8.6.185 SSAX // ssax<c> <Rd>,<Rn>,<Rm>
- // A8.6.186 SSUB16 // ssub16<c> <Rd>,<Rn>,<Rm>
- // A8.6.187 SSUB8 // ssub8<c> <Rd>,<Rn>,<Rm>
- // A8.6.233 UADD16 // uadd16<c> <Rd>,<Rn>,<Rm>
- // A8.6.234 UADD8 // uadd8<c> <Rd>,<Rn>,<Rm>
- // A8.6.235 UASX // uasx<c> <Rd>,<Rn>,<Rm>
- // A8.6.238 UHADD16 // uhadd16<c> <Rd>,<Rn>,<Rm>
- // A8.6.239 UHADD8 // uhadd8<c> <Rd>,<Rn>,<Rm>
- // A8.6.240 UHASX // uhasx<c> <Rd>,<Rn>,<Rm>
- // A8.6.241 UHSAX // uhsax<c> <Rd>,<Rn>,<Rm>
- // A8.6.242 UHSUB16 // uhsub16<c> <Rd>,<Rn>,<Rm>
- // A8.6.243 UHSUB8 // uhsub8<c> <Rd>,<Rn>,<Rm>
- // A8.6.247 UQADD16 // uqadd16<c> <Rd>,<Rn>,<Rm>
- // A8.6.248 UQADD8 // uqadd8<c> <Rd>,<Rn>,<Rm>
- // A8.6.249 UQASX // uqasx<c> <Rd>,<Rn>,<Rm>
- // A8.6.250 UQSAX // uqsax<c> <Rd>,<Rn>,<Rm>
- // A8.6.251 UQSUB16 // uqsub16<c> <Rd>,<Rn>,<Rm>
- // A8.6.252 UQSUB8 // uqsub8<c> <Rd>,<Rn>,<Rm>
- // A8.6.257 USAX // usax<c> <Rd>,<Rn>,<Rm>
- // A8.6.258 USUB16 // usub16<c> <Rd>,<Rn>,<Rm>
- // A8.6.259 USUB8 // usub8<c> <Rd>,<Rn>,<Rm>
+ case thumb2__r_dnm_math: // A8.6.125 QADD16
+ // qadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.126 QADD8
+ // qadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.127 QASX
+ // qasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.130 QSAX
+ // qsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.132 QSUB16
+ // qsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.133 QSUB8
+ // qsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.148 SADD16
+ // sadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.149 SADD8
+ // sadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.150 SASX
+ // sasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.159 SHADD16
+ // shadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.160 SHADD8
+ // shadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.161 SHASX
+ // shasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.162 SHSAX
+ // shsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.163 SHSUB16
+ // shsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.164 SHSUB8
+ // shsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.185 SSAX
+ // ssax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.186 SSUB16
+ // ssub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.187 SSUB8
+ // ssub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.233 UADD16
+ // uadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.234 UADD8
+ // uadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.235 UASX
+ // uasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.238 UHADD16
+ // uhadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.239 UHADD8
+ // uhadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.240 UHASX
+ // uhasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.241 UHSAX
+ // uhsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.242 UHSUB16
+ // uhsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.243 UHSUB8
+ // uhsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.247 UQADD16
+ // uqadd16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.248 UQADD8
+ // uqadd8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.249 UQASX
+ // uqasx<c> <Rd>,<Rn>,<Rm>
+ // A8.6.250 UQSAX
+ // uqsax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.251 UQSUB16
+ // uqsub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.252 UQSUB8
+ // uqsub8<c> <Rd>,<Rn>,<Rm>
+ // A8.6.257 USAX
+ // usax<c> <Rd>,<Rn>,<Rm>
+ // A8.6.258 USUB16
+ // usub16<c> <Rd>,<Rn>,<Rm>
+ // A8.6.259 USUB8
+ // usub8<c> <Rd>,<Rn>,<Rm>
if (1 == (opcode >> 4 & 7))
mnemonic = "";
else
@@ -3549,86 +3718,96 @@
case 6: mnemonic += "sax"; break;
}
// no break!
- case thumb2_mul: // A8.6.105 MUL // mul<c> <Rd>,<Rn>,<Rm>
- case thumb2_sel: // A8.6.156 SEL // sel<c> <Rd>,<Rn>,<Rm>
- case thumb2_usad8: // A8.6.253 USAD8 // usad8<c> <Rd>,<Rn>,<Rm>
- // . . . . . . . . . . . . Rn_1_3_0 . . . . Rd_0_11_8 . . . . Rm_0_3_0
-
+ case thumb2_mul: // A8.6.105 MUL
+ // mul<c> <Rd>,<Rn>,<Rm>
+ case thumb2_sel: // A8.6.156 SEL
+ // sel<c> <Rd>,<Rn>,<Rm>
+ case thumb2_usad8: // A8.6.253 USAD8
+ // usad8<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_sdiv: // A8.6.155 SDIV // sdiv<c> <Rd>,<Rn>,<Rm>
- case thumb2_udiv: // A8.6.237 UDIV // udiv<c> <Rd>,<Rn>,<Rm>
- // . . . . . . . . . . . . Rn_1_3_0 (1) (1)(1)(1) Rd_0_11_8 . . . . Rm_0_3_0
+ case thumb2_sdiv: // A8.6.155 SDIV
+ // sdiv<c> <Rd>,<Rn>,<Rm>
+ case thumb2_udiv: // A8.6.237 UDIV
+ // udiv<c> <Rd>,<Rn>,<Rm>
if (ARMv7 > versionMode) {
instruction = IDisassembler.INVALID_OPCODE;
break;
}
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_qadd: // A8.6.124 QADD // qadd<c> <Rd>,<Rm>,<Rn>
- // A8.6.128 QDADD // qdadd<c> <Rd>,<Rm>,<Rn>
- case thumb2_qsub: // A8.6.129 QDSUB // qdsub<c> <Rd>,<Rm>,<Rn>
- // A8.6.131 QSUB // qsub<c> <Rd>,<Rm>,<Rn>
+ case thumb2_qadd: // A8.6.124 QADD
+ // qadd<c> <Rd>,<Rm>,<Rn>
+ // A8.6.128 QDADD
+ // qdadd<c> <Rd>,<Rm>,<Rn>
+ case thumb2_qsub: // A8.6.129 QDSUB
+ // qdsub<c> <Rd>,<Rm>,<Rn>
+ // A8.6.131 QSUB
+ // qsub<c> <Rd>,<Rm>,<Rn>
mnemonic = (isBitEnabled(opcode, 4) ? "qd" : "q") + mnemonic;
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_0(opcode) + ',' + getR_16(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
-
- case thumb2_pkh: // A8.6.116 PKH // pkhbt<c> <Rd>,<Rn>,<Rm>{,lsl #<imm>}
- // pkhtb <Rd>,<Rn>,<Rm>{,asr #<imm>}
+
+ case thumb2_pkh: // A8.6.116 PKH
+ // pkhbt<c> <Rd>,<Rn>,<Rm>{,lsl #<imm>}
+ // pkhtb <Rd>,<Rn>,<Rm>{,asr #<imm>}
// 1 1 1 0 1 0 1 0 1 1 0 0 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 tb_0_5_5 0 Rm_0_3_0
mnemonic += isBitEnabled(opcode, 5) ? "tb\t" : "bt\t";
instruction = mnemonic + getR_8(opcode) + ',' + getR_16(opcode) + ','
- + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + getR_0(opcode) + getThumb2ShiftMode(opcode, 4);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
case thumb2_pld:
case thumb2_pli:
- if ((opcode >> 16 & 0xf) == 15) {
- // A8.6.118 PLD (literal) // pld<c> <label> pld [pc,#-0] Special case
- // 1 1 1 1 1 0 0 0 U_1_7_7 0 (0) 1 1 1 1 1 1 1 1 1 imm12_0_11_0
- // A8.6.120 PLI (immediate, literal) // pli<c> <label> pli [pc,#-0] Special case
- // 1 1 1 1 1 0 0 1 U_1_7_7 0 0 1 1 1 1 1 1 1 1 1 imm12_0_11_0
+ if ((opcode >> 16 & 0xf) == 15) {
+ // A8.6.118 PLD (literal)
+ // pld<c> <label>
+ // pld [pc,#-0] Special case
+ // A8.6.120 PLI (immediate, literal)
+ // pli<c> <label>
+ // pli [pc,#-0] Special case
instruction = mnemonic + TAB + getAddrModePCImm(opcode, opcode & 0xfff);
} else if (isBitEnabled(opcode, 23) || isBitEnabled(opcode, 11)){
String imm;
if (isBitEnabled(opcode, 23)) {
- // A8.6.117 PLD, PLDW (immediate) // pld{w}<c> [<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 0 1 0 W_1_5_5 1 Rn_1_3_0 1 1 1 1 imm12_0_11_0
- // A8.6.120 PLI (immediate, literal) // pli<c> [<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 1 1 0 0 1 Rn_1_3_0 1 1 1 1 imm12_0_11_0
+ // A8.6.117 PLD, PLDW (immediate)
+ // pld{w}<c> [<Rn>,#<imm12>]
+ // A8.6.120 PLI (immediate, literal)
+ // pli<c> [<Rn>,#<imm12>]
imm = getImmediate12(opcode);
- } else {
- // A8.6.117 PLD, PLDW (immediate) // pld{w}<c> [<Rn>,#-<imm8>]
- // 1 1 1 1 1 0 0 0 0 0 W_1_5_5 1 Rn_1_3_0 1 1 1 1 1 1 0 0 imm8_0_7_0
- // A8.6.120 PLI (immediate, literal) // pli<c> [<Rn>,#-<imm8>]
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 1 1 1 1 1 1 0 0 imm8_0_7_0
+ } else {
+ // A8.6.117 PLD, PLDW (immediate)
+ // pld{w}<c> [<Rn>,#-<imm8>]
+ // A8.6.120 PLI (immediate, literal)
+ // pli<c> [<Rn>,#-<imm8>]
imm = "#-" + getHexValue(opcode & 0xff);
}
instruction = mnemonic + (isBitEnabled(opcode, 21) ? "w\t[" : "\t[")
- + getR_16(opcode) + ',' + imm + ']';
+ + getR_16(opcode) + ',' + imm + ']';
} else {
- // A8.6.119 PLD, PLDW (register) // pld{w}<c> [<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 0 W_1_5_5 1 Rn_1_3_0 1 1 1 1 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // A8.6.121 PLI (register) // pli<c> [<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 1 1 1 1 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
+ // A8.6.119 PLD, PLDW (register)
+ // pld{w}<c> [<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.121 PLI (register)
+ // pli<c> [<Rn>,<Rm>{,lsl #<imm2>}]
instruction = mnemonic + (isBitEnabled(opcode, 21) ? "w\t" : "\t")
- + getThumb2AddrModeRegImm(opcode);
+ + getThumb2AddrModeRegImm(opcode);
}
- // No pc check: PC at Rn is handled above as literal
+ // No PC check: PC at Rn is handled above as literal
break;
- case thumb2_pop__regs: // A8.6.122 POP // pop<c>.w <registers> <registers> contains more than one register
- // 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P_0_15_15 M_0_14_14 (0) register_list_0_12_0
+ case thumb2_pop__regs: // A8.6.122 POP
+ // pop<c>.w <registers> <registers> contains more than one register
checkPC = true;
// no break!
- case thumb2_push__regs: // A8.6.123 PUSH // push<c>.w <registers> <registers> contains more than one register
+ case thumb2_push__regs: // A8.6.123 PUSH
+ // push<c>.w <registers> <registers> contains more than one register
// 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 (0) M_0_14_14 (0) register_list_0_12_0
regDest = getRegList(opcode);
instruction = mnemonic + TAB + regDest;
@@ -3636,162 +3815,176 @@
setDefaultPCJumpProperties(true);
break;
- case thumb2_pop__reg: // A8.6.122 POP // pop<c>.w <registers> <registers> contains one register, <Rt>
+ case thumb2_pop__reg: // A8.6.122 POP
+ // pop<c>.w <registers> <registers> contains one register, <Rt>
checkPC = true;
// no break!
- case thumb2_push__reg: // A8.6.123 PUSH // push<c>.w <registers> <registers> contains one register, <Rt>
+ case thumb2_push__reg: // A8.6.123 PUSH
+ // push<c>.w <registers> <registers> contains one register, <Rt>
regDest = getR_12(opcode);
instruction = mnemonic + TAB + '{' + regDest + '}';
if (regDest.equals("pc"))
setDefaultPCJumpProperties(true);
break;
- case thumb2_rfe: // B6.1.8 RFE // rfe{ia}<c> <Rn>{!} Outside or last in IT block
- // rfedb <Rn>{!} Outside or last in IT block
- // . . . . . . . . . . W_1_5_5 . Rn_1_3_0 (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
+ case thumb2_rfe: // B6.1.8 RFE
+ // rfe{ia}<c> <Rn>{!} Outside or last in IT block
+ // rfedb <Rn>{!} Outside or last in IT block
instruction = mnemonic
- + (isBitEnabled(opcode, 24) /* && isBitEnabled(opcode, 23) */ ? "ia\t" : "db\t")
- + getR_16(opcode) + getW(opcode);
+ + (isBitEnabled(opcode, 24) /* && isBitEnabled(opcode, 23) */ ? "ia\t" : "db\t")
+ + getR_16(opcode) + getW(opcode);
setDefaultPCJumpProperties(true);
break;
- case thumb2_smc: // B6.1.9 SMC (previously SMI) // smc #<imm4>
- // 1 1 1 1 0 1 1 1 1 1 1 1 imm4_1_3_0 1 0 0 0 (0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
+ case thumb2_smc: // B6.1.9 SMC (previously SMI)
+ // smc #<imm4>
instruction = mnemonic + "\t#" + getHexValue(opcode >> 16 & 0xf);
+ // No PC check: not applicable
break;
- case thumb2_smla: // A8.6.166 SMLABB, SMLABT, SMLATB, SMLATT // smla<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 0 1 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 N_0_5_5 M_0_4_4 Rm_0_3_0
+ case thumb2_smla: // A8.6.166 SMLABB, SMLABT, SMLATB, SMLATT
+ // smla<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getBorT(opcode, 5) + getBorT(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode) + ',' + getR_12(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode) + ',' + getR_12(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smlad: // A8.6.167 SMLAD // smlad{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
- case thumb2_smlsd: // A8.6.172 SMLSD // smlsd{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // . . . . . . . . . . . . Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 . . . M_0_4_4 Rm_0_3_0
+ case thumb2_smlad: // A8.6.167 SMLAD
+ // smlad{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
+ case thumb2_smlsd: // A8.6.172 SMLSD
+ // smlsd{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getX(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode) + ',' + getR_12(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode) + ',' + getR_12(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smlal: // A8.6.168 SMLAL // smlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // A8.6.169 SMLALBB, SMLALBT, SMLALTB, SMLALTT
- // smlal<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 0 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 0 0 0 0 Rm_0_3_0
- // 1 1 1 1 1 0 1 1 1 1 0 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 1 0 N_0_5_5 M_0_4_4 Rm_0_3_0
+ case thumb2_smlal: // A8.6.168 SMLAL
+ // smlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ // A8.6.169 SMLALBB, SMLALBT, SMLALTB, SMLALTT
+ // smlal<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm>
if (isBitEnabled(opcode, 7))
mnemonic += getBorT(opcode, 5) + getBorT(opcode, 4);
// no break!
- case thumb2_smull: // A8.6.179 SMULL // smull<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- case thumb2_umaal: // A8.6.244 UMAAL // umaal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- case thumb2_umlal: // A8.6.245 UMLAL // umlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- case thumb2_umull: // A8.6.246 UMULL // umull<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // . . . . . . . . . . . . Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 . . . . Rm_0_3_0
+ case thumb2_smull: // A8.6.179 SMULL
+ // smull<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ case thumb2_umaal: // A8.6.244 UMAAL
+ // umaal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ case thumb2_umlal: // A8.6.245 UMLAL
+ // umlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ case thumb2_umull: // A8.6.246 UMULL
+ // umull<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + TAB + getR_12(opcode) + ',' + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at RdLo or RdHi or Rn or Rm is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode);
+ // No PC check: PC at RdLo or RdHi or Rn or Rm is UNPREDICTABLE
break;
- case thumb2_smlald: // A8.6.170 SMLALD // smlald{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- case thumb2_smlsld: // A8.6.173 SMLSLD // smlsld{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // . . . . . . . . . . . . Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 . . . M_0_4_4 Rm_0_3_0
+ case thumb2_smlald: // A8.6.170 SMLALD
+ // smlald{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ case thumb2_smlsld: // A8.6.173 SMLSLD
+ // smlsld{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
instruction = mnemonic + getX(opcode, 4) + TAB + getR_12(opcode)
- + ',' + getR_8(opcode) + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_8(opcode) + ',' + getR_16(opcode) + ',' + getR_0(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smlaw: // A8.6.171 SMLAWB, SMLAWT // smlaw<y><c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 1 1 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
+ case thumb2_smlaw: // A8.6.171 SMLAWB, SMLAWT
+ // smlaw<y><c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = mnemonic + getBorT(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode) + ',' + getR_12(opcode);
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode) + ',' + getR_12(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smmla: // A8.6.174 SMMLA // smmla{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
- case thumb2_smmls: // A8.6.175 SMMLS // smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // . . . . . . . . . . . . Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 . . . R_0_4_4 Rm_0_3_0
+ case thumb2_smmla: // A8.6.174 SMMLA
+ // smmla{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
+ case thumb2_smmls: // A8.6.175 SMMLS
+ // smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
instruction = ',' + getR_12(opcode);
// no break!
- case thumb2_smmul: // A8.6.176 SMMUL // smmul{r}<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 R_0_4_4 Rm_0_3_0
+ case thumb2_smmul: // A8.6.176 SMMUL
+ // smmul{r}<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getR(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode)
- + instruction;
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode)
+ + instruction;
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smuad: // A8.6.177 SMUAD // smuad{x}<c> <Rd>,<Rn>,<Rm>
- case thumb2_smusd: // A8.6.181 SMUSD // smusd{x}<c> <Rd>,<Rn>,<Rm>
- // . . . . . . . . . . . . Rn_1_3_0 . . . . Rd_0_11_8 . . . M_0_4_4 Rm_0_3_0
+ case thumb2_smuad: // A8.6.177 SMUAD
+ // smuad{x}<c> <Rd>,<Rn>,<Rm>
+ case thumb2_smusd: // A8.6.181 SMUSD
+ // smusd{x}<c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getX(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smul: // A8.6.178 SMULBB, SMULBT, SMULTB, SMULTT
- // smul<x><y><c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 N_0_5_5 M_0_4_4 Rm_0_3_0
+ case thumb2_smul: // A8.6.178 SMULBB, SMULBT, SMULTB, SMULTT
+ // smul<x><y><c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getBorT(opcode, 5) + getBorT(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_smulw: // A8.6.180 SMULWB, SMULWT // smulw<y><c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 0 1 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
+ case thumb2_smulw: // A8.6.180 SMULWB, SMULWT
+ // smulw<y><c> <Rd>,<Rn>,<Rm>
instruction = mnemonic + getBorT(opcode, 4) + TAB + getR_8(opcode)
- + ',' + getR_16(opcode) + ',' + getR_0(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_16(opcode) + ',' + getR_0(opcode);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_srs: // B6.1.10 SRS // srsdb sp{!},#<mode>
- // 1 1 1 0 1 0 0 0 0 0 W_1_5_5 0 (1)(1)(0) (1) (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0) mode_0_4_0
- // srs{ia} sp{!},#<mode>
- // 1 1 1 0 1 0 0 1 1 0 W_1_5_5 0 (1)(1)(0) (1) (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0) mode_0_4_0
- // . . . . . . . . . . W_1_5_5 . (1)(1)(0) (1) (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0) mode_0_4_0
+ case thumb2_srs: // B6.1.10 SRS
+ // srsdb sp{!},#<mode>
+ // srs{ia} sp{!},#<mode>
instruction = mnemonic
- + (isBitEnabled(opcode, 24) /* && isBitEnabled(opcode, 23) */ ? "ia" : "db")
- + "\tsp" + getW(opcode) + ",#" + getHexValue(opcode & 0x1f);
+ + (isBitEnabled(opcode, 24) ? "ia" : "db")
+ + "\tsp" + getW(opcode) + ",#" + getHexValue(opcode & 0x1f);
+ // No PC check: not applicable
break;
- case thumb2_ssat: // A8.6.183 SSAT // ssat<c> <Rd>,#<imm>,<Rn>{,<shift>}
- case thumb2_usat: // A8.6.256 USAT16 // usat16<c> <Rd>,#<imm4>,<Rn>
- // 1 1 1 1 0 (0) 1 1 0 0 sh_1_5_5 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) sat_imm_0_4_0
+ case thumb2_ssat: // A8.6.183 SSAT
+ // ssat<c> <Rd>,#<imm>,<Rn>{,<shift>}
+ case thumb2_usat: // A8.6.256 USAT16
+ // usat16<c> <Rd>,#<imm4>,<Rn>
offset = (opcode & 0x1f) + 1 - getBit(opcode, 23);
instruction = mnemonic + TAB + getR_8(opcode) + ",#" + offset + ',' + getR_16(opcode)
- + getThumb2ShiftMode(opcode, 20);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + getThumb2ShiftMode(opcode, 20);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_ssat16: // A8.6.184 SSAT16 // ssat16<c> <Rd>,#<imm>,<Rn>
- case thumb2_usat16: // A8.6.256 USAT16 // usat16<c> <Rd>,#<imm4>,<Rn>
+ case thumb2_ssat16: // A8.6.184 SSAT16
+ // ssat16<c> <Rd>,#<imm>,<Rn>
+ case thumb2_usat16: // A8.6.256 USAT16
+ // usat16<c> <Rd>,#<imm4>,<Rn>
// . . . . . (0) . . . . . . Rn_1_3_0 . . . . Rd_0_11_8 . . (0)(0) sat_imm_0_3_0
offset = (opcode & 0xf) + 1 - getBit(opcode, 23);
instruction = mnemonic + TAB + getR_8(opcode) + ",#" + offset + ',' + getR_16(opcode);
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_stm: // A8.6.189 STM / STMIA / STMEA // stm<c>.w <Rn>{!},<registers>
- case thumb2_stmdb: // A8.6.191 STMDB / STMFD // stmdb<c> <Rn>{!},<registers>
- // . . . . . . . . . . W_1_5_5 . Rn_1_3_0 (0) M_0_14_14 (0) register_list_0_12_0
+ case thumb2_stm: // A8.6.189 STM / STMIA / STMEA
+ // stm<c>.w <Rn>{!},<registers>
+ case thumb2_stmdb: // A8.6.191 STMDB / STMFD
+ // stmdb<c> <Rn>{!},<registers>
instruction = mnemonic + TAB + getR_16(opcode) + getW(opcode)
- + ',' + getRegList(opcode);
- // No pc check: PC is not eligible for writeback
+ + ',' + getRegList(opcode);
+ // No PC check: PC is not eligible for writeback
break;
- case thumb2_strex: // A8.6.202 STREX // strex<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
- // 1 1 1 0 1 0 0 0 0 1 0 0 Rn_1_3_0 Rt_0_15_12 Rd_0_11_8 imm8_0_7_0
+ case thumb2_strex: // A8.6.202 STREX
+ // strex<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
offset = opcode & 0xff;
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_12(opcode) + ",[" + getR_16(opcode);
if (offset != 0)
instruction += ",#" + getHexValue(offset << 2);
instruction += ']';
- // No pc check: PC at Rd is UNPREDICTABLE
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_strexx: // A8.6.203 STREXB // strexb<c> <Rd>,<Rt>,[<Rn>]
- // A8.6.205 STREXH // strexh<c> <Rd>,<Rt>,[<Rn>]
- // A8.6.204 STREXD // strexd<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
- // . . . . . . . . . . . . Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) . . . . Rd_0_3_0
+ case thumb2_strexx: // A8.6.203 STREXB
+ // strexb<c> <Rd>,<Rt>,[<Rn>]
+ // A8.6.204 STREXD
+ // strexd<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
+ // A8.6.205 STREXH
+ // strexh<c> <Rd>,<Rt>,[<Rn>]
if (isBitEnabled(opcode, 5)) {
mnemonic += 'd';
instruction = "," + getR_8(opcode);
@@ -3799,893 +3992,963 @@
mnemonic += isBitEnabled(opcode, 4) ? 'h' : 'b';
}
instruction = mnemonic + TAB + getR_0(opcode) + ',' + getR_12(opcode)
- + instruction + ",[" + getR_16(opcode) + ']';
- // No pc check: PC at Rt is UNPREDICTABLE
+ + instruction + ",[" + getR_16(opcode) + ']';
+ // No PC check: PC at Rt is UNPREDICTABLE
break;
- case thumb2_subs: // B6.1.13 SUBS PC, LR and related instructions
- // subs pc,lr,#<imm8> Outside or last in IT block
- // 1 1 1 1 0 0 1 1 1 1 0 1 (1)(1)(1) (0) 1 0 (0) 0 (1)(1)(1)(1) imm8_0_7_0
+ case thumb2_subs: // B6.1.13 SUBS PC, LR and related instructions
+ // subs pc,lr,#<imm8> Outside or last in IT block
instruction = mnemonic + "\tpc,lr,#" + getHexValue(opcode & 0xff);
setDefaultPCJumpProperties(true);
break;
- case thumb2_sxtab: // A8.6.220 SXTAB // sxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- case thumb2_sxtab16: // A8.6.221 SXTAB16 // sxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- case thumb2_sxtah: // A8.6.222 SXTAH // sxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- case thumb2_uxtab: // A8.6.260 UXTAB // uxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- case thumb2_uxtab16: // A8.6.261 UXTAB16 // uxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- case thumb2_uxtah: // A8.6.262 UXTAH // uxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // . . . . . . . . . . . . Rn_1_3_0 . . . . Rd_0_11_8 . (0) rotate_0_5_4 Rm_0_3_0
+ case thumb2_sxtab: // A8.6.220 SXTAB
+ // sxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ case thumb2_sxtab16: // A8.6.221 SXTAB16
+ // sxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ case thumb2_sxtah: // A8.6.222 SXTAH
+ // sxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ case thumb2_uxtab: // A8.6.260 UXTAB
+ // uxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ case thumb2_uxtab16: // A8.6.261 UXTAB16
+ // uxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ case thumb2_uxtah: // A8.6.262 UXTAH
+ // uxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_16(opcode)
- + ',' + getR_0(opcode) + getRotationOperand(opcode, 4);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + ',' + getR_0(opcode) + getRotationOperand(opcode, 4);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_sxtb: // A8.6.223 SXTB // sxtb<c>.w <Rd>,<Rm>{,<rotation>}
- case thumb2_sxtb16: // A8.6.224 SXTB16 // sxtb16<c> <Rd>,<Rm>{,<rotation>}
- case thumb2_sxth: // A8.6.225 SXTH // sxth<c>.w <Rd>,<Rm>{,<rotation>}
- case thumb2_uxtb: // A8.6.263 UXTB // uxtb<c>.w <Rd>,<Rm>{,<rotation>}
- case thumb2_uxtb16: // A8.6.264 UXTB16 // uxtb16<c> <Rd>,<Rm>{,<rotation>}
- case thumb2_uxth: // A8.6.265 UXTH // uxth<c>.w <Rd>,<Rm>{,<rotation>}
- // . . . . . . . . . . . . . . . . . . . . Rd_0_11_8 . (0) rotate_0_5_4 Rm_0_3_0
+ case thumb2_sxtb: // A8.6.223 SXTB
+ // sxtb<c>.w <Rd>,<Rm>{,<rotation>}
+ case thumb2_sxtb16: // A8.6.224 SXTB16
+ // sxtb16<c> <Rd>,<Rm>{,<rotation>}
+ case thumb2_sxth: // A8.6.225 SXTH
+ // sxth<c>.w <Rd>,<Rm>{,<rotation>}
+ case thumb2_uxtb: // A8.6.263 UXTB
+ // uxtb<c>.w <Rd>,<Rm>{,<rotation>}
+ case thumb2_uxtb16: // A8.6.264 UXTB16
+ // uxtb16<c> <Rd>,<Rm>{,<rotation>}
+ case thumb2_uxth: // A8.6.265 UXTH
+ // uxth<c>.w <Rd>,<Rm>{,<rotation>}
instruction = mnemonic + TAB + getR_8(opcode) + ',' + getR_0(opcode)
- + getRotationOperand(opcode, 4);
- // No pc check: PC at Rd is UNPREDICTABLE
+ + getRotationOperand(opcode, 4);
+ // No PC check: PC at Rd is UNPREDICTABLE
break;
- case thumb2_tb: // A8.6.226 TBB, TBH // tbb<c> [<Rn>,<Rm>] Outside or last in IT block
- // tbh [<Rn>,<Rm>,LSL #1] Outside or last in IT block
- // 1 1 1 0 1 0 0 0 1 1 0 1 Rn_1_3_0 (1) (1)(1)(1)(0)(0)(0)(0) 0 0 0 H_0_4_4 Rm_0_3_0
+ case thumb2_tb: // A8.6.226 TBB, TBH
+ // tbb<c> [<Rn>,<Rm>] Outside or last in IT block
+ // tbh<c> [<Rn>,<Rm>,LSL #1] Outside or last in IT block
mnemonic += isBitEnabled(opcode, 4) ? 'h' : 'b';
instruction = mnemonic + TAB + '[' + getR_16(opcode) + ',' + getR_0(opcode)
- + (isBitEnabled(opcode, 4) ? ",lsl #1" : "") + ']';
+ + (isBitEnabled(opcode, 4) ? ",lsl #1" : "") + ']';
setDefaultPCJumpProperties(false);
break;
-
-
-
-
-
// VFP instructions
- case thumb2_vhadd_vhsub:
- // vhadd<c> <Qd>, <Qn>, <Qm>
- // vhadd<c> <Dd>, <Dn>, <Dm>
- // vhsub<c> <Qd>, <Qn>, <Qm>
- // vhsub<c> <Dd>, <Dn>, <Dm>
+ case thumb2_vhadd_vhsub: // A8.6.306 VHADD, VHSUB
+ // vhadd<c> <Qd>, <Qn>, <Qm>
+ // vhadd<c> <Dd>, <Dn>, <Dm>
+ // vhsub<c> <Qd>, <Qn>, <Qm>
+ // vhsub<c> <Dd>, <Dn>, <Dm>
mnemonic += isBitEnabled(opcode, 9) ? "sub" : "add";
- case thumb2_vaba:
- // vaba<c>.<dt> <Qd>, <Qn>, <Qm>
- // vaba<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vabd__int:
- // vabd<c>.<dt> <Qd>, <Qn>, <Qm>
- // vabd<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vcge__reg_int:
- // vceq<c>.<dt> <Qd>, <Qn>, <Qm>
- // vceq<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vcgt__reg_int:
- // vcgt<c>.<dt> <Qd>, <Qn>, <Qm>
- // vcgt<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vqadd:
- // vqadd<c>.<dt> <Qd>,<Qn>,<Qm>
- // vqadd<c>.<dt> <Dd>,<Dn>,<Dm>
- case thumb2_vrhadd:
- // vrhadd<c> <Qd>, <Qn>, <Qm>
- // vrhadd<c> <Dd>, <Dn>, <Dm>
- case thumb2_vqsub: // A8.6.369 VQSUB
- // vqsub<c>.<type><size> <Qd>,<Qn>,<Qm>
- // vqsub<c>.<type><size> <Dd>,<Dn>,<Dm>
+ case thumb2_vaba: // A8.6.266 VABA, VABAL
+ // vaba<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vaba<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vabd__int: // A8.6.267 VABD, VABDL (integer)
+ // vabd<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vabd<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vcge__reg_int: // A8.6.282 VCGE (register)
+ // vceq<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vceq<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vcgt__reg_int: // A8.6.284 VCGT (register)
+ // vcgt<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vcgt<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vqadd: // A8.6.357 VQADD
+ // vqadd<c>.<dt> <Qd>,<Qn>,<Qm>
+ // vqadd<c>.<dt> <Dd>,<Dn>,<Dm>
+ case thumb2_vrhadd: // A8.6.374 VRHADD
+ // vrhadd<c> <Qd>, <Qn>, <Qm>
+ // vrhadd<c> <Dd>, <Dn>, <Dm>
+ case thumb2_vqsub: // A8.6.369 VQSUB
+ // vqsub<c>.<type><size> <Qd>,<Qn>,<Qm>
+ // vqsub<c>.<type><size> <Dd>,<Dn>,<Dm>
instruction = mnemonic + getVFPSorUDataType(opcode, 28) + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vqdml__vec:
- // vqd<op><c>.<dt> <Qd>,<Dn>,<Dm>
+ case thumb2_vqdml__vec: // A8.6.358 VQDMLAL, VQDMLSL
+ // vqd<op><c>.<dt> <Qd>,<Dn>,<Dm>
mnemonic += isBitEnabled(opcode, 9) ? "sl" : "al";
// can use getVFPSorUDataType() because bit 24 is always '0'
// no break!
- case thumb2_vabal:
- // vabal<c>.<dt> <Qd>, <Dn>, <Dm>
- case thumb2_vabdl:
- // vabdl<c>.<dt> <Qd>, <Dn>, <Dm>
- case thumb2_vqdmull__vec:
- // vqdmull<c>.<dt> <Qd>,<Dn>,<Dm>
+ case thumb2_vabal: // A8.6.266 VABA, VABAL
+ // vabal<c>.<dt> <Qd>, <Dn>, <Dm>
+ case thumb2_vabdl: // A8.6.267 VABD, VABDL (integer)
+ // vabdl<c>.<dt> <Qd>, <Dn>, <Dm>
+ case thumb2_vqdmull__vec: // A8.6.360 VQDMULL
+ // vqdmull<c>.<dt> <Qd>,<Dn>,<Dm>
instruction = mnemonic + getVFPSorUDataType(opcode, 28)
- + TAB + getVFPQdDnDmRegs(opcode);
- // No pc check: not applicable
+ + TAB + getVFPQdDnDmRegs(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vabd__f32:
- // vabd<c>.f32 <Qd>, <Qn>, <Qm>
- // vabd<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vadd__f32:
- // vadd<c>.f32 <Qd>, <Qn>, <Qm>
- // vadd<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vceq__reg_f32:
- // vceq<c>.f32 <Qd>, <Qn>, <Qm>
- // vceq<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vcge__reg_f32:
- // vcge<c>.f32 <Qd>, <Qn>, <Qm>
- // vcge<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vcgt__reg_f32:
- // vcgt<c>.f32 <Qd>, <Qn>, <Qm>
- // vcgt<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vmul__f32:
- // vmul<c>.f32 <Qd>, <Qn>, <Qm>
- // vmul<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vpadd__f32:
- // vpadd<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vrecps:
- // vrecps<c>.f32 <Qd>, <Qn>, <Qm>
- // vrecps<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vrsqrts:
- // vrsqrts<c>.f32 <Qd>, <Qn>, <Qm>
- // vrsqrts<c>.f32 <Dd>, <Dn>, <Dm>
- case thumb2_vsub__f32:
- // vsub<c>.f32 <Qd>, <Qn>, <Qm>
- // vsub<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vabd__f32: // A8.6.268 VABD (floating-point)
+ // vabd<c>.f32 <Qd>, <Qn>, <Qm>
+ // vabd<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vadd__f32: // A8.6.272 VADD (floating-point)
+ // vadd<c>.f32 <Qd>, <Qn>, <Qm>
+ // vadd<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vceq__reg_f32: // A8.6.280 VCEQ (register)
+ // vceq<c>.f32 <Qd>, <Qn>, <Qm>
+ // vceq<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vcge__reg_f32: // A8.6.282 VCGE (register)
+ // vcge<c>.f32 <Qd>, <Qn>, <Qm>
+ // vcge<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vcgt__reg_f32: // A8.6.284 VCGT (register)
+ // vcgt<c>.f32 <Qd>, <Qn>, <Qm>
+ // vcgt<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vmul__f32: // A8.6.338 VMUL (floating-point)
+ // vmul<c>.f32 <Qd>, <Qn>, <Qm>
+ // vmul<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vpadd__f32: // A8.6.350 VPADD (floating-point)
+ // vpadd<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vrecps: // A8.6.372 VRECPS
+ // vrecps<c>.f32 <Qd>, <Qn>, <Qm>
+ // vrecps<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vrsqrts: // A8.6.379 VRSQRTS
+ // vrsqrts<c>.f32 <Qd>, <Qn>, <Qm>
+ // vrsqrts<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vsub__f32: // A8.6.402 VSUB (floating-point)
+ // vsub<c>.f32 <Qd>, <Qn>, <Qm>
+ // vsub<c>.f32 <Dd>, <Dn>, <Dm>
instruction = mnemonic + ".f32\t" + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vabs:
- // vabs<c>.<dt> <Qd>, <Qm>
- // vabs<c>.<dt> <Dd>, <Dm>
- case thumb2_vneg:
- // vneg<c>.<dt> <Qd>, <Qm>
- // vneg<c>.<dt> <Dd>, <Dm>
+ case thumb2_vabs: // A8.6.269 VABS
+ // vabs<c>.<dt> <Qd>, <Qm>
+ // vabs<c>.<dt> <Dd>, <Dm>
+ case thumb2_vneg: // A8.6.342 VNEG
+ // vneg<c>.<dt> <Qd>, <Qm>
+ // vneg<c>.<dt> <Dd>, <Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 10, 4); // chose bit 11 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vabs__f:
- // vabs<c>.f64 <Dd>, <Dm>
- // vabs<c>.f32 <Sd>, <Sm>
- case thumb2_vmov__reg_f:
- // vmov<c>.f64 <Dd>, <Dm>
- // vmov<c>.f32 <Sd>, <Sm>
- case thumb2_vneg__f:
- // vneg<c>.f64 <Dd>, <Dm>
- // vneg<c>.f32 <Sd>, <Sm>
- case thumb2_vsqrt:
- // vsqrt<c>.f64 <Dd>, <Dm>
- // vsqrt<c>.f32 <Sd>, <Sm>
+ case thumb2_vabs__f: // A8.6.269 VABS
+ // vabs<c>.f64 <Dd>, <Dm>
+ // vabs<c>.f32 <Sd>, <Sm>
+ case thumb2_vmov__reg_f: // A8.6.327 VMOV (register)
+ // vmov<c>.f64 <Dd>, <Dm>
+ // vmov<c>.f32 <Sd>, <Sm>
+ case thumb2_vneg__f: // A8.6.342 VNEG
+ // vneg<c>.f64 <Dd>, <Dm>
+ // vneg<c>.f32 <Sd>, <Sm>
+ case thumb2_vsqrt: // A8.6.388 VSQRT
+ // vsqrt<c>.f64 <Dd>, <Dm>
+ // vsqrt<c>.f32 <Sd>, <Sm>
instruction = mnemonic + getVFPSzF64F32dmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vacge_vacgt:
- // vacge<c>.f32 <Qd>, <Qn>, <Qm>
- // vacge<c>.f32 <Dd>, <Dn>, <Dm>
- // vacgt<c>.f32 <Qd>, <Qn>, <Qm>
- // vacgt<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vacge_vacgt: // A8.6.270 VACGE, VACGT, VACLE, VACLT
+ // vacge<c>.f32 <Qd>, <Qn>, <Qm>
+ // vacge<c>.f32 <Dd>, <Dn>, <Dm>
+ // vacgt<c>.f32 <Qd>, <Qn>, <Qm>
+ // vacgt<c>.f32 <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFP_vacge_vacgt(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vadd__int:
- // vadd<c>.<dt> <Qd>, <Qn>, <Qm>
- // vadd<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vceq__reg_int:
- // vceq<c>.<dt> <Qd>, <Qn>, <Qm>
- // vceq<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vpadd__int:
- // vpadd<c>.<dt> <Dd>, <Dn>, <Dm>
- case thumb2_vsub__int:
- // vsub<c>.<dt> <Qd>, <Qn>, <Qm>
- // vsub<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vadd__int: // A8.6.271 VADD (integer)
+ // vadd<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vadd<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vceq__reg_int: // A8.6.280 VCEQ (register)
+ // vceq<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vceq<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vpadd__int: // A8.6.349 VPADD (integer)
+ // vpadd<c>.<dt> <Dd>, <Dn>, <Dm>
+ case thumb2_vsub__int: // A8.6.401 VSUB (integer)
+ // vsub<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vsub<c>.<dt> <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFPIDataTypeQorDdnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vnml:
- // vnmla<c>.f64 <Dd>, <Dn>, <Dm>
- // vnmla<c>.f32 <Sd>, <Sn>, <Sm>
- // vnmls<c>.f64 <Dd>, <Dn>, <Dm>
- // vnmls<c>.f32 <Sd>, <Sn>, <Sm>
+ case thumb2_vnml: // A8.6.343 VNMLA, VNMLS, VNMUL
+ // vnmla<c>.f64 <Dd>, <Dn>, <Dm>
+ // vnmla<c>.f32 <Sd>, <Sn>, <Sm>
+ // vnmls<c>.f64 <Dd>, <Dn>, <Dm>
+ // vnmls<c>.f32 <Sd>, <Sn>, <Sm>
mnemonic += isBitEnabled(opcode, 6) ? 'a' : 's';
// no break!
- case thumb2_vadd__fp_f:
- // vadd<c>.f64 <Dd>, <Dn>, <Dm>
- // vadd<c>.f32 <Sd>, <Sn>, <Sm>
- case thumb2_vdiv:
- // vdiv<c>.f64 <Dd>, <Dn>, <Dm>
- // vdiv<c>.f32 <Sd>, <Sn>, <Sm>
- case thumb2_vmul__fp_2:
- // vmul<c>.f64 <Dd>, <Dn>, <Dm>
- // vmul<c>.f32 <Sd>, <Sn>, <Sm>
- case thumb2_vnmul:
- // vnmul<c>.f64 <Dd>, <Dn>, <Dm>
- // vnmul<c>.f32 <Sd>, <Sn>, <Sm>
- case thumb2_vsub__fp_f:
- // vsub<c>.f64 <Dd>, <Dn>, <Dm>
- // vsub<c>.f32 <Sd>, <Sn>, <Sm>
+ case thumb2_vadd__fp_f: // A8.6.272 VADD (floating-point)
+ // vadd<c>.f64 <Dd>, <Dn>, <Dm>
+ // vadd<c>.f32 <Sd>, <Sn>, <Sm>
+ case thumb2_vdiv: // A8.6.301 VDIV
+ // vdiv<c>.f64 <Dd>, <Dn>, <Dm>
+ // vdiv<c>.f32 <Sd>, <Sn>, <Sm>
+ case thumb2_vmul__fp_2: // A8.6.338 VMUL (floating-point)
+ // vmul<c>.f64 <Dd>, <Dn>, <Dm>
+ // vmul<c>.f32 <Sd>, <Sn>, <Sm>
+ case thumb2_vnmul: // A8.6.343 VNMLA, VNMLS, VNMUL
+ // vnmul<c>.f64 <Dd>, <Dn>, <Dm>
+ // vnmul<c>.f32 <Sd>, <Sn>, <Sm>
+ case thumb2_vsub__fp_f: // A8.6.402 VSUB (floating-point)
+ // vsub<c>.f64 <Dd>, <Dn>, <Dm>
+ // vsub<c>.f32 <Sd>, <Sn>, <Sm>
instruction = mnemonic + getVFPSzF64F32dnmOperands(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vaddhn:
- // vaddhn<c>.<dt> <Dd>, <Qn>, <Qm>
- case thumb2_vraddhn:
- // vraddhn<c>.<dt> <Dd>, <Qn>, <Qm>
- case thumb2_vrsubhn:
- // vrsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
- case thumb2_vsubhn:
- // vsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
+ case thumb2_vaddhn: // A8.6.273 VADDHN
+ // vaddhn<c>.<dt> <Dd>, <Qn>, <Qm>
+ case thumb2_vraddhn: // A8.6.370 VRADDHN
+ // vraddhn<c>.<dt> <Dd>, <Qn>, <Qm>
+ case thumb2_vrsubhn: // A8.6.381 VRSUBHN
+ // vrsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
+ case thumb2_vsubhn: // A8.6.403 VSUBHN
+ // vsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
instruction = mnemonic + getVFPIDataType2DdQnDmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vaddl_vaddw:
- // vaddl<c>.<dt> <Qd>, <Dn>, <Dm>
- // vaddw<c>.<dt> <Qd>, <Qn>, <Dm>
- case thumb2_vsubl_vsubw:
- // vsubl<c>.<dt> <Qd>, <Dn>, <Dm>
- // vsubw<c>.<dt> {<Qd>,} <Qn>, <Dm>
+ case thumb2_vaddl_vaddw: // A8.6.274 VADDL, VADDW
+ // vaddl<c>.<dt> <Qd>, <Dn>, <Dm>
+ // vaddw<c>.<dt> <Qd>, <Qn>, <Dm>
+ case thumb2_vsubl_vsubw: // A8.6.404 VSUBL, VSUBW
+ // vsubl<c>.<dt> <Qd>, <Dn>, <Dm>
+ // vsubw<c>.<dt> {<Qd>,} <Qn>, <Dm>
instruction = mnemonic + getVFP_vXXXl_vXXXw(opcode, 28);
+ // No PC check: not applicable
break;
- case thumb2_vbif_vbit_vbsl_veor:
- // vbif<c> <Qd>, <Qn>, <Qm>
- // vbif<c> <Dd>, <Dn>, <Dm>
- // vbit<c> <Qd>, <Qn>, <Qm>
- // vbit<c> <Dd>, <Dn>, <Dm>
- // vbsl<c> <Qd>, <Qn>, <Qm>
- // vbsl<c> <Dd>, <Dn>, <Dm>
- // veor<c> <Qd>, <Qn>, <Qm>
- // veor<c> <Dd>, <Dn>, <Dm>
+ case thumb2_vbif_vbit_vbsl_veor: // A8.6.279 VBIF, VBIT, VBSL
+ // vbif<c> <Qd>, <Qn>, <Qm>
+ // vbif<c> <Dd>, <Dn>, <Dm>
+ // vbit<c> <Qd>, <Qn>, <Qm>
+ // vbit<c> <Dd>, <Dn>, <Dm>
+ // vbsl<c> <Qd>, <Qn>, <Qm>
+ // vbsl<c> <Dd>, <Dn>, <Dm>
+ // veor<c> <Qd>, <Qn>, <Qm>
+ // veor<c> <Dd>, <Dn>, <Dm>
mnemonic = getVFP_vbif_vbit_vbsl_veor_mnemonic(opcode);
// no break!
- case thumb2_vand:
- // vand<c> <Qd>, <Qn>, <Qm>
- // vand<c> <Dd>, <Dn>, <Dm>
- case thumb2_vbic__reg:
- // vbic<c> <Qd>, <Qn>, <Qm>
- // vbic<c> <Dd>, <Dn>, <Dm>
- case thumb2_vorn:
- // vorn<c> <Qd>, <Qn>, <Qm>
- // vorn<c> <Dd>, <Dn>, <Dm>
- case thumb2_vorr__reg:
- // vorr<c> <Qd>, <Qn>, <Qm>
- // vorr<c> <Dd>, <Dn>, <Dm>
+ case thumb2_vand: // A8.6.276 VAND (register)
+ // vand<c> <Qd>, <Qn>, <Qm>
+ // vand<c> <Dd>, <Dn>, <Dm>
+ case thumb2_vbic__reg: // A8.6.278 VBIC (register)
+ // vbic<c> <Qd>, <Qn>, <Qm>
+ // vbic<c> <Dd>, <Dn>, <Dm>
+ case thumb2_vorn: // A8.6.345 VORN (register)
+ // vorn<c> <Qd>, <Qn>, <Qm>
+ // vorn<c> <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vmov_vbitwise:
- // vbic<c>.<dt> <Qd>, #<imm>
- // vbic<c>.<dt> <Dd>, #<imm>
- // vmov<c>.<dt> <Qd>, #<imm>
- // vmov<c>.<dt> <Dd>, #<imm>
- // vmvn<c>.<dt> <Qd>, #<imm>
- // vmvn<c>.<dt> <Dd>, #<imm>
- // vorr<c>.<dt> <Qd>, #<imm>
- // vorr<c>.<dt> <Dd>, #<imm>
+ case thumb2_vmov_vorr: // A8.6.327 VMOV (register)
+ // vmov<c> <Qd>, <Qn>, <Qm>
+ // vmov<c> <Dd>, <Dn>, <Dm>
+ // A8.6.347 VORR (register)
+ // vorr<c> <Qd>, <Qn>, <Qm>
+ // vorr<c> <Dd>, <Dn>, <Dm>
+ // mnemonic is "vmov" by default
+ if (getBit(opcode, 7) == getBit(opcode, 5) &&
+ (opcode & 0xf) == (opcode >> 16 & 0xf)) {
+ instruction = mnemonic + TAB + getVFPQorDdmRegs(opcode);
+ } else {
+ instruction = "vorr" + getVFPQorDdnmRegs(opcode);
+ }
+ // No PC check: not applicable
+ break;
+
+ case thumb2_vmov_vbitwise: // A8.6.277 VBIC (immediate)
+ // vbic<c>.<dt> <Qd>, #<imm>
+ // vbic<c>.<dt> <Dd>, #<imm>
+ // A8.6.326 VMOV (immediate)
+ // vmov<c>.<dt> <Qd>, #<imm>
+ // vmov<c>.<dt> <Dd>, #<imm>
+ // A8.6.340 VMVN (immediate)
+ // vmvn<c>.<dt> <Qd>, #<imm>
+ // vmvn<c>.<dt> <Dd>, #<imm>
+ // A8.6.346 VORR (immediate)
+ // vorr<c>.<dt> <Qd>, #<imm>
+ // vorr<c>.<dt> <Dd>, #<imm>
instruction = getVFP_vmov_vbitwise_instruction(opcode, 28);
+ // No PC check: not applicable
break;
- case thumb2_vceq__imm0: // A8.6.281 VCEQ (immediate #0)
- // vceq<c>.<dt> <Qd>, <Qm>, #0
- // vceq<c>.<dt> <Dd>, <Dm>, #0
- // vceq<c>.<dt> <Qd>, <Qm>, #0
- // vceq<c>.<dt> <Dd>, <Dm>, #0
+ case thumb2_vceq__imm0: // A8.6.281 VCEQ (immediate #0)
+ // vceq<c>.<dt> <Qd>, <Qm>, #0
+ // vceq<c>.<dt> <Dd>, <Dm>, #0
+ // vceq<c>.<dt> <Qd>, <Qm>, #0
+ // vceq<c>.<dt> <Dd>, <Dm>, #0
instruction = mnemonic + getVFPIorFQorDdmOperands(opcode, 10) + ",#0";
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcge__imm0:
- // vcge<c>.<dt> <Qd>, <Qm>, #0
- // vcge<c>.<dt> <Dd>, <Dm>, #0
- case thumb2_vcgt__imm0:
- // vcgt<c>.<dt> <Qd>, <Qm>, #0
- // vcgt<c>.<dt> <Dd>, <Dm>, #0
- case thumb2_vcle:
- // vcle<c>.<dt> <Qd>, <Qm>, #0
- // vcle<c>.<dt> <Dd>, <Dm>, #0
- case thumb2_vclt:
- // vclt<c>.<dt> <Qd>, <Qm>, #0
- // vclt<c>.<dt> <Dd>, <Dm>, #0
+ case thumb2_vcge__imm0: // A8.6.283 VCGE (immediate #0)
+ // vcge<c>.<dt> <Qd>, <Qm>, #0
+ // vcge<c>.<dt> <Dd>, <Dm>, #0
+ case thumb2_vcgt__imm0: // A8.6.285 VCGT (immediate #0)
+ // vcgt<c>.<dt> <Qd>, <Qm>, #0
+ // vcgt<c>.<dt> <Dd>, <Dm>, #0
+ case thumb2_vcle: // A8.6.287 VCLE (immediate #0)
+ // vcle<c>.<dt> <Qd>, <Qm>, #0
+ // vcle<c>.<dt> <Dd>, <Dm>, #0
+ case thumb2_vclt: // A8.6.290 VCLT (immediate #0)
+ // vclt<c>.<dt> <Qd>, <Qm>, #0
+ // vclt<c>.<dt> <Dd>, <Dm>, #0
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 10, 11) + ",#0"; // chose bit 11 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcls:
- // vcls<c>.<dt> <Qd>, <Qm>
- // vcls<c>.<dt> <Dd>, <Dm>
- case thumb2_vqabs:
- // vqabs<c>.<dt> <Qd>,<Qm>
- // vqabs<c>.<dt> <Dd>,<Dm>
- case thumb2_vqneg:
- // vqneg<c>.<dt> <Qd>,<Qm>
- // vqneg<c>.<dt> <Dd>,<Dm>
+ case thumb2_vcls: // A8.6.288 VCLS
+ // vcls<c>.<dt> <Qd>, <Qm>
+ // vcls<c>.<dt> <Dd>, <Dm>
+ case thumb2_vqabs: // A8.6.356 VQABS
+ // vqabs<c>.<dt> <Qd>,<Qm>
+ // vqabs<c>.<dt> <Dd>,<Dm>
+ case thumb2_vqneg: // A8.6.362 VQNEG
+ // vqneg<c>.<dt> <Qd>,<Qm>
+ // vqneg<c>.<dt> <Dd>,<Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 4, 11); // chose bit 11 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vclz:
- // vclz<c>.<dt> <Qd>, <Qm>
- // vclz<c>.<dt> <Dd>, <Dm>
- instruction = mnemonic + getVFPIorFQorDdmOperands(opcode, 11); // chose bit 11 because it is 0
- // No pc check: not applicable
+ case thumb2_vclz: // A8.6.291 VCLZ
+ // vclz<c>.<dt> <Qd>, <Qm>
+ // vclz<c>.<dt> <Dd>, <Dm>
+ instruction = mnemonic + getVFPIorFQorDdmOperands(opcode, 11); // chose bit 11 because it is 0
+ // No PC check: not applicable
break;
- case thumb2_vcmp__reg:
- // vcmp{e}<c>.f64 <Dd>, <Dm>
- // vcmp{e}<c>.f32 <Sd>, <Sm>
+ case thumb2_vcmp__reg: // A8.6.292 VCMP, VCMPE
+ // vcmp{e}<c>.f64 <Dd>, <Dm>
+ // vcmp{e}<c>.f32 <Sd>, <Sm>
instruction = mnemonic + getE(opcode) + getVFPSzF64F32dmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcmp__to_0:
- // vcmp{e}<c>.f64 <Dd>, #0.0
- // vcmp{e}<c>.f32 <Sd>, #0.0
+ case thumb2_vcmp__to_0: // A8.6.292 VCMP, VCMPE
+ // vcmp{e}<c>.f64 <Dd>, #0.0
+ // vcmp{e}<c>.f32 <Sd>, #0.0
instruction = mnemonic + getE(opcode) + getVFP_vcmpTo0Operands(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vcnt:
- // vcnt<c>.8 <Qd>, <Qm>
- // vcnt<c>.8 <Dd>, <Dm>
+ case thumb2_vcnt: // A8.6.293 VCNT
+ // vcnt<c>.8 <Qd>, <Qm>
+ // vcnt<c>.8 <Dd>, <Dm>
mnemonic += ".8";
- case thumb2_vmvn:
- // vmvn<c> <Qd>, <Qm>
- // vmvn<c> <Dd>, <Dm>
- case thumb2_vmov__reg:
- // vmov<c> <Qd>, <Qm> vmov<c> <Dd>, <Dm>
- case thumb2_vswp:
- // vswp<c> <Qd>, <Qm>
- // vswp<c> <Dd>, <Dm>
+ case thumb2_vmvn: // A8.6.341 VMVN (register)
+ // vmvn<c> <Qd>, <Qm>
+ // vmvn<c> <Dd>, <Dm>
+ case thumb2_vswp: // A8.6.405 VSWP
+ // vswp<c> <Qd>, <Qm>
+ // vswp<c> <Dd>, <Dm>
instruction = mnemonic + getVFPQorDdmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__fp_i_vec:
- // vcvt<c>.<Td>.<Tm> <Qd>, <Qm>
- // vcvt<c>.<Td>.<Tm> <Dd>, <Dm>
+ case thumb2_vcvt__fp_i_vec: // A8.6.294 VCVT (between floating-point and integer, Advanced SIMD)
+ // vcvt<c>.<Td>.<Tm> <Qd>, <Qm>
+ // vcvt<c>.<Td>.<Tm> <Dd>, <Dm>
instruction = mnemonic + getVFP_vcvtFpIVecOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__fp_i_reg:
- // vcvt{r}<c>.s32.f64 <Sd>, <Dm>
- // vcvt{r}<c>.s32.f32 <Sd>, <Sm>
- // vcvt{r}<c>.u32.f64 <Sd>, <Dm>
- // vcvt{r}<c>.u32.f32 <Sd>, <Sm>
- // vcvt<c>.f64.<Tm> <Dd>, <Sm>
- // vcvt<c>.f32.<Tm> <Sd>, <Sm>
+ case thumb2_vcvt__fp_i_reg: // A8.6.295 VCVT, VCVTR (between floating-point and integer, VFP)
+ // vcvt{r}<c>.s32.f64 <Sd>, <Dm>
+ // vcvt{r}<c>.s32.f32 <Sd>, <Sm>
+ // vcvt{r}<c>.u32.f64 <Sd>, <Dm>
+ // vcvt{r}<c>.u32.f32 <Sd>, <Sm>
+ // vcvt<c>.f64.<Tm> <Dd>, <Sm>
+ // vcvt<c>.f32.<Tm> <Sd>, <Sm>
if (isBitEnabled(opcode, 18) && !isBitEnabled(opcode, 7))
mnemonic += "r";
instruction = mnemonic + getVFP_vcvtFpIRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__fp_fix_vec:
- // vcvt<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits>
- // vcvt<c>.<Td>.<Tm> <Dd>, <Dm>, #<fbits>
+ case thumb2_vcvt__fp_fix_vec: // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
+ // vcvt<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits>
+ // vcvt<c>.<Td>.<Tm> <Dd>, <Dm>, #<fbits>
instruction = mnemonic + getVFP_vcvtFpFixVecOperands(opcode, 28);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__fp_fix_reg:
- // vcvt<c>.<Td>.f64 <Dd>, <Dd>, #<fbits>
- // vcvt<c>.<Td>.f32 <Sd>, <Sd>, #<fbits>
- // vcvt<c>.f64.<Td> <Dd>, <Dd>, #<fbits>
- // vcvt<c>.f32.<Td> <Sd>, <Sd>, #<fbits>
+ case thumb2_vcvt__fp_fix_reg: // A8.6.297 VCVT (between floating-point and fixed-point, VFP)
+ // vcvt<c>.<Td>.f64 <Dd>, <Dd>, #<fbits>
+ // vcvt<c>.<Td>.f32 <Sd>, <Sd>, #<fbits>
+ // vcvt<c>.f64.<Td> <Dd>, <Dd>, #<fbits>
+ // vcvt<c>.f32.<Td> <Sd>, <Sd>, #<fbits>
instruction = mnemonic + getVFP_vcvtFpFixRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__dp_sp:
- // vcvt<c>.f64.f32 <Dd>, <Sm>
- // vcvt<c>.f32.f64 <Sd>, <Dm>
+ case thumb2_vcvt__dp_sp: // A8.6.298 VCVT (between double-precision and single-precision)
+ // vcvt<c>.f64.f32 <Dd>, <Sm>
+ // vcvt<c>.f32.f64 <Sd>, <Dm>
instruction = mnemonic + getVFP_vcvtDpSpOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__hp_sp_vec:
- // vcvt<c>.f32.f16 <Qd>, <Dm>
- // vcvt<c>.f16.f32 <Dd>, <Qm>
+ case thumb2_vcvt__hp_sp_vec:// A8.6.299 VCVT (between half-precision and single-precision, Advanced SIMD)
+ // vcvt<c>.f32.f16 <Qd>, <Dm>
+ // vcvt<c>.f16.f32 <Dd>, <Qm>
instruction = mnemonic + getVFP_vcvtHpSpVecOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vcvt__hp_sp_reg:
- // vcvt<y><c>.f32.f16 <Sd>, <Sm>
- // vcvt<y><c>.f16.f32 <Sd>, <Sm>
+ case thumb2_vcvt__hp_sp_reg:// A8.6.300 VCVTB, VCVTT (between half-precision and single-precision, VFP)
+ // vcvt<y><c>.f32.f16 <Sd>, <Sm>
+ // vcvt<y><c>.f16.f32 <Sd>, <Sm>
mnemonic += (isBitEnabled(opcode, 7) ? "t" : "b");
instruction = mnemonic + getVFP_vcvtHpSpRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vdup__scalar:
- // vdup<c>.<size> <Qd>, <Dm[x]>
- // vdup<c>.<size> <Dd>, <Dm[x]>
+ case thumb2_vdup__scalar: // A8.6.302 VDUP (scalar)
+ // vdup<c>.<size> <Qd>, <Dm[x]>
+ // vdup<c>.<size> <Dd>, <Dm[x]>
instruction = mnemonic + getVFP_vdupScalarOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vdup__reg:
- // vdup<c>.<size> <Qd>, <Rt>
- // vdup<c>.<size> <Dd>, <Rt>
+ case thumb2_vdup__reg: // A8.6.303 VDUP (ARM core register)
+ // vdup<c>.<size> <Qd>, <Rt>
+ // vdup<c>.<size> <Dd>, <Rt>
instruction = mnemonic + getVFP_vdupRegOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vext:
- // vext<c>.8 <Qd>, <Qn>, <Qm>, #<imm>
- // vext<c>.8 <Dd>, <Dn>, <Dm>, #<imm>
+ case thumb2_vext: // A8.6.305 VEXT
+ // vext<c>.8 <Qd>, <Qn>, <Qm>, #<imm>
+ // vext<c>.8 <Dd>, <Dn>, <Dm>, #<imm>
instruction = mnemonic + getVFPQorDdnmRegs(opcode)
- + ",#" + (opcode >> 8 & 0xf);
- // No pc check: not applicable
+ + ",#" + (opcode >> 8 & 0xf);
+ // No PC check: not applicable
break;
- case thumb2_vld__multi:
- // vld1<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // vld2<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // vld3<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vld3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // vld4<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vld4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- case thumb2_vst__multi:
- // vst1<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // vst2<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vst2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // vst3<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vst3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // vst4<c>.<size> <list>, [<Rn>{@<align>}]{!}
- // vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ case thumb2_vld__multi: // A8.6.307 VLD1 (multiple single elements)
+ // vld1<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ // A8.6.310 VLD2 (multiple 2-element structures)
+ // vld2<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ // A8.6.313 VLD3 (multiple 3-element structures)
+ // vld3<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vld3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ // A8.6.316 VLD4 (multiple 4-element structures)
+ // vld4<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vld4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ case thumb2_vst__multi: // A8.6.391 VST1 (multiple single elements)
+ // vst1<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ // A8.6.393 VST2 (multiple 2-element structures)
+ // vst2<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vst2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ // A8.6.395 VST3 (multiple 3-element structures)
+ // vst3<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vst3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
+ // A8.6.397 VST4 (multiple 4-element structures)
+ // vst4<c>.<size> <list>, [<Rn>{@<align>}]{!}
+ // vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
instruction = mnemonic + getVFP_vXX_multi(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vld__xlane:
- // vld1<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld1<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld1<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld1<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld2<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld2<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld2<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld2<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld3<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld3<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld3<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld3<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vld4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vld4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- case thumb2_vst__xlane:
- // vst1<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vst1<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vst2<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vst2<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vst3<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vst3<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
- // vst4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
- // vst4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ case thumb2_vld__xlane: // A8.6.308 VLD1 (single element to one lane)
+ // vld1<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld1<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.309 VLD1 (single element to all lanes)
+ // vld1<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld1<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.311 VLD2 (single 2-element structure to one lane)
+ // vld2<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld2<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.312 VLD2 (single 2-element structure to all lanes)
+ // vld2<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld2<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.314 VLD3 (single 3-element structure to one lane)
+ // vld3<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld3<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.315 VLD3 (single 3-element structure to all lanes)
+ // vld3<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld3<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.317 VLD4 (single 4-element structure to one lane)
+ // vld4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.318 VLD4 (single 4-element structure to all lanes)
+ // vld4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vld4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ case thumb2_vst__xlane: // A8.6.392 VST1 (single element from one lane)
+ // vst1<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vst1<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.394 VST2 (single 2-element structure from one lane)
+ // vst2<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vst2<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.396 VST3 (single 3-element structure from one lane)
+ // vst3<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vst3<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
+ // A8.6.398 VST4 (single 4-element structure from one lane)
+ // vst4<c>.<size> <list>, [<Rn>{@<align>}}]{!}
+ // vst4<c>.<size> <list>, [<Rn>{@<align>}}], <Rm>
instruction = mnemonic + getVFP_vXX_Xlane(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vldm__64:
+ case thumb2_vldm__64: // A8.6.319 VLDM
// vldm{mode}<c> <Rn>{!},<list> (<list> is consecutive 64-bit registers)
- case thumb2_vldm__32:
+ case thumb2_vldm__32: // A8.6.319 VLDM
// vldm{mode}<c> <Rn>{!},<list> (<list> is consecutive 64-bit registers)
- case thumb2_vstm__64:
+ case thumb2_vstm__64: // A8.6.399 VSTM
// vstm{mode}<c> <Rn>{!},<list> (<list> is consecutive 64-bit registers)
- case thumb2_vstm__32:
+ case thumb2_vstm__32: // A8.6.399 VSTM
// vstm{mode}<c> <Rn>{!},<list> (<list> is consecutive 64-bit registers)
instruction = mnemonic + getVFPIncDec(opcode) + getVFP_vXXm(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vldr__64:
- // vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]
- // vldr<c> <Dd>, <label>
- // vldr<c> <Dd>, [pc,#-0] Special case
- case thumb2_vldr__32:
- // vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]
- // vldr<c> <Sd>, <label>
- // vldr<c> <Sd>, [pc,#-0] Special case
- case thumb2_vstr__64:
- // vstr<c> <Dd>, [<Rn>{,#+/-<imm>}]
- case thumb2_vstr__32:
- // vstr<c> <Sd>, [<Rn>{,#+/-<imm>}]
+ case thumb2_vldr__64: // A8.6.320 VLDR
+ // vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]
+ // vldr<c> <Dd>, <label>
+ // vldr<c> <Dd>, [pc,#-0] Special case
+ case thumb2_vldr__32: // A8.6.320 VLDR
+ // vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]
+ // vldr<c> <Sd>, <label>
+ // vldr<c> <Sd>, [pc,#-0] Special case
+ case thumb2_vstr__64: // A8.6.400 VSTR
+ // vstr<c> <Dd>, [<Rn>{,#+/-<imm>}]
+ case thumb2_vstr__32: // A8.6.400 VSTR
+ // vstr<c> <Sd>, [<Rn>{,#+/-<imm>}]
instruction = mnemonic + getVFP_vXXr(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmax_vmin__int:
- // A8.6.321 VMAX, VMIN (integer)
- // vmax<c>.<dt> <Qd>,<Qn>,<Qm> vmax<c>.<dt> <Dd>,<Dn>,<Dm> vmin<c>.<dt> <Qd>,<Qn>,<Qm> vmin<c>.<dt> <Dd>,<Dn>,<Dm>
- case thumb2_vpmax_vpmin__int:
- // A8.6.352 VPMAX, VPMIN (integer)
- // vp<op><c>.<dt> <Dd>, <Dn>, <Dm>
- // (this works despite no Q version because Q==1 is UNDEFEIND)
- // . . . U_1_12_12 . . . . . D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 . . . . N_0_7_7 Q_0_6_6 M_0_5_5 op_0_4_4 Vm_0_3_0
+ case thumb2_vmax_vmin__int: // A8.6.321 VMAX, VMIN (integer)
+ // vmax<c>.<dt> <Qd>,<Qn>,<Qm>
+ // vmax<c>.<dt> <Dd>,<Dn>,<Dm>
+ // vmin<c>.<dt> <Qd>,<Qn>,<Qm>
+ // vmin<c>.<dt> <Dd>,<Dn>,<Dm>
+ case thumb2_vpmax_vpmin__int: // A8.6.352 VPMAX, VPMIN (integer)
+ // vp<op><c>.<dt> <Dd>, <Dn>, <Dm>
+ // (this works despite no Q version because Q==1 is UNDEFINED)
instruction = mnemonic + (isBitEnabled(opcode, 4) ? "min" : "max")
- + getVFPSorUDataType(opcode, 28) + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ + getVFPSorUDataType(opcode, 28) + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vmax_vmin__fp:
- // A8.6.322 VMAX, VMIN (floating-point)
- // vmax<c>.f32 <Qd>,<Qn>,<Qm> vmax<c>.f32 <Dd>,<Dn>,<Dm> vmin<c>.f32 <Qd>,<Qn>,<Qm> vmin<c>.f32 <Dd>,<Dn>,<Dm>
- case thumb2_vpmax_vpmin__fp:
- // A8.6.353 VPMAX, VPMIN (floating-point)
- // vp<op><c>.f32 <Dd>,<Dn>,<Dm>
- // . . . . . . . . . D_1_6_6 op_1_5_5 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 . . . . N_0_7_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
+ case thumb2_vmax_vmin__fp: // A8.6.322 VMAX, VMIN (floating-point)
+ // vmax<c>.f32 <Qd>, <Qn>, <Qm>
+ // vmax<c>.f32 <Dd>, <Dn>, <Dm>
+ // vmin<c>.f32 <Qd>, <Qn>, <Qm>
+ // vmin<c>.f32 <Dd>, <Dn>, <Dm>
+ case thumb2_vpmax_vpmin__fp:// A8.6.353 VPMAX, VPMIN (floating-point)
+ // vp<op><c>.f32 <Dd>,<Dn>,<Dm>
instruction = mnemonic + (isBitEnabled(opcode, 21) ? "min.f32" : "max.f32")
- + getVFPQorDdnmRegs(opcode);
+ + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vml__int:
- // A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
- // v<op><c>.<dt> <Qd>,<Qn>,<Qm> v<op><c>.<dt> <Dd>,<Dn>,<Dm>
- // 1 1 1 op_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
+ case thumb2_vml__int: // A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
+ // v<op><c>.<dt> <Qd>, <Qn>, <Qm>
+ // v<op><c>.<dt> <Dd>, <Dn>, <Dm>
mnemonic += isBitEnabled(opcode, 28) ? 's' : 'a';
instruction = mnemonic + getVFPIDataType(opcode, 20) + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vml__int_long:
- // A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
- // v<op>l<c>.<dt> <Qd>,<Dn>,<Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 op_0_9_9 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
+ case thumb2_vml__int_long: // A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
+ // v<op>l<c>.<dt> <Qd>,<Dn>,<Dm>
mnemonic += isBitEnabled(opcode, 9) ? "sl" : "al";
instruction = mnemonic + getVFPSorUDataType(opcode, 28)
- + TAB + getVFPQdDnDmRegs(opcode);
- // No pc check: not applicable
+ + TAB + getVFPQdDnDmRegs(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vml__f32:
- // A8.6.324 VMLA, VMLS (floating-point)
- // v<op><c>.f32 <Qd>,<Qn>,<Qm> v<op><c>.f32 <Dd>,<Dn>,<Dm>
+ case thumb2_vml__f32: // A8.6.324 VMLA, VMLS (floating-point)
+ // v<op><c>.f64 <Dd>, <Dn>, <Dm>
+ // v<op><c>.f32 <Sd>, <Sn>, <Sm>
mnemonic += isBitEnabled(opcode, 21) ? "s.f32" : "a.f32";
instruction = mnemonic + TAB + getVFPQorDdnmRegs(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vml__fp:
- // A8.6.324 VMLA, VMLS (floating-point)
- // v<op><c>.f64 <Dd>,<Dn>,<Dm> v<op><c>.f32 <Sd>,<Sn>,<Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 0 0 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 op_0_6_6 M_0_5_5 0 Vm_0_3_0
+ case thumb2_vml__fp: // A8.6.324 VMLA, VMLS (floating-point)
+ // v<op><c>.f64 <Dd>, <Dn>, <Dm>
+ // v<op><c>.f32 <Sd>, <Sn>, <Sm>
mnemonic += isBitEnabled(opcode, 6) ? 's' : 'a';
instruction = mnemonic + getVFPSzF64F32dnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vml__scalar:
- // v<op><c>.<dt> <Qd>,<Qn>,<Dm[x]> v<op><c>.<dt> <Dd>,<Dn>,<Dm[x]>
- // v<op>l<c>.<dt> <Qd>,<Dn>,<Dm[x]>
+ case thumb2_vml__scalar: // A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
+ // v<op><c>.<dt> <Qd>, <Qn>, <Dm[x]>
+ // v<op><c>.<dt> <Dd>, <Dn>, <Dm[x]>
+ // v<op>l<c>.<dt> <Qd>, <Dn>, <Dm[x]>
mnemonic += isBitEnabled(opcode, 10) ? 's' : 'a';
- case thumb2_vmul__scalar:
- // vmul<c>.<dt> <Qd>,<Qn>,<Dm[x]> vmul<c>.<dt> <Dd>,<Dn>,<Dm[x]>
- // vmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
- case thumb2_vqdmull__scalar: // bit9 == 1, so getVFP_vmXXScalar() works
- // vqdmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
+ case thumb2_vmul__scalar: // A8.6.339 VMUL, VMULL (by scalar)
+ // vmul<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+ // vmul<c>.<dt> <Dd>, <Dn>, <Dm[x]>
+ // vmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
+ case thumb2_vqdmull__scalar:// A8.6.360 VQDMULL
+ // vqdmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
+ // bit 9 == 1, so getVFP_vmXXScalar() works
instruction = mnemonic + getVFP_vmXXScalar(opcode, 28);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmov__imm:
- // A8.6.326 VMOV (immediate)
- // vmov<c>.f64 <Dd>,#<imm> vmov<c>.f32 <Sd>,#<imm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 imm4H_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 (0) 0 (0) 0 imm4L_0_3_0
+ case thumb2_vmov__imm: // A8.6.326 VMOV (immediate)
+ // vmov<c>.f64 <Dd>, #<imm>
+ // vmov<c>.f32 <Sd>, #<imm>
mnemonic += getVFPSzF64F32Type(getBit(opcode, 8));
instruction = mnemonic + TAB + getVFPDorSReg(opcode, getBit(opcode, 8), 12, 22)
- + ",#" + getHexValue((opcode >> 16 & 0xf) << 4 | opcode & 0xf);
- // No pc check: not applicable
+ + ",#" + getHexValue((opcode >> 16 & 0xf) << 4 | opcode & 0xf);
+ // No PC check: not applicable
break;
- case thumb2_vmov_5:
- // vmov<c>.<size> <Dd[x]>,<Rt>
+ case thumb2_vmov_5: // A8.6.328 VMOV (ARM core register to scalar)
+ // vmov<c>.<size> <Dd[x]>,<Rt>
instruction = mnemonic + getVFP_vmovArmCoreRegToScalar(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmov_6:
- // vmov<c>.<dt> <Rt>,<Dn[x]>
+ case thumb2_vmov_6: // A8.6.329 VMOV (scalar to ARM core register)
+ // vmov<c>.<dt> <Rt>,<Dn[x]>
instruction = mnemonic + getVFP_vmovScalarToArmCoreReg(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmov_7:
- // vmov<c> <Sn>,<Rt> vmov<c> <Rt>,<Sn>
+ case thumb2_vmov_7: // A8.6.330 VMOV (between ARM core register and
+ // single-precision register)
+ // vmov<c> <Sn>, <Rt>
+ // vmov<c> <Rt>, <Sn>
instruction = mnemonic + getVFP_vmovBetweenArmCoreAndSinglePrecReg(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmov_8:
- // vmov<c> <Sm>,<Sm1>,<Rt>,<Rt2> vmov<c> <Rt>,<Rt2>,<Sm>,<Sm1>
+ case thumb2_vmov_8: // A8.6.331 VMOV (between two ARM core registers and
+ // two single-precision registers)
+ // vmov<c> <Sm>, <Sm1>, <Rt>, <Rt2>
+ // vmov<c> <Rt>, <Rt2>, <Sm>, <Sm1>
instruction = mnemonic + getVFP_vmovBetween2ArmCoreAndSinglePrecRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmov_9:
- // vmov<c> <Dm>,<Rt>,<Rt2> vmov<c> <Rt>,<Rt2>,<Dm>
+ case thumb2_vmov_9: // A8.6.332 VMOV (between two ARM core registers and
+ // a doubleword extension register)
+ // vmov<c> <Dm>, <Rt>, <Rt2>
+ // vmov<c> <Rt>, <Rt2>, <Dm>
instruction = mnemonic + getVFP_vmovBetween2ArmCoreAnd1DoublewordExtensionRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmovl:
- // vmovl<c>.<dt> <Qd>, <Dm>
- case thumb2_vshll__various:
- // vshll<c>.<type><size> <Qd>,<Dm>,#<imm> (0 < <imm> < <size>)
+ case thumb2_vmovl: // A8.6.333 VMOVL
+ // vmovl<c>.<dt> <Qd>, <Dm>
+ case thumb2_vshll__various: // A8.6.384 VSHLL
+ // vshll<c>.<type><size> <Qd>,<Dm>,#<imm> (0 < <imm> < <size>)
instruction = mnemonic + getVFP_vmovl_vshll_operands(opcode, 28);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmovn:
- // A8.6.334 VMOVN
- // vmovn<c>.<dt> <Dd>,<Qm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 1 0 0 0 M_0_5_5 0 Vm_0_3_0
+ case thumb2_vmovn: // A8.6.334 VMOVN
+ // vmovn<c>.<dt> <Dd>,<Qm>
mnemonic += getVFPIDataType2(opcode, 18);
instruction = mnemonic + TAB + getVFPQorDReg(opcode, 0, 12, 22)
- + ',' + getVFPQorDReg(opcode, 1, 0, 5);
- // No pc check: not applicable
+ + ',' + getVFPQorDReg(opcode, 1, 0, 5);
+ // No PC check: not applicable
break;
- case thumb2_vmrs:
- // A8.6.335 VMRS
- // vmrs<c> <Rt>,fpscr
- // 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 Rt_0_15_12 1 0 1 0 0 (0)(0) 1 (0)(0)(0)(0)
+ case thumb2_vmrs: // A8.6.335 VMRS
+ // vmrs<c> <Rt>,fpscr
+ // B6.1.14 VMRS
+ // vmrs<c> <Rt>,<spec_reg>
instruction = mnemonic + TAB + getR_12(opcode) + "," + getVFPSpecialReg(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmsr:
- // A8.6.336 VMSR
- // vmsr<c> fpscr,<Rt>
- // 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 Rt_0_15_12 1 0 1 0 0 (0)(0) 1 (0)(0)(0)(0)
+ case thumb2_vmsr: // A8.6.336 VMSR
+ // vmsr<c> fpscr,<Rt>
+ // B6.1.15 VMSR
+ // vmsr<c> <spec_reg>,<Rt>
instruction = mnemonic + TAB + getVFPSpecialReg(opcode) + "," + getR_12(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmul_1:
- // A8.6.337 VMUL, VMULL (integer and polynomial)
- // vmul<c>.<dt> <Qd>,<Qn>,<Qm> vmul<c>.<dt> <Dd>,<Dn>,<Dm>
- // 1 1 1 op_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
+ case thumb2_vmul_1: // A8.6.337 VMUL, VMULL (integer and polynomial)
+ // vmul<c>.<dt> <Qd>, <Qn>, <Qm>
+ // vmul<c>.<dt> <Dd>, <Dn>, <Dm>
mnemonic += (isBitEnabled(opcode, 28) ? ".p" : ".i") + getVFPDataTypeSize(opcode, 20);
instruction = mnemonic + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vmull:
- // A8.6.337 VMUL, VMULL (integer and polynomial)
- // vmull<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 1 op_9_9 0 N_7_7 0 M_5_5 0 Vm_3_0
+ case thumb2_vmull: // A8.6.337 VMUL, VMULL (integer and polynomial)
+ // vmull<c>.<dt> <Qd>, <Dn>, <Dm>
mnemonic += isBitEnabled(opcode, 9) ? getVFPPDataType(opcode, 20) : getVFPSorUDataType(opcode, 28);
instruction = mnemonic + TAB + getVFPQdDnDmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vpadal:
- // vpadal<c>.<dt> <Qd>, <Qm>
- // vpadal<c>.<dt> <Dd>, <Dm>
- case thumb2_vpaddl:
- // vpaddl<c>.<dt> <Qd>, <Qm>
- // vpaddl<c>.<dt> <Dd>, <Dm>
+ case thumb2_vpadal: // A8.6.348 VPADAL
+ // vpadal<c>.<dt> <Qd>, <Qm>
+ // vpadal<c>.<dt> <Dd>, <Dm>
+ case thumb2_vpaddl: // A8.6.351 VPADDL
+ // vpaddl<c>.<dt> <Qd>, <Qm>
+ // vpaddl<c>.<dt> <Dd>, <Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 4, 7); // chose bit 4 because it is 0
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vpop:
- // vpop <list> <list> is consecutive 64-bit registers
- // vpop <list> <list> is consecutive 32-bit registers
- case thumb2_vpush:
- // vpush <list> <list> is consecutive 64-bit registers
- // vpush <list> <list> is consecutive 32-bit registers
+ case thumb2_vpop: // A8.6.354 VPOP
+ // vpop <list> <list> is consecutive 64-bit registers
+ // vpop <list> <list> is consecutive 32-bit registers
+ case thumb2_vpush: // A8.6.355 VPUSH
+ // vpush <list> <list> is consecutive 64-bit registers
+ // vpush <list> <list> is consecutive 32-bit registers
instruction = mnemonic + getVFP_vpop_vpush_operands(opcode);
+ // No PC check: not applicable
break;
- case thumb2_vqdml__scalar:
- // A8.6.358 VQDMLAL, VQDMLSL
- // vqd<op><c>.<dt> <Qd>,<Dn>,<Dm[x]>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 1 1 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
+ case thumb2_vqdml__scalar: // A8.6.358 VQDMLAL, VQDMLSL
+ // vqd<op><c>.<dt> <Qd>,<Dn>,<Dm[x]>
mnemonic += isBitEnabled(opcode, 10) ? "sl.s" : "al.s";
instruction = mnemonic + getVFPScalarOperands(opcode, 1, 0);
+ // No PC check: not applicable
break;
- case thumb2_vqdmulh__vec:
- // vqdmulh<c>.<dt> <Qd>,<Qn>,<Qm> vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
- case thumb2_vqrdmulh__vec:
- // vqrdmulh<c>.<dt> <Qd>,<Qn>,<Qm> vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
+ case thumb2_vqdmulh__vec: // A8.6.359 VQDMULH
+ // vqdmulh<c>.<dt> <Qd>,<Qn>,<Qm>
+ // vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
+ case thumb2_vqrdmulh__vec: // A8.6.363 VQRDMULH
+ // vqrdmulh<c>.<dt> <Qd>,<Qn>,<Qm>
+ // vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
mnemonic += isBitEnabled(opcode, 20) ? ".s16" : ".s32";
instruction = mnemonic + TAB + getVFPQorDdnmRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vqdmulh__scalar:
- // vqdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]> vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
- case thumb2_vqrdmulh__scalar:
- // vqrdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]> vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
+ case thumb2_vqdmulh__scalar:// A8.6.359 VQDMULH
+ // vqdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]>
+ // vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
+ case thumb2_vqrdmulh__scalar: // A8.6.363 VQRDMULH
+ // vqrdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]>
+ // vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
{
int q = getBit(opcode, 28);
instruction = mnemonic + ".s" + getVFPScalarOperands(opcode, q, q);
}
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vqmov:
- // vqmov{u}n<c>.<type><size> <Dd>,<Qm>
+ case thumb2_vqmov: // A8.6.361 VQMOVN, VQMOVUN
+ // vqmov{u}n<c>.<type><size> <Dd>,<Qm>
instruction = mnemonic + getVFP_vqmov_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vqrshl: // A8.6.364 VQRSHL
- // vqrshl<c>.<type><size> <Qd>,<Qm>,<Qn>
- // vqrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- case thumb2_vqshl__reg: // A8.6.366 VQSHL (register)
- // vqshl<c>.<type><size> <Qd>,<Qm>,<Qn>
- // vqshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- case thumb2_vrshl: // A8.6.375 VRSHL
- // vrshl<c>.<type><size> <Qd>,<Qm>,<Qn>
- // vrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- case thumb2_vshl__reg: // A8.6.383 VSHL (register)
- // vshl<c>.<type><size> <Qd>,<Qm>,<Qn>
- // vshl<c>.<type><size> <Dd>,<Dm>,<Dn>
+ case thumb2_vqrshl: // A8.6.364 VQRSHL
+ // vqrshl<c>.<type><size> <Qd>,<Qm>,<Qn>
+ // vqrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
+ case thumb2_vqshl__reg: // A8.6.366 VQSHL (register)
+ // vqshl<c>.<type><size> <Qd>,<Qm>,<Qn>
+ // vqshl<c>.<type><size> <Dd>,<Dm>,<Dn>
+ case thumb2_vrshl: // A8.6.375 VRSHL
+ // vrshl<c>.<type><size> <Qd>,<Qm>,<Qn>
+ // vrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
+ case thumb2_vshl__reg: // A8.6.383 VSHL (register)
+ // vshl<c>.<type><size> <Qd>,<Qm>,<Qn>
+ // vshl<c>.<type><size> <Dd>,<Dm>,<Dn>
instruction = mnemonic + getVFPSorUDataType(opcode, 28) + getVFPQorDdmnRegs(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vqrshr:
- // vqrshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- case thumb2_vqshr:
- // vqshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
+ case thumb2_vqrshr: // A8.6.365 VQRSHRN, VQRSHRUN
+ // vqrshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
+ case thumb2_vqshr: // A8.6.368 VQSHRN, VQSHRUN
+ // vqshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
instruction = mnemonic + getVFP_vqXshr_instruction(opcode, 28);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vqshl__imm:
- // vqshl{u}<c>.<type><size> <Qd>,<Qm>,#<imm> vqshl{u}<c>.<type><size> <Dd>,<Dm>,#<imm>
+ case thumb2_vqshl__imm: // A8.6.367 VQSHL, VQSHLU (immediate)
+ // vqshl{u}<c>.<type><size> <Qd>,<Qm>,#<imm>
+ // vqshl{u}<c>.<type><size> <Dd>,<Dm>,#<imm>
instruction = mnemonic + getVFP_vqshl_instruction(opcode, 28);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vrecpe:
- // vrecpe<c>.<dt> <Qd>, <Qm>
- // vrecpe<c>.<dt> <Dd>, <Dm>
- case thumb2_vrsqrte:
- // vrsqrte<c>.<dt> <Qd>, <Qm>
- // vrsqrte<c>.<dt> <Dd>, <Dm>
+ case thumb2_vrecpe: // A8.6.371 VRECPE
+ // vrecpe<c>.<dt> <Qd>, <Qm>
+ // vrecpe<c>.<dt> <Dd>, <Dm>
+ case thumb2_vrsqrte: // A8.6.378 VRSQRTE
+ // vrsqrte<c>.<dt> <Qd>, <Qm>
+ // vrsqrte<c>.<dt> <Dd>, <Dm>
instruction = mnemonic + getVFPSorUorFQorDdmOperands(opcode, 8, 10);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vrev:
- // vrev<n><c>.<size> <Qd>, <Qm> vrev<n><c>.<size> <Dd>, <Dm>
+ case thumb2_vrev: // A8.6.373 VREV16, VREV32, VREV64
+ // vrev<n><c>.<size> <Qd>,<Qm>
+ // vrev<n><c>.<size> <Dd>,<Dm>
instruction = mnemonic + getVFP_vrev_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vrshr:
- // vrshr<c>.<type><size> <Qd>, <Qm>, #<imm> vrshr<c>.<type><size> <Dd>, <Dm>, #<imm>
- case thumb2_vrsra:
- // vrsra<c>.<type><size> <Qd>,<Qm>,#<imm> vrsra<c>.<type><size> <Dd>,<Dm>,#<imm>
- case thumb2_vshr:
- // vshr<c>.<type><size> <Qd>,<Qm>,#<imm> vshr<c>.<type><size> <Dd>,<Dm>,#<imm>
- case thumb2_vsra:
- // vsra<c>.<type><size> <Qd>,<Qm>,#<imm> vsra<c>.<type><size> <Dd>,<Dm>,#<imm>
+ case thumb2_vrshr: // A8.6.376 VRSHR
+ // vrshr<c>.<type><size> <Qd>, <Qm>, #<imm>
+ // vrshr<c>.<type><size> <Dd>, <Dm>, #<imm>
+ case thumb2_vrsra: // A8.6.380 VRSRA
+ // vrsra<c>.<type><size> <Qd>, <Qm>, #<imm>
+ // vrsra<c>.<type><size> <Dd>, <Dm>, #<imm>
+ case thumb2_vshr: // A8.6.385 VSHR
+ // vshr<c>.<type><size> <Qd>, <Qm>, #<imm>
+ // vshr<c>.<type><size> <Dd>, <Dm>, #<imm>
+ case thumb2_vsra: // A8.6.389 VSRA
+ // vsra<c>.<type><size> <Qd>, <Qm>, #<imm>
+ // vsra<c>.<type><size> <Dd>, <Dm>, #<imm>
mnemonic += (isBitEnabled(opcode, 28) ? ".u" : ".s");
// no break
- case thumb2_vsri:
- // vsri<c>.<size> <Qd>,<Qm>,#<imm> vsri<c>.<size> <Dd>,<Dm>,#<imm>
+ case thumb2_vsri: // A8.6.390 VSRI
+ // vsri<c>.<size> <Qd>, <Qm>, #<imm>
+ // vsri<c>.<size> <Dd>, <Dm>, #<imm>
instruction = mnemonic + getVFP_vXrX_instruction(opcode, true);
- // No pc check: not applicable
- break;
-
- case thumb2_vshl__imm:
- // vshl<c>.i<size> <Qd>,<Qm>,#<imm> vshl<c>.i<size> <Dd>,<Dm>,#<imm>
- case thumb2_vsli:
- // vsli<c>.<size> <Qd>,<Qm>, #<imm> vsli<c>.<size> <Dd>,<Dm>,#<imm>
- instruction = mnemonic + getVFP_vXrX_instruction(opcode, false);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vrshrn:
- // vrshrn<c>.i<size> <Dd>,<Qm>,#<imm>
- case thumb2_vshrn:
- // vshrn<c>.i<size> <Dd>,<Qm>,#<imm>
+ case thumb2_vrshrn: // A8.6.377 VRSHRN
+ // vrshrn<c>.i<size> <Dd>,<Qm>,#<imm>
+ case thumb2_vshrn: // A8.6.386 VSHRN
+ // vshrn<c>.i<size> <Dd>,<Qm>,#<imm>
instruction = mnemonic + getVFP_vXshrn_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vshll__max:
- // A8.6.384 VSHLL
- // vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (<imm> == <size>)
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 1 1 0 0 M_0_5_5 0 Vm_0_3_0
+ case thumb2_vshl__imm: // A8.6.382 VSHL (immediate)
+ // vshl<c>.i<size> <Qd>, <Qm>, #<imm>
+ // vshl<c>.i<size> <Dd>, <Dm>, #<imm>
+ case thumb2_vsli: // A8.6.387 VSLI
+ // vsli<c>.<size> <Qd>, <Qm>, #<imm>
+ // vsli<c>.<size> <Dd>, <Dm>, #<imm>
+ instruction = mnemonic + getVFP_vXrX_instruction(opcode, false);
+ // No PC check: not applicable
+ break;
+
+ case thumb2_vshll__max: // A8.6.384 VSHLL
+ // vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (<imm> == <size>)
mnemonic += getVFPIDataType3(opcode, 18);
instruction = mnemonic + TAB + getVFPQorDReg(opcode, 1, 12, 22)
+ ',' + getVFPQorDReg(opcode, 0, 0, 5) + ",#" + (8 << (opcode >> 18 & 3));
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vtb:
- // v<op><c>.8 <Dd>, <list>, <Dm>
+ case thumb2_vtb: // A8.6.406 VTBL, VTBX
+ // v<op><c>.8 <Dd>, <list>, <Dm>
instruction = mnemonic + getVFP_vtb_instruction(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vtrn:
- case thumb2_vuzp:
- case thumb2_vzip:
+ case thumb2_vtrn: // A8.6.407 VTRN
+ // vtrn<c>.<size> <Qd>, <Qm>
+ // vtrn<c>.<size> <Dd>, <Dm>
+ case thumb2_vuzp: // A8.6.409 VUZP
+ // vuzp<c>.<size> <Qd>, <Qm>
+ // vuzp<c>.<size> <Dd>, <Dm>
+ case thumb2_vzip: // A8.6.410 VZIP
+ // vzip<c>.<size> <Qd>, <Qm>
+ // vzip<c>.<size> <Dd>, <Dm>
instruction = mnemonic + getVFPSzQorDdmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_vtst:
+ case thumb2_vtst: // A8.6.408 VTST
+ // vtst<c>.<size> <Qd>, <Qn>, <Qm>
+ // vtst<c>.<size> <Dd>, <Dn>, <Dm>
instruction = mnemonic + getVFPSzQorDdnmOperands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
+ // CoProcessor instructions
-
-
- // CoProcessor instructions
-
- case thumb2_cdp:
- // cdp<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- case thumb2_cdp2:
- // cdp2<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+ case thumb2_cdp: // A8.6.28 CDP, CDP2
+ // cdp<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+ case thumb2_cdp2: // A8.6.28 CDP, CDP2
+ // cdp2<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
instruction = mnemonic + "\t" + getCo_cdp_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_cps:
- // cps<effect>.w <iflags>{,#<mode>} Not permitted in IT block. cps #<mode> Not permitted in IT block.
+ case thumb2_cps: // B6.1.1 CPS
+ // cps<effect>.w <iflags>{,#<mode>} Not permitted in IT block.
+ // cps #<mode> Not permitted in IT block.
instruction = mnemonic + getCo_cps_instruction(opcode, true);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_ldc: // A8.6.51 LDC, LDC2 (immediate) // ldc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
- // ldc{l} <coproc>,<CRd>,[<Rn>],#+/-<imm>
- // ldc{l} <coproc>,<CRd>,[<Rn>],<option>
- // A8.6.51 LDC, LDC2 (immediate) // ldc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
- // ldc2{l} <coproc>,<CRd>,[<Rn>],#+/-<imm>
- // ldc2{l} <coproc>,<CRd>,[<Rn>],<option>
- case thumb2_stc: // A8.6.188 STC, STC2 // stc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
- // stc{l} <coproc>,<CRd>,[<Rn>],#+/-<imm>
- // stc{l} <coproc>,<CRd>,[<Rn>],<option>
- // A8.6.188 STC, STC2 // stc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
- // stc2{l} <coproc>,<CRd>,[<Rn>],#+/-<imm>
- // stc2{l} <coproc>,<CRd>,[<Rn>],<option>
- // . . . . . . . P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 . Rn_1_3_0 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
+ case thumb2_ldc: // A8.6.51 LDC, LDC2 (immediate)
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // A8.6.52 LDC, LDC2 (literal)
+ // ldc{l}<c> <coproc>,<CRd>,<label>
+ // ldc{l}<c> <coproc>,<CRd>,[pc,#-0]
+ // Special case ldc{l}<c> <coproc>,<CRd>,[pc],<option>
+ // A8.6.52 LDC, LDC2 (literal)
+ // ldc2{l}<c> <coproc>,<CRd>,<label>
+ // ldc2{l}<c> <coproc>,<CRd>,[pc,#-0]
+ // Special case ldc2{l}<c> <coproc>,<CRd>,[pc],<option>
+ // A8.6.51 LDC, LDC2 (immediate)
+ // ldc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // ldc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ case thumb2_stc: // A8.6.188 STC, STC2
+ // stc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
+ // stc{l} <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // stc{l} <coproc>,<CRd>,[<Rn>],<option>
+ // A8.6.188 STC, STC2
+ // stc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}
+ // stc2{l} <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // stc2{l} <coproc>,<CRd>,[<Rn>],<option>
if (isBitEnabled(opcode, 28))
mnemonic += '2';
instruction = mnemonic + (isBitEnabled(opcode, 22) ? "l\t" : "\t") + getCoprocessor(opcode)
- + ',' + getCR_12(opcode) + ',' + getAddrModeImm8(opcode);
+ + ',' + getCR_12(opcode) + ',' + getAddrModeImm8(opcode);
+ // No PC check: not applicable
break;
- case thumb2_mcr:
- // mcr<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // mcr2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
+ case thumb2_mcr: // A8.6.92 MCR, MCR2
+ // mcr<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
+ // mcr2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
if (isBitEnabled(opcode, 28))
mnemonic += '2';
instruction = mnemonic + getCo_mcr_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_mcrr:
- // mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- // mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- case thumb2_mrrc:
- // mrrc<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- // mrrc2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ case thumb2_mcrr: // A8.6.93 MCRR, MCRR2
+ // mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ // mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ case thumb2_mrrc: // A8.6.101 MRRC, MRRC2
+ // mrrc<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ // mrrc2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
if (isBitEnabled(opcode, 28))
mnemonic += '2';
instruction = mnemonic + getCo_mrr_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
- case thumb2_mrc:
- // mrc<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // mrc2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
+ case thumb2_mrc: // A8.6.100 MRC, MRC2
+ // mrc<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
+ // A8.6.100 MRC, MRC2
+ // mrc2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
if (isBitEnabled(opcode, 28))
mnemonic += '2';
instruction = mnemonic + getCo_mrc_operands(opcode);
- // No pc check: not applicable
+ // No PC check: not applicable
break;
default:
@@ -4696,15 +4959,6 @@
}
-
-
-
-
-
-
-
-
-
private String getAddrMode(int opcode) {
int amode = (opcode >> 23) & 0x3;
if (amode == 0)
@@ -4731,7 +4985,7 @@
operands += ",#" + sign + getHexValue(offset);
} else {
operands += "," + sign + getR_0(opcode);
- if (scaled != 0 || shiftValue != 0) // scaled register offset
+ if (scaled != 0 || shiftValue != 0) // scaled register offset
operands += getAddrMode2ScaledRegOffset(opcode, shiftValue, shiftMode);
}
operands += isBitEnabled(opcode, 21) ? "]!" : "]";
@@ -4742,7 +4996,7 @@
operands += ",#" + sign + getHexValue(offset);
} else {
operands += "]," + sign + getR_0(opcode);
- if (scaled != 0 || shiftValue != 0) // scaled register offset
+ if (scaled != 0 || shiftValue != 0) // scaled register offset
operands += getAddrMode2ScaledRegOffset(opcode, shiftValue, shiftMode);
}
}
@@ -4834,7 +5088,7 @@
int offset = ((opcode << 8) >> 6) + 8;
return offset;
}
-
+
private String getCondition(int condition) {
switch (condition) {
case 0: return "eq";
@@ -4983,8 +5237,8 @@
}
private String getRotationOperand(int opcode, int bit) {
- int rotation = ((opcode >> (bit-3)) & 0x18);
- return (rotation != 0) ? ",ror #" + rotation : "";
+ int rotation = ((opcode >> (bit-3)) & 0x18);
+ return (rotation != 0) ? ",ror #" + rotation : "";
}
private String getShifterOperand(int opcode) {
@@ -5113,7 +5367,7 @@
String ops;
- // treat unpredictable ((imod == 0 && !changeMode) || imod == 1) as a change mode to 0
+ // treat UNPREDICTABLE ((imod == 0 && !changeMode) || imod == 1) as a change mode to 0
if (imod == 0 || imod == 1) {
if (!changeMode || mode == 0)
ops = TAB + "#0";
@@ -5184,7 +5438,7 @@
* {@literal mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>}
* {@literal mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>}
* A8.6.101 MRRC, MRRC2
- * {@literal mrrc<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>}
+ * {@literal mrrc<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>}
* {@literal mrrc2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>}
*/
private String getCo_mrr_operands(int opcode) {
@@ -5196,14 +5450,14 @@
private int getThumbBranchOffset8(int opcode) {
int offset = (byte)(opcode & 0xff);
-
+
offset = (offset*2) + 4;
return offset;
}
private int getThumbBranchOffset11(int opcode) {
short offset = (short) ((opcode << 5) & 0xffff);
-
+
return (offset / 16) + 4;
}
@@ -5382,7 +5636,7 @@
return ",rrx";
shift += "ror";
}
- return shift + " #" + value;
+ return shift + " #" + value;
}
private int getThumb2ShiftValue(int opcode, int type) {
@@ -5420,7 +5674,7 @@
private String getVFPDdQmRegs(int opcode) {
return getVFPQorDReg(opcode, 0, 12, 22) + ',' + getVFPQorDReg(opcode, 1, 0, 5);
- }
+ }
private String getVFPIncDec(int opcode) {
int mode = (opcode >> 23) & 3;
@@ -5435,10 +5689,10 @@
private int getVFPDataTypeSize (int opcode, int sizePos) {
return 8 << (opcode >> sizePos & 3);
}
-
+
/**
* Return 6-bit immediate instruction size
- *
+ *
* @param opcode
* @param uPos bit indicating unsigned
* @param opPos
@@ -5456,7 +5710,7 @@
/**
* Return vqshl{u} sign or unsigned type with bit size
- *
+ *
* @param opcode
* @param lBit
* @param uPos bit indicating unsigned
@@ -5598,7 +5852,7 @@
private String getVFPIorFDataType(int opcode, int sizePos, int bitIorF) {
int size = 8 << ((opcode >> sizePos) & 0x3);
int f = (opcode >> bitIorF) & 1;
- return (f == 1 ? ".f" : ".i") + size;
+ return (f == 1 ? ".f" : ".i") + size;
}
private String getVFPSorUDataType(int opcode, int uPos) {
@@ -5669,7 +5923,7 @@
String td = u ? (sx ? ".u32" : ".u16") : (sx ? ".s32" : ".s16");
String ts = sf ? ".f64" : ".f32";
-
+
return op ? td + ts : ts + td;
}
@@ -5693,7 +5947,7 @@
suffix = "!";
else
suffix = "," + getRegName(Rm);
-
+
return suffix;
}
@@ -5714,8 +5968,8 @@
*/
private String getVFPIDataTypeQorDdnmOperands(int opcode) {
return getVFPIDataType(opcode, 20) + getVFPQorDdnmRegs(opcode);
- }
-
+ }
+
/**
* ARM--- ... D_22_22 size_21_20 Vn_10_16 Vd___15_12 ... N___7_7 . M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 ... N_0_7_7 . M_0_5_5 . Vm_0_3_0
@@ -5737,7 +5991,7 @@
+ ',' + getVFPQorDReg(opcode, 1, 16, 7)
+ ',' + getVFPQorDReg(opcode, 1, 0, 5);
return ops;
- }
+ }
/**
* ARM--- ... D_22_22 size_21_20 Vn_19_16 Vd___15_12 ... N___7_7 . M___5_5 . Vm___3_0<br>
@@ -5758,15 +6012,15 @@
* {@literal vqd<op><c>.<dt> <Qd>,<Dn>,<Dm>}
* A8.6.360 VQDMULL
* {@literal vqdmull<c>.<dt> <Qd>,<Dn>,<Dm>}
- *
+ *
*/
private String getVFPQdDnDmRegs(int opcode) {
String regs = getVFPQorDReg(opcode, 1, 12, 22)
+ ',' + getVFPQorDReg(opcode, 0, 16, 7)
+ ',' + getVFPQorDReg(opcode, 0, 0, 5);
return regs;
- }
-
+ }
+
/**
* ARM--- ... D_22_22 ... Vd___15_12 ... Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 ... Vd_0_15_12 ... Q_0_6_6 M_0_5_5 . Vm_0_3_0
@@ -5785,8 +6039,8 @@
private String getVFPQorDdmRegs(int opcode) {
int q = getBit(opcode, 6);
return TAB + getVFPQorDReg(opcode, q, 12, 22) + ',' + getVFPQorDReg(opcode, q, 0, 5);
- }
-
+ }
+
/**
* ARM--- ... D_22_22 ... Vn_19_16 Vd___15_12 ... N___7_7 Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 ... Vn_1_3_0 Vd_0_15_12 ... N_0_7_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
@@ -5908,7 +6162,7 @@
+ ',' + getVFPQorDReg(opcode, nType, 16, 7)
+ ",d" + mR + '[' + index + ']';
}
-
+
/**
* ARM--- ... D_22_22 . . size_19_18 . . Vd___15_12 ... Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 . . size_1_3_2 . . Vd_0_15_12 ... Q_0_6_6 M_0_5_5 . Vm_0_3_0
@@ -5946,8 +6200,8 @@
*/
private String getVFPSorUorFQorDdmOperands(int opcode, int bitIorF, int bitSorU) {
return getVFPSorUorFDataType(opcode, 18, bitIorF, bitSorU) + TAB + getVFPQorDdmRegs(opcode);
- }
-
+ }
+
/**
* ARM--- ... D_22_22 . . size_19_18 . . Vd___15_12 ... Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 . . size_1_3_2 . . Vd_0_15_12 ... Q_0_6_6 M_0_5_5 . Vm_0_3_0
@@ -5969,7 +6223,7 @@
private String getVFPIorFQorDdmOperands(int opcode, int bitIorF) {
return getVFPIorFDataType(opcode, 18, bitIorF) + TAB + getVFPQorDdmRegs(opcode);
}
-
+
/**
* @param szbit bit containing the sz determining ".f64" or ".f32"
* @return String containing ".f64" or ".f32"
@@ -6014,7 +6268,7 @@
* A8.6.272 VADD (floating-point)
* {@literal vadd<c>.f64 <Dd>,<Dn>,<Dm> vadd<c>.f32 <Sd>,<Sn>,<Sm>}
* A8.6.301 VDIV
- * {@literal vdiv<c>.f64 <Dd>,<Dn>,<Dm> vdiv<c>.f32 <Sd>,<Sn>,<Sm>}
+ * {@literal vdiv<c>.f64 <Dd>,<Dn>,<Dm> vdiv<c>.f32 <Sd>,<Sn>,<Sm>}
* A8.6.324 VMLA, VMLS (floating-point)
* {@literal vml<op><c>.f64 <Dd>,<Dn>,<Dm> vml<op><c>.f32 <Sd>,<Sn>,<Sm>}
* A8.6.338 VMUL (floating-point)
@@ -6022,9 +6276,9 @@
* A8.6.343 VNMLA, VNMLS, VNMUL
* {@literal vnmul<c>.f64 <Dd>,<Dn>,<Dm> vnmul<c>.f32 <Sd>,<Sn>,<Sm>}
* A8.6.402 VSUB (floating-point)
- * {@literal vsub<c>.f64 <Dd>,<Dn>,<Dm> vsub<c>.f32 <Sd>,<Sn>,<Sm>}
+ * {@literal vsub<c>.f64 <Dd>,<Dn>,<Dm> vsub<c>.f32 <Sd>,<Sn>,<Sm>}
*/
- private String getVFPSzF64F32dnmOperands(int opcode) {
+ private String getVFPSzF64F32dnmOperands(int opcode) {
int sz = getBit(opcode, 8);
return getVFPSzF64F32Type(sz)
+ TAB + getVFPDorSReg(opcode, sz, 12, 22)
@@ -6039,7 +6293,7 @@
* @return String containing ".8", ".16" or ".32" + TAB + proper Q-or-D _d,_m reg operands
* <p><listing>
* A8.6.407 VTRN
- * {@literal vtrn<c>.<size> <Qd>,<Qm> vtrn<c>.<size> <Dd>,<Dm>}
+ * {@literal vtrn<c>.<size> <Qd>,<Qm> vtrn<c>.<size> <Dd>,<Dm>}
* A8.6.409 VUZP
* {@literal vuzp<c>.<size> <Qd>,<Qm> vuzp<c>.<size> <Dd>,<Dm>}
* A8.6.410 VZIP
@@ -6056,7 +6310,7 @@
* @return String containing ".8" ".16" or ".32" + TAB + proper Q-or-D _d,_n,_m reg operands
* <p><listing>
* A8.6.408 VTST
- * {@literal vtst<c>.<size> <Qd>,<Qn>,<Qm> vtst<c>.<size> <Dd>,<Dn>,<Dm>}
+ * {@literal vtst<c>.<size> <Qd>,<Qn>,<Qm> vtst<c>.<size> <Dd>,<Dn>,<Dm>}
*/
private String getVFPSzQorDdnmOperands(int opcode) {
return "." + getVFPDataTypeSize(opcode, 20) + getVFPQorDdnmRegs(opcode);
@@ -6070,7 +6324,7 @@
* <p><listing>
* A8.6.270 VACGE, VACGT, VACLE, VACLT
* {@literal vacge<c>.f32 <Qd>,<Qn>,<Qm> vacge<c>.f32 <Dd>,<Dn>,<Dm>}
- * {@literal vacgt<c>.f32 <Qd>,<Qn>,<Qm> vacgt<c>.f32 <Dd>,<Dn>,<Dm>}
+ * {@literal vacgt<c>.f32 <Qd>,<Qn>,<Qm> vacgt<c>.f32 <Dd>,<Dn>,<Dm>}
*/
private String getVFP_vacge_vacgt(int opcode) {
return (isBitEnabled(opcode, 21) ? "gt.f32" : "ge.f32")
@@ -6095,8 +6349,8 @@
}
/**
- * ARM--- ... D_22_22 ... Vd___15_12 ... sz___8_8 E___7_7 ...<br>
- * Thumb2 ... D_1_6_6 ... Vd_0_15_12 ... sz_0_8_8 E_0_7_7 ...
+ * ARM--- ... D_22_22 ... Vd___15_12 ... sz___8_8 E___7_7 ...<br>
+ * Thumb2 ... D_1_6_6 ... Vd_0_15_12 ... sz_0_8_8 E_0_7_7 ...
* @param opcode
* @return String containing ".f32" or ".f64" + TAB + proper D-or-S _d reg operand + ",0.0"
* <p><listing>
@@ -6110,7 +6364,7 @@
}
/**
- * ARM--- ... D_22_22 ... Vd___15_12 ... sz___8_8 . . M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_22_22 ... Vd___15_12 ... sz___8_8 . . M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 ... Vd_0_15_12 ... sz_0_8_8 . . M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper D-or-S _d,_m reg operands
@@ -6127,8 +6381,8 @@
}
/**
- * ARM--- ... D_22_22 ... op_18_18 . U_16_16 Vd___15_12 ... sf___8_8 sx___7_7 . i___5_5 . imm4___3_0<br>
- * Thumb2 ... D_1_6_6 ... op_1_2_2 . U_1_0_0 Vd_0_15_12 ... sf_0_8_8 sx_0_7_7 . i_0_5_5 . imm4_0_3_0
+ * ARM--- ... D_22_22 ... op_18_18 . U_16_16 Vd___15_12 ... sf___8_8 sx___7_7 . i___5_5 . imm4___3_0<br>
+ * Thumb2 ... D_1_6_6 ... op_1_2_2 . U_1_0_0 Vd_0_15_12 ... sf_0_8_8 sx_0_7_7 . i_0_5_5 . imm4_0_3_0
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper D-or-S _d,_d reg operands
* <p><listing>
@@ -6150,8 +6404,8 @@
}
/**
- * ARM--- ... D_22_22 imm6_21_16 Vd___15_12 ... op___8_8 0 Q___6_6 M___5_5 1 Vm___3_0<br>
- * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 0 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
+ * ARM--- ... D_22_22 imm6_21_16 Vd___15_12 ... op___8_8 0 Q___6_6 M___5_5 1 Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 0 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
* @param opcode
* @param uBit bit in the opcode containing the u (unsigned) bit
* @return String containing proper mnemonic postfix + TAB + proper Q-or-D _d,_m reg operands
@@ -6160,14 +6414,14 @@
* {@literal vcvt<c>.<Td>.<Tm> <Qd>,<Qm>,#<fbits>}
* {@literal vcvt<c>.<Td>.<Tm> <Dd>,<Dm>,#<fbits>}
*/
- private String getVFP_vcvtFpFixVecOperands(int opcode, int uBit) {
+ private String getVFP_vcvtFpFixVecOperands(int opcode, int uBit) {
return getVFPTdTm2(opcode, 8, uBit) + getVFPQorDdmRegs(opcode)
+ ",#" + (opcode >> 16 & 0x3f);
}
/**
- * ARM--- ... D_22_22 . . size_19_18 1 1 Vd___15_12 ... op___8_7 Q___6_6 M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 . . size_1_3_2 1 1 Vd_0_15_12 ... op_0_8_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 . . size_19_18 1 1 Vd___15_12 ... op___8_7 Q___6_6 M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 . . size_1_3_2 1 1 Vd_0_15_12 ... op_0_8_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing proper Td.Tm combo + TAB + proper Q-or-D _d,_m reg operands
* <p><listing>
@@ -6180,8 +6434,8 @@
}
/**
- * ARM--- ... D_22_22 ... opc2_18_16 Vd___15_12 ... sz___8_8 op___7_7 . M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 ... opc2_1_2_0 Vd_0_15_12 ... sz_0_8_8 op_0_7_7 . M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 ... opc2_18_16 Vd___15_12 ... sz___8_8 op___7_7 . M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 ... opc2_1_2_0 Vd_0_15_12 ... sz_0_8_8 op_0_7_7 . M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper D-or-S _d,_m reg operands
* <p><listing>
@@ -6203,7 +6457,7 @@
}
/**
- * ARM--- ... D_22_22 ... op_16_16 Vd___15_12 ... T___7_7 . M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_22_22 ... op_16_16 Vd___15_12 ... T___7_7 . M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 ... op_1_0_0 Vd_0_15_12 ... T_0_7_7 . M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper Sd,Sm reg operands
@@ -6219,7 +6473,7 @@
}
/**
- * ARM--- ... D_22_22 . . size_19_18 . . Vd___15_12 ... op___8_8 . . M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_22_22 . . size_19_18 . . Vd___15_12 ... op___8_8 . . M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 . . size_1_3_2 ... Vd_0_15_12 . . op_0_8_8 . . M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper Q-or-D _d,_m reg operands
@@ -6236,7 +6490,7 @@
}
/**
- * ARM--- ... b_22_22 Q_21_21 . Vd_19_16 Rt___15_12 ... D___7_7 . e___5_5 ...<br>
+ * ARM--- ... b_22_22 Q_21_21 . Vd_19_16 Rt___15_12 ... D___7_7 . e___5_5 ...<br>
* Thumb2 ... b_1_6_6 Q_1_5_5 . Vd_1_3_0 Rt_0_15_12 ... D_0_7_7 . e_0_5_5 ...
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper Q-or-D _d,Rt reg operands
@@ -6258,7 +6512,7 @@
}
/**
- * ARM--- ... D_22_22 . . imm4_19_16 Vd___15_12 ... Q___6_6 M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_22_22 . . imm4_19_16 Vd___15_12 ... Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 . . imm4_1_3_0 Vd_0_15_12 ... Q_0_6_6 M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing proper mnemonic postfix + TAB + proper Sd,Sm reg operands
@@ -6275,7 +6529,7 @@
x = imm >> 1;
} else if ((imm & 2) != 0) {
postfix = ".16";
- x = imm >> 2;
+ x = imm >> 2;
} else {
postfix = ".32";
x = imm >> 3;
@@ -6287,7 +6541,7 @@
}
/**
- * ARM--- ... D_22_22 size_21_20 Vn_19_16 Vd___15_12 0 op___10_10 L___9_9 . N___7_7 1 M___5_5 0 Vm___3_0<br>
+ * ARM--- ... D_22_22 size_21_20 Vn_19_16 Vd___15_12 0 op___10_10 L___9_9 . N___7_7 1 M___5_5 0 Vm___3_0<br>
* Thumb2 ... D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 L_0_9_9 . N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
* @param opcode
* @param quBit shift position of q-bit/u-bit in instruction
@@ -6438,7 +6692,7 @@
String mnemonic = "";
// concatenate bit 5 op field with bits 8-11 cmode field
int opCmode = ((opcode >> 1) & 0x10) | (opcode >> 8) & 0xf;
-
+
// find the instruction mnemonic
switch (opCmode) {
case 0: case 2: case 4: case 6:
@@ -6463,15 +6717,15 @@
default:
break;
}
-
+
return mnemonic + getVFPSize(opCmode);
}
/**
- * ARM--- ... D_22_22 ... imm3_18_16 Vd___15_12 cmode___11_8 . Q___6_6 . . imm4___3_0<br>
- * Thumb2 ... D_1_6_6 ... imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 . Q_0_6_6 . . imm4_0_3_0
+ * ARM--- ... D_22_22 ... imm3_18_16 Vd___15_12 cmode___11_8 . Q___6_6 . . imm4___3_0<br>
+ * Thumb2 ... D_1_6_6 ... imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 . Q_0_6_6 . . imm4_0_3_0
* @param opcode
- * @param topIBit location of the I bit to place at the top of the imm8 to be constructed
+ * @param topIBit location of the I bit to place at the top of the imm8 to be constructed
* @return String containing the full mnemonic + TAB + proper Q-or-D _d,_m reg operands
* <p><listing>
* A8.6.277 VBIC (immediate)
@@ -6491,8 +6745,8 @@
}
/**
- * ARM--- ... D_22_22 imm6_21_16 Vd___15_12 ... M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 imm6_21_16 Vd___15_12 ... M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... M_0_5_5 . Vm_0_3_0
* @param opcode
* @param uBit shift position of u-bit in instruction
* @return String containing mnemonic data type post-fix + TAB + proper Q-or-D _d,_m reg operands
@@ -6512,8 +6766,8 @@
}
/**
- * ARM--- ... D_22_22 ... Vd___15_12 ... imm___3_0<br>
- * Thumb2 ... D_1_6_6 ... Vd_0_15_12 ... imm_0_3_0
+ * ARM--- ... D_22_22 ... Vd___15_12 ... imm___3_0<br>
+ * Thumb2 ... D_1_6_6 ... Vd_0_15_12 ... imm_0_3_0
* @param opcode
* @param uBit shift position of u-bit in instruction
* @return String containing mnemonic data size post-fix + TAB + proper D-or-S <list> reg operands
@@ -6531,10 +6785,10 @@
}
/**
- * ARM--- ... D_22_22 . . size_19_18 . . Vd___15_12 ... op___7_6 M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 . . size_1_3_2 . . Vd_0_15_12 ... op_0_7_6 M_0_5_4 . Vm_0_3_0
+ * ARM--- ... D_22_22 . . size_19_18 . . Vd___15_12 ... op___7_6 M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 . . size_1_3_2 . . Vd_0_15_12 ... op_0_7_6 M_0_5_4 . Vm_0_3_0
* @param opcode
- * @return String containing mnemonic size postfix + TAB + proper Dd,Qm reg operands
+ * @return String containing mnemonic size postfix + TAB + proper Dd,Qm reg operands
* <p><listing>
* A8.6.361 VQMOVN
* vld1{@literal vqmov{u}n<c>.<type><size> <Dd>, <Qm>}
@@ -6545,8 +6799,8 @@
}
/**
- * ARM--- ... D_22_22 imm6_21_16 Vd_15_12 1 ... op___8_8 . . M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 . . M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 imm6_21_16 Vd_15_12 1 ... op___8_8 . . M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 . . M_0_5_5 . Vm_0_3_0
* @param opcode
* @param uBit shift position of u-bit in instruction
* @return String containing mnemonic postfix + TAB + proper Dd,Qm,#imm operands
@@ -6557,13 +6811,13 @@
private String getVFP_vqshl_instruction(int opcode, int uBit) {
int l = getBit(opcode, 7);
int imm = l == 1 ? opcode >> 16 & 0x3f : getVFPQImm6(opcode);
- String typeSize = getVFPQUUorSType(opcode, l, uBit, 8);
+ String typeSize = getVFPQUUorSType(opcode, l, uBit, 8);
return typeSize + TAB + getVFPQorDdmRegs(opcode) + ",#" + imm;
}
/**
- * ARM--- ... D_22_22 imm6_21_16 Vd_15_12 1 ... op___8_8 . . M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 . . M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 imm6_21_16 Vd_15_12 1 ... op___8_8 . . M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 . . M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing mnemonic postfix + TAB + proper Dd,Qm,#imm operands
* <p><listing>
@@ -6577,8 +6831,8 @@
}
/**
- * ARM--- ... D_22_22 imm6_21_16 Vd_15_12 1 ... op___8_8 . . M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 . . M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 imm6_21_16 Vd_15_12 1 ... op___8_8 . . M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... op_0_8_8 . . M_0_5_5 . Vm_0_3_0
* @param opcode
* @param uPos shift position of u-bit in instruction
* @return String containing mnemonic postfix + TAB + proper Dd,Qm,#imm operands
@@ -6597,7 +6851,7 @@
}
/**
- * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... L___7_7 Q___6_6 M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... L___7_7 Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... L_0_7_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing TAB + proper Dd,{Dn1-Dnn},Dm reg operands
@@ -6614,15 +6868,15 @@
ops += ",d" + (reg + i);
}
ops += "}," + getVFPQorDReg(opcode, 0, 0, 5);
-
+
return ops;
}
/**
- * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... L___7_7 Q___6_6 M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... L___7_7 Q___6_6 M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... L_0_7_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
* @param opcode
- * @param encoded whether immediate is in the opcode or must be derived
+ * @param encoded whether immediate is in the opcode or must be derived
* @return String containing mnemonic postfix + TAB + proper Q-or-D _d,_m,#imm operands
* <p><listing>
* A8.6.376 VRSHR
@@ -6649,27 +6903,7 @@
}
/**
- * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... L___7_7 Q___6_6 M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... L_0_7_7 Q_0_6_6 M_0_5_5 . Vm_0_3_0
- * @param opcode
- * @return String containing mnemonic postfix + TAB + proper Q-or-D _d,_m,#imm operands
- * <p><listing>
- * A8.6.387 VSLI
- * {@literal vsli<c>.<size> <Qd>,<Qm>,#<imm> vsli<c>.<size> <Dd>,<Dm>,#<imm>}
- * A8.6.390 VSRI
- * {@literal vsri<c>.<size> <Qd>,<Qm>,#<imm> vsri<c>.<size> <Dd>,<Dm>,#<imm>}
- */
-// private String getVFP_vXrX_instruction(int opcode) {
-// boolean encoded = isBitEnabled()
-// int l = opcode >> 7 & 1;
-// int imm = l == 1
-// ? (encoded ? 64 - (opcode >> 16 & 0x3f) : opcode >> 16 & 0x3f)
-// : (encoded ? getVFPImm6Encoded(opcode) : getVFPImm6(opcode));
-// return getVFPLImm6Size(opcode, l) + getVFPQorDdmRegs(opcode) + ",#" + imm;
-// }
-
- /**
- * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... M___5_5 . Vm___3_0<br>
+ * ARM--- ... D_1_6_6 imm6_1_5_0 Vd___15_12 ... M___5_5 . Vm___3_0<br>
* Thumb2 ... D_1_6_6 imm6_1_5_0 Vd_0_15_12 ... M_0_5_5 . Vm_0_3_0
* @param opcode
* @return String containing mnemonic size postfix + TAB + proper Dd,Qm,#imm operands
@@ -6686,10 +6920,10 @@
}
/**
- * ARM--- ... D_22_22 . . Rn_19_16 Vd___15_12 type___11_8 size___7_6 align___5_4 Rm___3_0<br>
- * Thumb2 ... D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
+ * ARM--- ... D_22_22 . . Rn_19_16 Vd___15_12 type___11_8 size___7_6 align___5_4 Rm___3_0<br>
+ * Thumb2 ... D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
* @param opcode
- * @return String containing
+ * @return String containing
* <p><listing>
* A8.6.308 VLD1 (single element to one lane)
* vld1{@literal <c>.<size> <list>,[<Rn>}{{@literal @<align>}}]{!}
@@ -6727,7 +6961,7 @@
* A8.6.398 VST4 (single 4-element structure from one lane)
* vst4{@literal <c>.<size> <list>,[<Rn>}{{@literal @<align>}}]{!}
* vst4{@literal <c>.<size> <list>,[<Rn>}{{@literal @<align>}}],{@literal <Rm>}
- */
+ */
private String getVFP_vXX_Xlane(int opcode) {
// careful examination of the bit patterns in the
// reference manual shows bits 8 & 9 determine
@@ -6737,7 +6971,7 @@
// bits 10 & 11 have double use: 0 - 2 means size for 1 lane, but 3 means all lanes
int sz = (opcode >> 10 & 3); // size (if not 3) for "one-lane" versions
-
+
boolean allLanes = 3 == sz;
if (allLanes)
sz = (opcode >> 6 & 3); // "all-lanes" size
@@ -6758,9 +6992,9 @@
// determine differences for "all-lanes" versions
if (allLanes) {
- boolean align = isBitEnabled(opcode, 4);
+ boolean align = isBitEnabled(opcode, 4);
spacing = getBit(opcode, 5) + 1;
-
+
index += "]";
// figure out the list member count, spacing and alignment string
@@ -6789,7 +7023,7 @@
if (ver > 1) {
spacing = sz == 0 ? 1 : getBit(ia, sz) + 1;
}
-
+
listMembers = ver;
// figure out the list member count, spacing and alignment string
@@ -6825,8 +7059,8 @@
}
/**
- * ARM--- ... D_22_22 . . Rn_19_16 Vd___15_12 type___11_8 size___7_6 align___5_4 Rm___3_0<br>
- * Thumb2 ... D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
+ * ARM--- ... D_22_22 . . Rn_19_16 Vd___15_12 type___11_8 size___7_6 align___5_4 Rm___3_0<br>
+ * Thumb2 ... D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
* @param opcode
* @return String containing mnemonic c.size postfix + TAB + all operands
* <p><listing>
@@ -6854,7 +7088,7 @@
* A8.6.397 VST4 (multiple 4-element structures)
* vst4{@literal <c>.<size> <list>,[<Rn>}{{@literal @<align>}}]{!}
* vst4{@literal <c>.<size> <list>,[<Rn>}{{@literal @<align>}}],{@literal <Rm>}
- */
+ */
private String getVFP_vXX_multi(int opcode) {
int vecReg = (getBit(opcode, 22) << 4) | (opcode >> 12 & 0xf);
int type = (opcode >> 8) & 0xf;
@@ -6964,8 +7198,8 @@
}
/**
- * ARM--- ... D_22_22 . . Rn_19_16 Vd___15_12 type___11_8 size___7_6 align___5_4 Rm___3_0<br>
- * Thumb2 ... D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
+ * ARM--- ... D_22_22 . . Rn_19_16 Vd___15_12 type___11_8 size___7_6 align___5_4 Rm___3_0<br>
+ * Thumb2 ... D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
* @param opcode
* @return String containing mnemonic post-coniditon postfix + TAB + all operands
* <p><listing>
@@ -6973,7 +7207,7 @@
* vldm{mode}{@literal <c> <Rn>}{!}{@literal <list>}
* A8.6.399 VSTM
* vstm{mode}{@literal <c> <Rn>}{!}{@literal <list>}
- */
+ */
private String getVFP_vXXm(int opcode) {
boolean is64 = isBitEnabled(opcode, 8);
return TAB + getR_16(opcode) + getW(opcode)
@@ -6981,8 +7215,8 @@
}
/**
- * ARM--- ... U_23_23 D_22_22 0 1 Rn_19_16 Vd___15_12 ... imm8___7_0<br>
- * Thumb2 ... U_1_7_7 D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 ... imm8_0_7_0
+ * ARM--- ... U_23_23 D_22_22 0 1 Rn_19_16 Vd___15_12 ... imm8___7_0<br>
+ * Thumb2 ... U_1_7_7 D_1_6_6 . . Rn_1_3_0 Vd_0_15_12 ... imm8_0_7_0
* @param opcode
* @return String containing post-condition mnemonic prefix
* + TAB + proper D-or-S reg & imm8 addressing mode operands
@@ -6999,7 +7233,7 @@
* vldr{@literal <c> <Dd>, [<Rn>}{, #+/-{@literal <imm>}}]
* A8.6.400 VSTR
* vldr{@literal <c> <Sd>, [<Rn>}{, #+/-{@literal <imm>}}]
- */
+ */
private String getVFP_vXXr(int opcode) {
int ds = getBit(opcode, 8);
return (ds == 1 ? ".64" : ".32")
@@ -7008,8 +7242,8 @@
}
/**
- * ARM--- ... D_22_22 sz_21_20 Vn_19_16 Vd___15_12 ... op___8_8 N___7_7 . M___5_5 . Vm___3_0<br>
- * Thumb2 ... D_1_6_6 sz_1_5_4 Vn_1_3_0 Vd_0_15_12 ... op_0_8_8 N_0_7_7 . M_0_5_5 . Vm_0_3_0
+ * ARM--- ... D_22_22 sz_21_20 Vn_19_16 Vd___15_12 ... op___8_8 N___7_7 . M___5_5 . Vm___3_0<br>
+ * Thumb2 ... D_1_6_6 sz_1_5_4 Vn_1_3_0 Vd_0_15_12 ... op_0_8_8 N_0_7_7 . M_0_5_5 . Vm_0_3_0
* @param opcode
* @param uBit shift position of u-bit in instruction
* @return "w" or "l" + type mnemonic postfix, a TAB,
@@ -7019,7 +7253,7 @@
* {@literal vaddl<c>.<dt> <Qd>,<Dn>,<Dm> vaddw<c>.<dt>} {{@literal <Qd>}},{@literal <Qn>,<Dm>}
* A8.6.404 VSUBL, VSUBW
* {@literal vsubl<c>.<dt> <Qd>,<Dn>,<Dm> vsubw<c>.<dt>} {{@literal <Qd>}},{@literal <Qn>,<Dm>}
- */
+ */
private String getVFP_vXXXl_vXXXw(int opcode, int uBit) {
String ops;
if (isBitEnabled(opcode, 8)) {
@@ -7054,7 +7288,7 @@
private String getR(int opcode, int bitPos) {
return isBitEnabled(opcode, bitPos) ? "r" : "";
}
-
+
private String getS(int opcode) {
return isBitEnabled(opcode, 20) ? "s" : "";
}
@@ -7062,7 +7296,7 @@
private String getW(int opcode) {
return isBitEnabled(opcode, 21) ? "!" : "";
}
-
+
private String getX(int opcode, int bitPos) {
return isBitEnabled(opcode, bitPos) ? "x" : "";
}
diff --git a/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/OpcodeARM.java b/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/OpcodeARM.java
index bde541c..3612ecc 100644
--- a/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/OpcodeARM.java
+++ b/org.eclipse.cdt.debug.edc.arm/src/org/eclipse/cdt/debug/edc/internal/arm/disassembler/OpcodeARM.java
@@ -205,8 +205,8 @@
arm_vldr__64, arm_vldr__32,
arm_vmax_vmin__int, arm_vmax_vmin__fp,
arm_vml__int, arm_vml__int_long, arm_vml__f32, arm_vml__fp, arm_vml__scalar,
- arm_vmov_vbitwise, arm_vmov__imm, arm_vmov__reg, arm_vmov__reg_f,
- arm_vmov_5, arm_vmov_6, arm_vmov_7, arm_vmov_8, arm_vmov_9,
+ arm_vmov_vbitwise, arm_vmov__imm, arm_vmov_vorr, arm_vmov__reg_f,
+ arm_vmov_5, arm_vmov_6, arm_vmov_7, arm_vmov_8, arm_vmov_9,
arm_vmovl,
arm_vmovn,
arm_vmrs,
@@ -218,7 +218,6 @@
arm_vnml,
arm_vnmul,
arm_vorn,
- arm_vorr,
arm_vpadal,
arm_vpadd__int, arm_vpadd__f32,
arm_vpaddl,
@@ -277,7 +276,8 @@
// 16-bit Thumb instructions
thumb_adc,
- thumb_add__imm, thumb_add__imm_to_sp, thumb_add__reg, thumb_add__reg_imm, thumb_add__reg_reg,
+ thumb_add__imm, thumb_add__imm_to_sp, thumb_add__reg,
+ thumb_add__reg_imm, thumb_add__reg_reg,
thumb_add__sp_imm,
thumb_adr,
thumb_and,
@@ -473,7 +473,9 @@
thumb2_vclz,
thumb2_vcmp__reg, thumb2_vcmp__to_0,
thumb2_vcnt,
- thumb2_vcvt__fp_i_vec, thumb2_vcvt__fp_i_reg, thumb2_vcvt__fp_fix_vec, thumb2_vcvt__fp_fix_reg, thumb2_vcvt__dp_sp, thumb2_vcvt__hp_sp_vec, thumb2_vcvt__hp_sp_reg,
+ thumb2_vcvt__fp_i_vec, thumb2_vcvt__fp_i_reg,
+ thumb2_vcvt__fp_fix_vec, thumb2_vcvt__fp_fix_reg,
+ thumb2_vcvt__dp_sp, thumb2_vcvt__hp_sp_vec, thumb2_vcvt__hp_sp_reg,
thumb2_vdiv,
thumb2_vdup__scalar, thumb2_vdup__reg,
thumb2_vext,
@@ -483,8 +485,10 @@
thumb2_vldm__64, thumb2_vldm__32,
thumb2_vldr__64, thumb2_vldr__32,
thumb2_vmax_vmin__int, thumb2_vmax_vmin__fp,
- thumb2_vml__int, thumb2_vml__int_long, thumb2_vml__f32, thumb2_vml__fp, thumb2_vml__scalar,
- thumb2_vmov_vbitwise, thumb2_vmov__imm, thumb2_vmov__reg, thumb2_vmov__reg_f, thumb2_vmov_5, thumb2_vmov_6, thumb2_vmov_7, thumb2_vmov_8, thumb2_vmov_9,
+ thumb2_vml__int, thumb2_vml__int_long, thumb2_vml__f32,
+ thumb2_vml__fp, thumb2_vml__scalar,
+ thumb2_vmov_vbitwise, thumb2_vmov__imm, thumb2_vmov_vorr, thumb2_vmov__reg_f,
+ thumb2_vmov_5, thumb2_vmov_6, thumb2_vmov_7, thumb2_vmov_8, thumb2_vmov_9,
thumb2_vmovl,
thumb2_vmovn,
thumb2_vmrs,
@@ -496,7 +500,6 @@
thumb2_vnml,
thumb2_vnmul,
thumb2_vorn,
- thumb2_vorr__reg,
thumb2_vpadal,
thumb2_vpadd__int, thumb2_vpadd__f32,
thumb2_vpaddl,
@@ -572,5940 +575,4587 @@
};
+ // Reference manual citations (e.g., "A8.6.67") refer to sections in the ARM Architecture
+ // Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
public static final OpcodeARM arm_opcode_table[] = {
- // NEW - Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.67 LDRD (literal)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// ldrd<c> <Rt>,<Rt2>,<label> ldrd<c> <Rt>,<Rt2>,[pc,#-0] Special case
- // xxxx000(1)x1(0)01111xxxxxxxx1101xxxx
- // must precede arm_ldrd__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx000(1)x1(0)01111xxxxxxxx1101xxxx
+ // must precede arm_ldrd__imm in table
new OpcodeARM(Index.arm_ldrd__lit, "ldrd", "xxxx000xx1x01111xxxxxxxx1101xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.66 LDRD (immediate)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// ldrd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}] ldrd<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8> ldrd<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
- // xxxx000xx1x0xxxxxxxxxxxx1101xxxx
- // must follow arm_ldrd__lit in search table
+ // must follow arm_ldrd__lit in table
new OpcodeARM(Index.arm_ldrd__imm, "ldrd", "xxxx000xx1x0xxxxxxxxxxxx1101xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.77 LDRHT
+ // Encoding A1 ARMv6T2, ARMv7
// ldrht<c> <Rt>, [<Rn>] {, #+/-<imm8>}
- // xxxx0000x111xxxxxxxxxxxx1011xxxx
- // must precede arm_ldrh__imm in search table
+ // must precede arm_ldrh__imm in table
new OpcodeARM(Index.arm_ldrht__imm, "ldrht", "xxxx0000x111xxxxxxxxxxxx1011xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.75 LDRH (literal)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrh<c> <Rt>,<label> ldrh<c> <Rt>,[pc,#-0] Special case
- // xxxx000(1)x1(0)11111xxxxxxxx1011xxxx
- // must precede arm_ldrh__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx000(1)x1(0)11111xxxxxxxx1011xxxx
+ // must precede arm_ldrh__imm in table
new OpcodeARM(Index.arm_ldrh__lit, "ldrh", "xxxx000xx1x11111xxxxxxxx1011xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.74 LDRH (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrh<c> <Rt>,[<Rn>{,#+/-<imm8>}] ldrh<c> <Rt>,[<Rn>],#+/-<imm8> ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // xxxx000xx1x1xxxxxxxxxxxx1011xxxx
- // must follow arm_ldrh__lit in search table
- // must follow arm_ldrht__imm in search table
+ // must follow arm_ldrh__lit in table
+ // must follow arm_ldrht__imm in table
new OpcodeARM(Index.arm_ldrh__imm, "ldrh", "xxxx000xx1x1xxxxxxxxxxxx1011xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.81 LDRSBT
+ // Encoding A1 ARMv6T2, ARMv7
// ldrsbt<c> <Rt>, [<Rn>] {, #+/-<imm8>}
- // xxxx0000x111xxxxxxxxxxxx1101xxxx
- // must precede arm_ldrsb__imm in search table
+ // must precede arm_ldrsb__imm in table
new OpcodeARM(Index.arm_ldrsbt__imm, "ldrsbt", "xxxx0000x111xxxxxxxxxxxx1101xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.79 LDRSB (literal)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrsb<c> <Rt>,<label> ldrsb<c> <Rt>,[pc,#-0] Special case
- // xxxx000(1)x1(0)11111xxxxxxxx1101xxxx
- // must precede arm_ldrsb__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx000(1)x1(0)11111xxxxxxxx1101xxxx
+ // must precede arm_ldrsb__imm in table
new OpcodeARM(Index.arm_ldrsb__lit, "ldrsb", "xxxx000xx1x11111xxxxxxxx1101xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.78 LDRSB (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrsb<c> <Rt>,[<Rn>{,#+/-<imm8>}] ldrsb<c> <Rt>,[<Rn>],#+/-<imm8> ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // xxxx000xx1x1xxxxxxxxxxxx1101xxxx
- // must follow arm_ldrsb__lit in search table
- // must follow arm_ldrsbt__imm in search table
+ // must follow arm_ldrsb__lit in table
+ // must follow arm_ldrsbt__imm in table
new OpcodeARM(Index.arm_ldrsb__imm, "ldrsb", "xxxx000xx1x1xxxxxxxxxxxx1101xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.85 LDRSHT
+ // Encoding A1 ARMv6T2, ARMv7
// ldrsht<c> <Rt>, [<Rn>] {, #+/-<imm8>}
- // xxxx0000x111xxxxxxxxxxxx1111xxxx
- // must precede arm_ldrsh__imm in search table
+ // must precede arm_ldrsh__imm in table
new OpcodeARM(Index.arm_ldrsht__imm, "ldrsht", "xxxx0000x111xxxxxxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.83 LDRSH (literal)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrsh<c> <Rt>,<label> ldrsh<c> <Rt>,[pc,#-0] Special case
- // xxxx000(1)x1(0)11111xxxxxxxx1111xxxx
- // must precede arm_ldrsh__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx000(1)x1(0)11111xxxxxxxx1111xxxx
+ // must precede arm_ldrsh__imm in table
new OpcodeARM(Index.arm_ldrsh__lit, "ldrsh", "xxxx000xx1x11111xxxxxxxx1111xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.82 LDRSH (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}] ldrsh<c> <Rt>,[<Rn>],#+/-<imm8> ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // xxxx000xx1x1xxxxxxxxxxxx1111xxxx
- // must follow arm_ldrsh__lit in search table
- // must follow arm_ldrsht__imm in search table
+ // must follow arm_ldrsh__lit in table
+ // must follow arm_ldrsht__imm in table
new OpcodeARM(Index.arm_ldrsh__imm, "ldrsh", "xxxx000xx1x1xxxxxxxxxxxx1111xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.200 STRD (immediate)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// strd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}] strd<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8> strd<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
- // xxxx000xx1x0xxxxxxxxxxxx1111xxxx
new OpcodeARM(Index.arm_strd__imm, "strd", "xxxx000xx1x0xxxxxxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.209 STRHT
+ // Encoding A1 ARMv6T2, ARMv7
// strht<c> <Rt>, [<Rn>] {, #+/-<imm8>}
- // xxxx0000x110xxxxxxxxxxxx1011xxxx
- // must precede arm_strh__imm in search table
+ // must precede arm_strh__imm in table
new OpcodeARM(Index.arm_strht__imm, "strht", "xxxx0000x110xxxxxxxxxxxx1011xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.207 STRH (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strh<c> <Rt>,[<Rn>{,#+/-<imm8>}] strh<c> <Rt>,[<Rn>],#+/-<imm8> strh<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // xxxx000xx1x0xxxxxxxxxxxx1011xxxx
- // must follow arm_strht__imm in search table
+ // must follow arm_strht__imm in table
new OpcodeARM(Index.arm_strh__imm, "strh", "xxxx000xx1x0xxxxxxxxxxxx1011xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.1 ADC (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// adc{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010101xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_adc__imm, "adc", "xxxx0010101xxxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.2 ADC (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// adc{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000101xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_adc__reg, "adc", "xxxx0000101xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.3 ADC (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// adc{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000101xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_adc__rsr, "adc", "xxxx0000101xxxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.10 ADR
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// adr<c> <Rd>,<label> add<c> <Rd>,pc,#<const> Alternative form
- // xxxx001010001111xxxxxxxxxxxxxxxx
- // must precede arm_add__imm in search table
+ // must precede arm_add__imm in table
new OpcodeARM(Index.arm_adr__higher, "add", "xxxx001010001111xxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.5 ADD (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// add{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010100xxxxxxxxxxxxxxxxxxxxx
- // must follow arm_adr__higher in search table
+ // A8.6.8 ADD (SP plus immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // add{s}<c> <Rd>,sp,#<const>
+ //
+ // must follow arm_adr__higher in table
new OpcodeARM(Index.arm_add__imm, "add", "xxxx0010100xxxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.6 ADD (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// add{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000100xxxxxxxxxxxxxxxx0xxxx
+ // A8.6.9 ADD (SP plus register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // add{s}<c> <Rd>,sp,<Rm>{,<shift>}
+ //
new OpcodeARM(Index.arm_add__reg, "add", "xxxx0000100xxxxxxxxxxxxxxxx0xxxx"),
-// // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
-// // A8.6.8 ADD (SP plus immediate)
-// // add{s}<c> <Rd>,sp,#<const>
-// // xxxx0010100x1101xxxxxxxxxxxxxxxx
-// SEE arm_add__imm
-// // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
-// // A8.6.9 ADD (SP plus register)
-// // add{s}<c> <Rd>,sp,<Rm>{,<shift>}
-// // xxxx0000100x1101xxxxxxxxxxx0xxxx
-// SEE arm_add__reg
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.7 ADD (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// add{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000100xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_add__rsr, "add", "xxxx0000100xxxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.11 AND (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// and{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010000xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_and__imm, "and", "xxxx0010000xxxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.12 AND (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// and{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000000xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_and__reg, "and", "xxxx0000000xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.13 AND (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// and{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000000xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_and__rsr, "and", "xxxx0000000xxxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.14 ASR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// asr{s}<c> <Rd>,<Rm>,#<imm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxxx100xxxx
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxxx100xxxx
new OpcodeARM(Index.arm_asr__imm, "asr", "xxxx0001101xxxxxxxxxxxxxx100xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.15 ASR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// asr{s}<c> <Rd>,<Rn>,<Rm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxx0101xxxx
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxx0101xxxx
new OpcodeARM(Index.arm_asr__reg, "asr", "xxxx0001101xxxxxxxxxxxxx0101xxxx"),
+ // A8.6.23 BL, BLX (immediate)
// Encoding A2 ARMv5T*, ARMv6*, ARMv7
- // A8.6.23 BL, BLX (immediate)
// blx <label>
- // 1111101xxxxxxxxxxxxxxxxxxxxxxxxx
- // must precede arm_b in search table
+ // must precede arm_b in table
new OpcodeARM(Index.arm_blx__imm, "blx", "1111101xxxxxxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.16 B
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// b<c> <label>
- // xxxx1010xxxxxxxxxxxxxxxxxxxxxxxx
- //must follow arm_blx__imm in search table
+ // must follow arm_blx__imm in table
new OpcodeARM(Index.arm_b, "b", "xxxx1010xxxxxxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.17 BFC
+ // Encoding A1 ARMv6T2, ARMv7
// bfc<c> <Rd>,#<lsb>,#<width>
- // xxxx0111110xxxxxxxxxxxxxx0011111
- // must precede arm_bfi in search table
+ // must precede arm_bfi in table
new OpcodeARM(Index.arm_bfc, "bfc", "xxxx0111110xxxxxxxxxxxxxx0011111"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.18 BFI
+ // Encoding A1 ARMv6T2, ARMv7
// bfi<c> <Rd>,<Rn>,#<lsb>,#<width>
- // xxxx0111110xxxxxxxxxxxxxx001xxxx
- // must follow arm_bfc in search table
+ // must follow arm_bfc in table
new OpcodeARM(Index.arm_bfi, "bfi", "xxxx0111110xxxxxxxxxxxxxx001xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.20 BIC (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// bic{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0001110xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_bic__reg, "bic", "xxxx0001110xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.21 BIC (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// bic{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0001110xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_bic__rsr, "bic", "xxxx0001110xxxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv5T*, ARMv6*, ARMv7
// A8.6.22 BKPT
+ // Encoding A1 ARMv5T*, ARMv6*, ARMv7
// bkpt #<imm16>
- // xxxx00010010xxxxxxxxxxxx0111xxxx
new OpcodeARM(Index.arm_bkpt, "bkpt", "xxxx00010010xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.23 BL, BLX (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// bl<c> <label>
- // xxxx1011xxxxxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_bl, "bl", "xxxx1011xxxxxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv5T*, ARMv6*, ARMv7
// A8.6.24 BLX (register)
- // blx<c> <Rm>
- // xxxx00010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0011xxxx
- new OpcodeARM(Index.arm_blx__reg, "blx", "xxxx00010010xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.25 BX
- // bx<c> Rm
- // xxxx00010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0001xxxx
- new OpcodeARM(Index.arm_bx, "bx", "xxxx00010010xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv5TEJ, ARMv6*, ARMv7
- // A8.6.26 BXJ
- // bxj<c> <Rm>
- // xxxx00010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0010xxxx
- new OpcodeARM(Index.arm_bxj, "bxj", "xxxx00010010xxxxxxxxxxxx0010xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
- // A8.6.30 CLREX
- // clrex
- // 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0001(1)(1)(1)(1)
- new OpcodeARM(Index.arm_clrex, "clrex", "111101010111xxxxxxxxxxxx0001xxxx"),
// Encoding A1 ARMv5T*, ARMv6*, ARMv7
+ // blx<c> <Rm>
+ // Unpredictable if (1) is 0: xxxx00010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0011xxxx
+ new OpcodeARM(Index.arm_blx__reg, "blx", "xxxx00010010xxxxxxxxxxxx0011xxxx"),
+ // A8.6.25 BX
+ // Encoding A1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // bx<c> Rm
+ // Unpredictable if (1) is 0: xxxx00010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0001xxxx
+ new OpcodeARM(Index.arm_bx, "bx", "xxxx00010010xxxxxxxxxxxx0001xxxx"),
+ // A8.6.26 BXJ
+ // Encoding A1 ARMv5TEJ, ARMv6*, ARMv7
+ // bxj<c> <Rm>
+ // Unpredictable if (1) is 0: xxxx00010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0010xxxx
+ new OpcodeARM(Index.arm_bxj, "bxj", "xxxx00010010xxxxxxxxxxxx0010xxxx"),
+ // A8.6.30 CLREX
+ // Encoding A1 ARMv6K, ARMv7
+ // clrex
+ // Unpredictable if (1) is 0 or (0) is 1: 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0001(1)(1)(1)(1)
+ new OpcodeARM(Index.arm_clrex, "clrex", "111101010111xxxxxxxxxxxx0001xxxx"),
// A8.6.31 CLZ
+ // Encoding A1 ARMv5T*, ARMv6*, ARMv7
// clz<c> <Rd>,<Rm>
- // xxxx00010110(1)(1)(1)(1)xxxx(1)(1)(1)(1)0001xxxx
+ // Unpredictable if (1) is 0: xxxx00010110(1)(1)(1)(1)xxxx(1)(1)(1)(1)0001xxxx
new OpcodeARM(Index.arm_clz, "clz", "xxxx00010110xxxxxxxxxxxx0001xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.33 CMN (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cmn<c> <Rn>,<Rm>{,<shift>}
- // xxxx00010111xxxx(0)(0)(0)(0)xxxxxxx0xxxx
+ // Unpredictable if (0) is 1: xxxx00010111xxxx(0)(0)(0)(0)xxxxxxx0xxxx
new OpcodeARM(Index.arm_cmn__reg, "cmn", "xxxx00010111xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.34 CMN (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cmn<c> <Rn>,<Rm>,<type> <Rs>
- // xxxx00010111xxxx(0)(0)(0)(0)xxxx0xx1xxxx
+ // Unpredictable if (0) is 1: xxxx00010111xxxx(0)(0)(0)(0)xxxx0xx1xxxx
new OpcodeARM(Index.arm_cmn__rsr, "cmn", "xxxx00010111xxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.36 CMP (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cmp<c> <Rn>,<Rm>{,<shift>}
- // xxxx00010101xxxx(0)(0)(0)(0)xxxxxxx0xxxx
+ // Unpredictable if (0) is 1: xxxx00010101xxxx(0)(0)(0)(0)xxxxxxx0xxxx
new OpcodeARM(Index.arm_cmp__reg, "cmp", "xxxx00010101xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.37 CMP (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cmp<c> <Rn>,<Rm>,<type> <Rs>
- // xxxx00010101xxxx(0)(0)(0)(0)xxxx0xx1xxxx
+ // Unpredictable if (0) is 1: xxxx00010101xxxx(0)(0)(0)(0)xxxx0xx1xxxx
new OpcodeARM(Index.arm_cmp__rsr, "cmp", "xxxx00010101xxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv7 (executes as NOP in ARMv6Kand ARMv6T2)
// A8.6.40 DBG
+ // Encoding A1 ARMv7 (executes as NOP in ARMv6Kand ARMv6T2)
// dbg<c> #<option>
- // xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)1111xxxx
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)1111xxxx
new OpcodeARM(Index.arm_dbg, "dbg", "xxxx001100100000xxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv7
// A8.6.41 DMB
+ // Encoding A1 ARMv7
// dmb #<option>
- // 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0101xxxx
+ // Unpredictable if (1) is 0 or (0) is 1: 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0101xxxx
new OpcodeARM(Index.arm_dmb, "dmb", "111101010111xxxxxxxxxxxx0101xxxx"),
- // NEW - Encoding A1 ARMv7
// A8.6.42 DSB
+ // Encoding A1 ARMv7
// dsb #<option>
- // 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0100xxxx
+ // Unpredictable if (1) is 0 or (0) is 1: 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0100xxxx
new OpcodeARM(Index.arm_dsb, "dsb", "111101010111xxxxxxxxxxxx0100xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.44 EOR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// eor{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010001xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_eor__imm, "eor", "xxxx0010001xxxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.45 EOR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// eor{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000001xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_eor__reg, "eor", "xxxx0000001xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.46 EOR (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// eor{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000001xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_eor__rsr, "eor", "xxxx0000001xxxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv7
// A8.6.49 ISB
+ // Encoding A1 ARMv7
// isb #<option>
- // 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0110xxxx
+ // Unpredictable if (1) is 0 or (0) is 1: 111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)0110xxxx
new OpcodeARM(Index.arm_isb, "isb", "111101010111xxxxxxxxxxxx0110xxxx"),
- // NEW - Encoding A1 ARMv6*, ARMv7
// B6.1.8 RFE
+ // Encoding A1 ARMv6*, ARMv7
// rfe{<amode>} <Rn>{!}
- // 1111100xx0x1xxxx(0)(0)(0)(0)(1)(0)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)
- // must precede arm_ldm__exc_ret in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 1111100xx0x1xxxx(0)(0)(0)(0)(1)(0)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)
+ // must precede arm_ldm__exc_ret in table
new OpcodeARM(Index.arm_rfe, "rfe", "1111100xx0x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// B6.1.2 LDM (exception return)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldm{<amode>}<c> <Rn>{!},<registers_with_pc>^
- // xxxx100xx1x1xxxx1xxxxxxxxxxxxxxx
- // must follow arm_rfe in search table
+ // must follow arm_rfe in table
new OpcodeARM(Index.arm_ldm__exc_ret, "ldm", "xxxx100xx1x1xxxx1xxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// B6.1.3 LDM (user registers)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldm{<amode>}<c> <Rn>,<registers_without_pc>^
- // xxxx100xx1(0)1xxxx0xxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx100xx1(0)1xxxx0xxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_ldm__user_reg, "ldm", "xxxx100xx1x1xxxx0xxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.122 POP
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// pop<c> <registers> <registers> contains more than one register
- // xxxx100010111101xxxxxxxxxxxxxxxx
- // must precede arm_ldm in search table
+ // must precede arm_ldm in table
new OpcodeARM(Index.arm_pop__regs, "pop", "xxxx100010111101xxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.53 LDM / LDMIA / LDMFD
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldm<c> <Rn>{!},<registers>
- // xxxx100010x1xxxxxxxxxxxxxxxxxxxx
- // must follow arm_pop__regs in search table
+ // must follow arm_pop__regs in table
new OpcodeARM(Index.arm_ldm, "ldm", "xxxx100010x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.54 LDMDA / LDMFA
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldmda<c> <Rn>{!},<registers>
- // xxxx100000x1xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_ldmda, "ldmda", "xxxx100000x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.55 LDMDB / LDMEA
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldmdb<c> <Rn>{!},<registers>
- // xxxx100100x1xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_ldmdb, "ldmdb", "xxxx100100x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.56 LDMIB / LDMED
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldmib<c> <Rn>{!},<registers>
- // xxxx100110x1xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_ldmib, "ldmib", "xxxx100110x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.122 POP
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// pop<c> <registers> <registers> contains one register, <Rt>
- // xxxx010010011101xxxx000000000100
- // must precede arm_ldr__imm in search table
+ // must precede arm_ldr__imm in table
new OpcodeARM(Index.arm_pop__reg, "pop", "xxxx010010011101xxxx000000000100"),
- // NEW - Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.118 PLD (literal)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// pld <label> pld [pc,#-0] Special case
- // 11110101x(1)011111(1)(1)(1)(1)xxxxxxxxxxxx
- // must precede arm_ldr__imm in search table
- // must precede arm_pld__imm in search table
+ // Unpredictable if (1) is 0: 11110101x(1)011111(1)(1)(1)(1)xxxxxxxxxxxx
+ // must precede arm_ldr__imm in table
+ // must precede arm_pld__imm in table
new OpcodeARM(Index.arm_pld__lit, "pld", "11110101xx011111xxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// A8.6.117 PLD, PLDW (immediate)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// pld{w} [<Rn>,#+/-<imm12>]
- // 11110101xx01xxxx(1)(1)(1)(1)xxxxxxxxxxxx
- // must follow arm_pld__lit in search table
- // must precede arm_ldr__imm in search table
- // must precede arm_ldrbt__imm in search table
- // must precede arm_ldrb__lit in search table
- // must precede arm_ldrb__imm in search table
+ // Unpredictable if (1) is 0: 11110101xx01xxxx(1)(1)(1)(1)xxxxxxxxxxxx
+ // must follow arm_pld__lit in table
+ // must precede arm_ldr__imm in table
+ // must precede arm_ldrbt__imm in table
+ // must precede arm_ldrb__lit in table
+ // must precede arm_ldrb__imm in table
new OpcodeARM(Index.arm_pld__imm, "pld", "11110101xx01xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv7
// A8.6.120 PLI (immediate, literal)
+ // Encoding A1 ARMv7
// pli [<Rn>,#+/-<imm12>] pli <label> pli [pc,#-0] Special case
- // 11110100x101xxxx(1)(1)(1)(1)xxxxxxxxxxxx
- // must precede arm_ldr__imm in search table
- // must precede arm_ldrbt__imm in search table
- // must precede arm_ldrb__lit in search table
- // must precede arm_ldrb__imm in search table
+ // Unpredictable if (1) is 0: 11110100x101xxxx(1)(1)(1)(1)xxxxxxxxxxxx
+ // must precede arm_ldr__imm in table
+ // must precede arm_ldrbt__imm in table
+ // must precede arm_ldrb__lit in table
+ // must precede arm_ldrb__imm in table
new OpcodeARM(Index.arm_pli__imm_lit, "pli", "11110100x101xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.86 LDRT
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrt<c> <Rt>, [<Rn>] {, #+/-<imm12>}
- // xxxx0100x011xxxxxxxxxxxxxxxxxxxx
- // must precede arm_ldr__lit in search table
- // must follow arm_pld__lit in search table
- // must follow arm_pld__imm in search table
- // must follow arm_pli__imm_lit in search table
+ // must precede arm_ldr__lit in table
+ // must follow arm_pld__lit in table
+ // must follow arm_pld__imm in table
+ // must follow arm_pli__imm_lit in table
new OpcodeARM(Index.arm_ldrt__imm, "ldrt", "xxxx0100x011xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.59 LDR (literal)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldr<c> <Rt>,<label> ldr<c> <Rt>,[pc,#-0] Special case
- // xxxx010(1)x0(0)11111xxxxxxxxxxxxxxxx
- // must precede arm_ldr__imm in search table
- // must follow arm_ldrt__imm i n search table
- // must follow arm_pld__lit in search table
- // must follow arm_pld__imm in search table
- // must follow arm_pli__imm_lit in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx010(1)x0(0)11111xxxxxxxxxxxxxxxx
+ // must precede arm_ldr__imm in table
+ // must follow arm_ldrt__imm in table
+ // must follow arm_pld__lit in table
+ // must follow arm_pld__imm in table
+ // must follow arm_pli__imm_lit in table
new OpcodeARM(Index.arm_ldr__lit, "ldr", "xxxx010xx0x11111xxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.58 LDR (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldr<c> <Rt>,[<Rn>{,#+/-<imm12>}] ldr<c> <Rt>,[<Rn>],#+/-<imm12> ldr<c> <Rt>,[<Rn>,#+/-<imm12>]!
- // xxxx010xx0x1xxxxxxxxxxxxxxxxxxxx
- // must follow arm_ldr__lit in search table
- // must follow arm_pop__reg in search table
- // must follow arm_pld__lit in search table
- // must follow arm_pld__imm in search table
- // must follow arm_pli__imm_lit in search table
+ // must follow arm_ldr__lit in table
+ // must follow arm_pop__reg in table
+ // must follow arm_pld__lit in table
+ // must follow arm_pld__imm in table
+ // must follow arm_pli__imm_lit in table
new OpcodeARM(Index.arm_ldr__imm, "ldr", "xxxx010xx0x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.86 LDRT
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrt<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx0110x011xxxxxxxxxxxxxxx0xxxx
- // must precede arm_ldr__reg in search table
+ // must precede arm_ldr__reg in table
new OpcodeARM(Index.arm_ldrt__reg, "ldrt", "xxxx0110x011xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv5TE*, ARMv6*, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// A8.6.119 PLD, PLDW (register)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// pld{w}<c> [<Rn>,+/-<Rm>{, <shift>}]
- // 11110111xx01xxxx(1)(1)(1)(1)xxxxxxx0xxxx
- // must precede arm_ldrb__reg in search table
- // must precede arm_ldrt__reg in search table
+ // Unpredictable if (1) is 0: 11110111xx01xxxx(1)(1)(1)(1)xxxxxxx0xxxx
+ // must precede arm_ldrb__reg in table
+ // must precede arm_ldrt__reg in table
new OpcodeARM(Index.arm_pld__reg, "pld", "11110111xx01xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv7
// A8.6.121 PLI (register)
+ // Encoding A1 ARMv7
// pli [<Rn>,+/-<Rm>{, <shift>}]
- // 11110110x101xxxx(1)(1)(1)(1)xxxxxxx0xxxx
- // must precede arm_ldrb__reg in search table
- // must precede arm_ldrt__reg in search table
+ // Unpredictable if (1) is 0: 11110110x101xxxx(1)(1)(1)(1)xxxxxxx0xxxx
+ // must precede arm_ldrb__reg in table
+ // must precede arm_ldrt__reg in table
new OpcodeARM(Index.arm_pli__reg, "pli", "11110110x101xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.60 LDR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldr<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} ldr<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx011xx0x1xxxxxxxxxxxxxxx0xxxx
- // must follow arm_ldrt__reg in search table
- // must follow arm_pld__reg in search table
- // must follow arm_pli__reg in search table
+ // must follow arm_ldrt__reg in table
+ // must follow arm_pld__reg in table
+ // must follow arm_pli__reg in table
new OpcodeARM(Index.arm_ldr__reg, "ldr", "xxxx011xx0x1xxxxxxxxxxxxxxx0xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.65 LDRBT
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrbt<c> <Rt>,[<Rn>],#+/-<imm12>
- // xxxx0100x111xxxxxxxxxxxxxxxxxxxx
- // must precede arm_ldrb__imm in search table
- // must follow arm_pld__imm in search table
+ // must precede arm_ldrb__imm in table
+ // must follow arm_pld__imm in table
new OpcodeARM(Index.arm_ldrbt__imm, "ldrbt", "xxxx0100x111xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.63 LDRB (literal)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrb<c> <Rt>,<label> ldrb<c> <Rt>,[pc,#-0] Special case
- // xxxx010(1)x1(0)11111xxxxxxxxxxxxxxxx
- // must precede arm_ldrb__imm in search table
- // must follow arm_pld__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx010(1)x1(0)11111xxxxxxxxxxxxxxxx
+ // must precede arm_ldrb__imm in table
+ // must follow arm_pld__imm in table
new OpcodeARM(Index.arm_ldrb__lit, "ldrb", "xxxx010xx1x11111xxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.62 LDRB (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrb<c> <Rt>,[<Rn>{,#+/-<imm12>}] ldrb<c> <Rt>,[<Rn>],#+/-<imm12> ldrb<c> <Rt>,[<Rn>,#+/-<imm12>]!
- // xxxx010xx1x1xxxxxxxxxxxxxxxxxxxx
- // must follow arm_ldrb__lit in search table
- // must follow arm_ldrbt__imm in search table
- // must follow arm_pld__imm in search table
+ // must follow arm_ldrb__lit in table
+ // must follow arm_ldrbt__imm in table
+ // must follow arm_pld__imm in table
new OpcodeARM(Index.arm_ldrb__imm, "ldrb", "xxxx010xx1x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.65 LDRBT
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrbt<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx0110x111xxxxxxxxxxxxxxx0xxxx
- // must precede arm_ldrb__reg in search table
+ // must precede arm_ldrb__reg in table
new OpcodeARM(Index.arm_ldrbt__reg, "ldrbt", "xxxx0110x111xxxxxxxxxxxxxxx0xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.64 LDRB (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrb<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} ldrb<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx011xx1x1xxxxxxxxxxxxxxx0xxxx
- // must follow arm_ldrbt__reg in search table
- // must follow arm_pld__reg in search table
+ // must follow arm_ldrbt__reg in table
+ // must follow arm_pld__reg in table
new OpcodeARM(Index.arm_ldrb__reg, "ldrb", "xxxx011xx1x1xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv6*, ARMv7
// B6.1.1 CPS
+ // Encoding A1 ARMv6*, ARMv7
// cps<effect> <iflags>{,#<mode>} cps #<mode>
- // 111100010000xxx0(0)(0)(0)(0)(0)(0)(0)xxx0xxxxx
- // must precede arm_mrs in search table
- // must precede arm_ldrd__reg in search table
+ // Unpredictable if (0) is 1: 111100010000xxx0(0)(0)(0)(0)(0)(0)(0)xxx0xxxxx
+ // must precede arm_mrs in table
+ // must precede arm_ldrd__reg in table
new OpcodeARM(Index.arm_cps, "cps", "111100010000xxx0xxxxxxxxxx0xxxxx"),
- // NEW - Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.68 LDRD (register)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// ldrd<c> <Rt>,<Rt2>,[<Rn>,+/-<Rm>]{!} ldrd<c> <Rt>,<Rt2>,[<Rn>],+/-<Rm>
- // xxxx000xx0x0xxxxxxxx(0)(0)(0)(0)1101xxxx
- //must follow arm_cps in search table
+ // Unpredictable if (0) is 1: xxxx000xx0x0xxxxxxxx(0)(0)(0)(0)1101xxxx
+ // must follow arm_cps in table
new OpcodeARM(Index.arm_ldrd__reg, "ldrd", "xxxx000xx0x0xxxxxxxxxxxx1101xxxx"),
- // NEW - Encoding A1 ARMv6*, ARMv7
// A8.6.69 LDREX
+ // Encoding A1 ARMv6*, ARMv7
// ldrex<c> <Rt>,[<Rn>]
- // xxxx00011001xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
+ // Unpredictable if (1) is 0: xxxx00011001xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
new OpcodeARM(Index.arm_ldrex, "ldrex", "xxxx00011001xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
// A8.6.70 LDREXB
+ // Encoding A1 ARMv6K, ARMv7
// ldrexb<c> <Rt>, [<Rn>]
- // xxxx00011101xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
+ // Unpredictable if (1) is 0: xxxx00011101xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
new OpcodeARM(Index.arm_ldrexb, "ldrexb", "xxxx00011101xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
// A8.6.71 LDREXD
+ // Encoding A1 ARMv6K, ARMv7
// ldrexd<c> <Rt>,<Rt2>,[<Rn>]
- // xxxx00011011xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
+ // Unpredictable if (1) is 0: xxxx00011011xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
new OpcodeARM(Index.arm_ldrexd, "ldrexd", "xxxx00011011xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
// A8.6.72 LDREXH
+ // Encoding A1 ARMv6K, ARMv7
// ldrexh<c> <Rt>, [<Rn>]
- // xxxx00011111xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
+ // Unpredictable if (1) is 0: xxxx00011111xxxxxxxx(1)(1)(1)(1)1001(1)(1)(1)(1)
new OpcodeARM(Index.arm_ldrexh, "ldrexh", "xxxx00011111xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A2 ARMv6T2, ARMv7
// A8.6.77 LDRHT
+ // Encoding A2 ARMv6T2, ARMv7
// ldrht<c> <Rt>, [<Rn>], +/-<Rm>
- // xxxx0000x011xxxxxxxx(0)(0)(0)(0)1011xxxx
- // must precede arm_ldrh__reg in search table
+ // Unpredictable if (0) is 1: xxxx0000x011xxxxxxxx(0)(0)(0)(0)1011xxxx
+ // must precede arm_ldrh__reg in table
new OpcodeARM(Index.arm_ldrht__reg, "ldrht", "xxxx0000x011xxxxxxxxxxxx1011xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.76 LDRH (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!} ldrh<c> <Rt>,[<Rn>],+/-<Rm>
- // xxxx000xx0x1xxxxxxxx(0)(0)(0)(0)1011xxxx
- // must follow arm_ldrht__reg in search table
+ // Unpredictable if (0) is 1: xxxx000xx0x1xxxxxxxx(0)(0)(0)(0)1011xxxx
+ // must follow arm_ldrht__reg in table
new OpcodeARM(Index.arm_ldrh__reg, "ldrh", "xxxx000xx0x1xxxxxxxxxxxx1011xxxx"),
- // NEW - Encoding A2 ARMv6T2, ARMv7
// A8.6.81 LDRSBT
+ // Encoding A2 ARMv6T2, ARMv7
// ldrsbt<c> <Rt>, [<Rn>], +/-<Rm>
- // xxxx0000x011xxxxxxxx(0)(0)(0)(0)1101xxxx
- // must precede arm_ldrsb__reg in search table
+ // Unpredictable if (0) is 1: xxxx0000x011xxxxxxxx(0)(0)(0)(0)1101xxxx
+ // must precede arm_ldrsb__reg in table
new OpcodeARM(Index.arm_ldrsbt__reg, "ldrsbt", "xxxx0000x011xxxxxxxxxxxx1101xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.80 LDRSB (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!} ldrsb<c> <Rt>,[<Rn>],+/-<Rm>
- // xxxx000xx0x1xxxxxxxx(0)(0)(0)(0)1101xxxx
- // must follow arm_ldrsbt__reg in search table
+ // Unpredictable if (0) is 1: xxxx000xx0x1xxxxxxxx(0)(0)(0)(0)1101xxxx
+ // must follow arm_ldrsbt__reg in table
new OpcodeARM(Index.arm_ldrsb__reg, "ldrsb", "xxxx000xx0x1xxxxxxxxxxxx1101xxxx"),
- // NEW - Encoding A2 ARMv6T2, ARMv7
// A8.6.85 LDRSHT
+ // Encoding A2 ARMv6T2, ARMv7
// ldrsht<c> <Rt>, [<Rn>], +/-<Rm>
- // xxxx0000x011xxxxxxxx(0)(0)(0)(0)1111xxxx
- // must precede arm_ldrsh__reg in search table
+ // Unpredictable if (0) is 1: xxxx0000x011xxxxxxxx(0)(0)(0)(0)1111xxxx
+ // must precede arm_ldrsh__reg in table
new OpcodeARM(Index.arm_ldrsht__reg, "ldrsht", "xxxx0000x011xxxxxxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.84 LDRSH (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!} ldrsh<c> <Rt>,[<Rn>],+/-<Rm>
- // xxxx000xx0x1xxxxxxxx(0)(0)(0)(0)1111xxxx
- // must follow arm_ldrsht__reg in search table
+ // Unpredictable if (0) is 1: xxxx000xx0x1xxxxxxxx(0)(0)(0)(0)1111xxxx
+ // must follow arm_ldrsht__reg in table
new OpcodeARM(Index.arm_ldrsh__reg, "ldrsh", "xxxx000xx0x1xxxxxxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.89 LSL (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// lsl{s}<c> <Rd>,<Rn>,<Rm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxx0001xxxx
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxx0001xxxx
new OpcodeARM(Index.arm_lsl__reg, "lsl", "xxxx0001101xxxxxxxxxxxxx0001xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.90 LSR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// lsr{s}<c> <Rd>,<Rm>,#<imm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxxx010xxxx
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxxx010xxxx
new OpcodeARM(Index.arm_lsr__imm, "lsr", "xxxx0001101xxxxxxxxxxxxxx010xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.91 LSR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// lsr{s}<c> <Rd>,<Rn>,<Rm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxx0011xxxx
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxx0011xxxx
new OpcodeARM(Index.arm_lsr__reg, "lsr", "xxxx0001101xxxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.94 MLA
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mla{s}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx0000001xxxxxxxxxxxxx1001xxxx
new OpcodeARM(Index.arm_mla, "mla", "xxxx0000001xxxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.95 MLS
+ // Encoding A1 ARMv6T2, ARMv7
// mls<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx00000110xxxxxxxxxxxx1001xxxx
new OpcodeARM(Index.arm_mls, "mls", "xxxx00000110xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.96 MOV (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mov{s}<c> <Rd>,#<const>
- // xxxx0011101x(0)(0)(0)(0)xxxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx0011101x(0)(0)(0)(0)xxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_mov__imm, "mov", "xxxx0011101xxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.97 MOV (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mov{s}<c> <Rd>,<Rm>
- // xxxx0001101x(0)(0)(0)(0)xxxx00000000xxxx
- // must precede arm_lsl__imm in search table
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxx00000000xxxx
+ // must precede arm_lsl__imm in table
new OpcodeARM(Index.arm_mov__reg, "mov", "xxxx0001101xxxxxxxxx00000000xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.88 LSL (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// lsl{s}<c> <Rd>,<Rm>,#<imm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxxx000xxxx
- // must follow arm_mov__reg in search table
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxxx000xxxx
+ // must follow arm_mov__reg in table
new OpcodeARM(Index.arm_lsl__imm, "lsl", "xxxx0001101xxxxxxxxxxxxxx000xxxx"),
- // NEW - Encoding A2 ARMv6T2, ARMv7
// A8.6.96 MOV (immediate)
+ // Encoding A2 ARMv6T2, ARMv7
// movw<c> <Rd>,#<imm16>
- // xxxx00110000xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_movw, "movw", "xxxx00110000xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.157 SETEND
+ // Encoding A1 ARMv6*, ARMv7
// setend <endian_specifier> Cannot be conditional
- // 111100010000(0)(0)(0)1(0)(0)(0)(0)(0)(0)x(0)0000(0)(0)(0)(0)
- //must precede arm_mrs in search table
+ // Unpredictable if (0) is 1: 111100010000(0)(0)(0)1(0)(0)(0)(0)(0)(0)x(0)0000(0)(0)(0)(0)
+ // must precede arm_mrs in table
new OpcodeARM(Index.arm_setend, "setend", "111100010000xxx1xxxxxxxx0000xxxx"),
-// // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
-// // B6.1.5 MRS
-// // mrs<c> <Rd>,<spec_reg>
-// // xxxx00010x00(1)(1)(1)(1)xxxx(0)(0)(0)(0)0000(0)(0)(0)(0)
-// SEE arm_mrs
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.102 MRS
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mrs<c> <Rd>,<spec_reg>
- // xxxx00010000(1)(1)(1)(1)xxxx(0)(0)(0)(0)0000(0)(0)(0)(0)
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx00010000(1)(1)(1)(1)xxxx(0)(0)(0)(0)0000(0)(0)(0)(0)
+ // B6.1.5 MRS
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // mrs<c> <Rd>,<spec_reg>
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx00010x00(1)(1)(1)(1)xxxx(0)(0)(0)(0)0000(0)(0)(0)(0)
+ //
// combined A8.6.102 MRS and B6.1.5 MRS, using the bit pattern of B6.1.5 MRS
- // must follow arm_cps in search table
- // must follow arm_setend in search table
+ // must follow arm_cps in table
+ // must follow arm_setend in table
new OpcodeARM(Index.arm_mrs, "mrs", "xxxx00010x00xxxxxxxxxxxx0000xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// A8.6.158 SEV
+ // Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// sev<c>
- // xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000100
- // must precede arm_msr__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000100
+ // must precede arm_msr__imm in table
new OpcodeARM(Index.arm_sev, "sev", "xxxx001100100000xxxxxxxx00000100"),
- // NEW - Encoding A1 ARMv6K, ARMv6T2, ARMv7
// A8.6.110 NOP
+ // Encoding A1 ARMv6K, ARMv6T2, ARMv7
// nop<c>
- // xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000000
- // must precede arm_msr__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000000
+ // must precede arm_msr__imm in table
new OpcodeARM(Index.arm_nop, "nop", "xxxx001100100000xxxxxxxx00000000"),
- // NEW - Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// A8.6.411 WFE
+ // Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// wfe<c>
- // xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000010
- // must precede arm_msr__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000010
+ // must precede arm_msr__imm in table
new OpcodeARM(Index.arm_wfe, "wfe", "xxxx001100100000xxxxxxxx00000010"),
- // NEW - Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// A8.6.412 WFI
+ // Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// wfi<c>
- // xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000011
- // must precede arm_msr__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000011
+ // must precede arm_msr__imm in table
new OpcodeARM(Index.arm_wfi, "wfi", "xxxx001100100000xxxxxxxx00000011"),
- // NEW - Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// A8.6.413 YIELD
+ // Encoding A1 ARMv6K, ARMv7 (executes as NOP in ARMv6T2)
// yield<c>
- // xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000001
- // must precede arm_msr__imm in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000001
+ // must precede arm_msr__imm in table
new OpcodeARM(Index.arm_yield, "yield", "xxxx001100100000xxxxxxxx00000001"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.104 MSR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// msr<c> <spec_reg>,<Rn>
- // xxxx00010010xx00(1)(1)(1)(1)(0)(0)(0)(0)0000xxxx
- // must precede arm_msr__sys_reg in search table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx00010010xx00(1)(1)(1)(1)(0)(0)(0)(0)0000xxxx
+ // must precede arm_msr__sys_reg in table
new OpcodeARM(Index.arm_msr__reg, "msr", "xxxx00010010xx00xxxxxxxx0000xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// B6.1.7 MSR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// msr<c> <spec_reg>,<Rn>
- // xxxx00010x10xxxx(1)(1)(1)(1)(0)(0)(0)(0)0000xxxx
- // must follow arm_msr__reg in table
+ // Unpredictable if (1) is 0 or (0) is 1: xxxx00010x10xxxx(1)(1)(1)(1)(0)(0)(0)(0)0000xxxx
+ // must follow arm_msr__reg in table in table
new OpcodeARM(Index.arm_msr__sys_reg, "msr", "xxxx00010x10xxxxxxxxxxxx0000xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.105 MUL
- // mul{s}<c> <Rd>,<Rn>,<Rm>
- // xxxx0000000xxxxx(0)(0)(0)(0)xxxx1001xxxx
- new OpcodeARM(Index.arm_mul, "mul", "xxxx0000000xxxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
- // A8.6.107 MVN (register)
- // mvn{s}<c> <Rd>,<Rm>{,<shift>}
- // xxxx0001111x(0)(0)(0)(0)xxxxxxxxxxx0xxxx
- new OpcodeARM(Index.arm_mvn__reg, "mvn", "xxxx0001111xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
- // A8.6.108 MVN (register-shifted register)
- // mvn{s}<c> <Rd>,<Rm>,<type> <Rs>
- // xxxx0001111x(0)(0)(0)(0)xxxxxxxx0xx1xxxx
- new OpcodeARM(Index.arm_mvn__rsr, "mvn", "xxxx0001111xxxxxxxxxxxxx0xx1xxxx"),
// Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // mul{s}<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (0) is 1: xxxx0000000xxxxx(0)(0)(0)(0)xxxx1001xxxx
+ new OpcodeARM(Index.arm_mul, "mul", "xxxx0000000xxxxxxxxxxxxx1001xxxx"),
+ // A8.6.107 MVN (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // mvn{s}<c> <Rd>,<Rm>{,<shift>}
+ // Unpredictable if (0) is 1: xxxx0001111x(0)(0)(0)(0)xxxxxxxxxxx0xxxx
+ new OpcodeARM(Index.arm_mvn__reg, "mvn", "xxxx0001111xxxxxxxxxxxxxxxx0xxxx"),
+ // A8.6.108 MVN (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // mvn{s}<c> <Rd>,<Rm>,<type> <Rs>
+ // Unpredictable if (0) is 1: xxxx0001111x(0)(0)(0)(0)xxxxxxxx0xx1xxxx
+ new OpcodeARM(Index.arm_mvn__rsr, "mvn", "xxxx0001111xxxxxxxxxxxxx0xx1xxxx"),
// A8.6.113 ORR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// orr{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0011100xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_orr__imm, "orr", "xxxx0011100xxxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.114 ORR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// orr{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0001100xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_orr__reg, "orr", "xxxx0001100xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.115 ORR (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// orr{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0001100xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_orr__rsr, "orr", "xxxx0001100xxxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.116 PKH
+ // Encoding A1 ARMv6*, ARMv7
// pkhbt<c> <Rd>,<Rn>,<Rm>{,lsl #<imm>} pkhtb<c> <Rd>,<Rn>,<Rm>{,asr #<imm>}
- // xxxx01101000xxxxxxxxxxxxxx01xxxx
new OpcodeARM(Index.arm_pkh, "pkh", "xxxx01101000xxxxxxxxxxxxxx01xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.124 QADD
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// qadd<c> <Rd>,<Rm>,<Rn>
- // xxxx00010000xxxxxxxx(0)(0)(0)(0)0101xxxx
+ // Unpredictable if (0) is 1: xxxx00010000xxxxxxxx(0)(0)(0)(0)0101xxxx
new OpcodeARM(Index.arm_qadd, "qadd", "xxxx00010000xxxxxxxxxxxx0101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.125 QADD16
- // qadd16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)0001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_qadd16, "qadd16", "xxxx01100010xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.126 QADD8
- // qadd8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)1001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_qadd8, "qadd8", "xxxx01100010xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.127 QASX
- // qasx<c> <Rd>,<Rn>,<Rm>
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)0011xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_qasx, "qasx", "xxxx01100010xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.128 QDADD
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// qdadd<c> <Rd>,<Rm>,<Rn>
- // xxxx00010100xxxxxxxx(0)(0)(0)(0)0101xxxx
+ // Unpredictable if (0) is 1: xxxx00010100xxxxxxxx(0)(0)(0)(0)0101xxxx
new OpcodeARM(Index.arm_qdadd, "qdadd", "xxxx00010100xxxxxxxxxxxx0101xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.129 QDSUB
- // qdsub<c> <Rd>,<Rm>,<Rn>
- // xxxx00010110xxxxxxxx(0)(0)(0)(0)0101xxxx
- new OpcodeARM(Index.arm_qdsub, "qdsub", "xxxx00010110xxxxxxxxxxxx0101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.130 QSAX
- // qsax<c> <Rd>,<Rn>,<Rm>
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)0101xxxx
-// see arm__r_dnm_math
// Encoding A1 ARMv5TE*, ARMv6*, ARMv7
+ // qdsub<c> <Rd>,<Rm>,<Rn>
+ // Unpredictable if (0) is 1: xxxx00010110xxxxxxxx(0)(0)(0)(0)0101xxxx
+ new OpcodeARM(Index.arm_qdsub, "qdsub", "xxxx00010110xxxxxxxxxxxx0101xxxx"),
// A8.6.131 QSUB
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// qsub<c> <Rd>,<Rm>,<Rn>
- // xxxx00010010xxxxxxxx(0)(0)(0)(0)0101xxxx
+ // Unpredictable if (0) is 1: xxxx00010010xxxxxxxx(0)(0)(0)(0)0101xxxx
new OpcodeARM(Index.arm_qsub, "qsub", "xxxx00010010xxxxxxxxxxxx0101xxxx"),
+ // A8.6.125 QADD16
// Encoding A1 ARMv6*, ARMv7
+ // qadd16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // A8.6.126 QADD8
+ // Encoding A1 ARMv6*, ARMv7
+ // qadd8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // A8.6.127 QASX
+ // Encoding A1 ARMv6*, ARMv7
+ // qasx<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // A8.6.130 QSAX
+ // Encoding A1 ARMv6*, ARMv7
+ // qsax<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)0101xxxx
// A8.6.132 QSUB16
- // qsub16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)0111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_qsub16, "qsub16", "xxxx01100010xxxxxxxxxxxx0111xxxx"),
// Encoding A1 ARMv6*, ARMv7
+ // qsub16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)0111xxxx
// A8.6.133 QSUB8
+ // Encoding A1 ARMv6*, ARMv7
// qsub8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)1111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_qsub8, "qsub8", "xxxx01100010xxxxxxxxxxxx1111xxxx"),
-
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)1111xxxx
+ // A8.6.148 SADD16
+ // Encoding A1 ARMv6*, ARMv7
+ // sadd16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100001xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // A8.6.149 SADD8
+ // Encoding A1 ARMv6*, ARMv7
+ // sadd8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100001xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // A8.6.150 SASX
+ // Encoding A1 ARMv6*, ARMv7
+ // sasx<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100001xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // A8.6.159 SHADD16
+ // Encoding A1 ARMv6*, ARMv7
+ // shadd16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100011xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // A8.6.160 SHADD8
+ // Encoding A1 ARMv6*, ARMv7
+ // shadd8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100011xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // A8.6.161 SHASX
+ // Encoding A1 ARMv6*, ARMv7
+ // shasx<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100011xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // A8.6.162 SHSAX
+ // Encoding A1 ARMv6*, ARMv7
+ // shsax<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100011xxxxxxxx(1)(1)(1)(1)0101xxxx
+ // A8.6.163 SHSUB16
+ // Encoding A1 ARMv6*, ARMv7
+ // shsub16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100011xxxxxxxx(1)(1)(1)(1)0111xxxx
+ // A8.6.164 SHSUB8
+ // Encoding A1 ARMv6*, ARMv7
+ // shsub8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100011xxxxxxxx(1)(1)(1)(1)1111xxxx
+ // A8.6.185 SSAX
+ // Encoding A1 ARMv6*, ARMv7
+ // ssax<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100001xxxxxxxx(1)(1)(1)(1)0101xxxx
+ // A8.6.186 SSUB16
+ // Encoding A1 ARMv6*, ARMv7
+ // ssub16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100001xxxxxxxx(1)(1)(1)(1)0111xxxx
+ // A8.6.187 SSUB8
+ // Encoding A1 ARMv6*, ARMv7
+ // ssub8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100001xxxxxxxx(1)(1)(1)(1)1111xxxx
+ // A8.6.233 UADD16
+ // Encoding A1 ARMv6*, ARMv7
+ // uadd16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100101xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // A8.6.234 UADD8
+ // Encoding A1 ARMv6*, ARMv7
+ // uadd8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100101xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // A8.6.235 UASX
+ // Encoding A1 ARMv6*, ARMv7
+ // uasx<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100101xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // A8.6.238 UHADD16
+ // Encoding A1 ARMv6*, ARMv7
+ // uhadd16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100111xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // A8.6.239 UHADD8
+ // Encoding A1 ARMv6*, ARMv7
+ // uhadd8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100111xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // A8.6.240 UHASX
+ // Encoding A1 ARMv6*, ARMv7
+ // uhasx<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100111xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // A8.6.241 UHSAX
+ // Encoding A1 ARMv6*, ARMv7
+ // uhsax<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100111xxxxxxxx(1)(1)(1)(1)0101xxxx
+ // A8.6.242 UHSUB16
+ // Encoding A1 ARMv6*, ARMv7
+ // uhsub16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100111xxxxxxxx(1)(1)(1)(1)0111xxxx
+ // A8.6.243 UHSUB8
+ // Encoding A1 ARMv6*, ARMv7
+ // uhsub8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100111xxxxxxxx(1)(1)(1)(1)1111xxxx
+ // A8.6.247 UQADD16
+ // Encoding A1 ARMv6*, ARMv7
+ // uqadd16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100110xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // A8.6.248 UQADD8
+ // Encoding A1 ARMv6*, ARMv7
+ // uqadd8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100110xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // A8.6.249 UQASX
+ // Encoding A1 ARMv6*, ARMv7
+ // uqasx<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100110xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // A8.6.250 UQSAX
+ // Encoding A1 ARMv6*, ARMv7
+ // uqsax<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100110xxxxxxxx(1)(1)(1)(1)0101xxxx
+ // A8.6.251 UQSUB16
+ // Encoding A1 ARMv6*, ARMv7
+ // uqsub16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100110xxxxxxxx(1)(1)(1)(1)0111xxxx
+ // A8.6.252 UQSUB8
+ // Encoding A1 ARMv6*, ARMv7
+ // uqsub8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100110xxxxxxxx(1)(1)(1)(1)1111xxxx
+ // A8.6.257 USAX
+ // Encoding A1 ARMv6*, ARMv7
+ // usax<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100101xxxxxxxx(1)(1)(1)(1)0101xxxx
+ // A8.6.258 USUB16
+ // Encoding A1 ARMv6*, ARMv7
+ // usub16<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100101xxxxxxxx(1)(1)(1)(1)0111xxxx
+ // A8.6.259 USUB8
+ // Encoding A1 ARMv6*, ARMv7
+ // usub8<c> <Rd>,<Rn>,<Rm>
+ // Unpredictable if (1) is 0: xxxx01100101xxxxxxxx(1)(1)(1)(1)1111xxxx
+ //
// {s|u|}{h|q|}{{add|sub}{8|16}|asx|sax}<c> <Rd>,<Rn>,<Rm>
// cond_31_28 0 1 1 0 0 hqsu_22_20 Rn_19_16 Rd_15_12 (1)(1)(1)(1) op_7_5 1 Rm_3_0
- // xxxx01100010xxxxxxxx(1)(1)(1)(1)0001xxxx
+ // Unpredictable if (1) is 0: xxxx01100010xxxxxxxx(1)(1)(1)(1)0001xxxx
new OpcodeARM(Index.arm__r_dnm_math, null, "xxxx01100xxxxxxxxxxxxxxxxxx1xxxx"),
-
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.134 RBIT
+ // Encoding A1 ARMv6T2, ARMv7
// rbit<c> <Rd>,<Rm>
- // xxxx01101111(1)(1)(1)(1)xxxx(1)(1)(1)(1)0011xxxx
+ // Unpredictable if (1) is 0: xxxx01101111(1)(1)(1)(1)xxxx(1)(1)(1)(1)0011xxxx
new OpcodeARM(Index.arm_rbit, "rbit", "xxxx01101111xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.135 REV
+ // Encoding A1 ARMv6*, ARMv7
// rev<c> <Rd>,<Rm>
- // xxxx01101011(1)(1)(1)(1)xxxx(1)(1)(1)(1)0011xxxx
+ // Unpredictable if (1) is 0: xxxx01101011(1)(1)(1)(1)xxxx(1)(1)(1)(1)0011xxxx
new OpcodeARM(Index.arm_rev, "rev", "xxxx01101011xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.136 REV16
+ // Encoding A1 ARMv6*, ARMv7
// rev16<c> <Rd>,<Rm>
- // xxxx01101011(1)(1)(1)(1)xxxx(1)(1)(1)(1)1011xxxx
+ // Unpredictable if (1) is 0: xxxx01101011(1)(1)(1)(1)xxxx(1)(1)(1)(1)1011xxxx
new OpcodeARM(Index.arm_rev16, "rev16", "xxxx01101011xxxxxxxxxxxx1011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.137 REVSH
+ // Encoding A1 ARMv6*, ARMv7
// revsh<c> <Rd>,<Rm>
- // xxxx01101111(1)(1)(1)(1)xxxx(1)(1)(1)(1)1011xxxx
+ // Unpredictable if (1) is 0: xxxx01101111(1)(1)(1)(1)xxxx(1)(1)(1)(1)1011xxxx
new OpcodeARM(Index.arm_revsh, "revsh", "xxxx01101111xxxxxxxxxxxx1011xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.141 RRX
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rrx{s}<c> <Rd>,<Rm>
- // xxxx0001101x(0)(0)(0)(0)xxxx00000110xxxx
- // must precede arm_ror__imm in search table
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxx00000110xxxx
+ // must precede arm_ror__imm in table
new OpcodeARM(Index.arm_rrx, "rrx", "xxxx0001101xxxxxxxxx00000110xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.139 ROR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ror{s}<c> <Rd>,<Rm>,#<imm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxxx110xxxx
- // must follow arm_rrx in search table
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxxx110xxxx
+ // must follow arm_rrx in table
new OpcodeARM(Index.arm_ror__imm, "ror", "xxxx0001101xxxxxxxxxxxxxx110xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.140 ROR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// ror{s}<c> <Rd>,<Rn>,<Rm>
- // xxxx0001101x(0)(0)(0)(0)xxxxxxxx0111xxxx
+ // Unpredictable if (0) is 1: xxxx0001101x(0)(0)(0)(0)xxxxxxxx0111xxxx
new OpcodeARM(Index.arm_ror__reg, "ror", "xxxx0001101xxxxxxxxxxxxx0111xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.143 RSB (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rsb{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000011xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_rsb__reg, "rsb", "xxxx0000011xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.144 RSB (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rsb{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000011xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_rsb__rsr, "rsb", "xxxx0000011xxxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.146 RSC (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rsc{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000111xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_rsc__reg, "rsc", "xxxx0000111xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.147 RSC (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rsc{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000111xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_rsc__rsr, "rsc", "xxxx0000111xxxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.148 SADD16
- // sadd16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100001xxxxxxxx(1)(1)(1)(1)0001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_sadd16, "sadd16", "xxxx01100001xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.149 SADD8
- // sadd8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100001xxxxxxxx(1)(1)(1)(1)1001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_sadd8, "sadd8", "xxxx01100001xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.150 SASX
- // sasx<c> <Rd>,<Rn>,<Rm>
- // xxxx01100001xxxxxxxx(1)(1)(1)(1)0011xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_sasx, "sasx", "xxxx01100001xxxxxxxxxxxx0011xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.152 SBC (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// sbc{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000110xxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.arm_sbc__reg, "sbc", "xxxx0000110xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.153 SBC (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// sbc{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000110xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_sbc__rsr, "sbc", "xxxx0000110xxxxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.154 SBFX
+ // Encoding A1 ARMv6T2, ARMv7
// sbfx<c> <Rd>,<Rn>,#<lsb>,#<width>
- // xxxx0111101xxxxxxxxxxxxxx101xxxx
new OpcodeARM(Index.arm_sbfx, "sbfx", "xxxx0111101xxxxxxxxxxxxxx101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.156 SEL
+ // Encoding A1 ARMv6*, ARMv7
// sel<c> <Rd>,<Rn>,<Rm>
- // xxxx01101000xxxxxxxx(1)(1)(1)(1)1011xxxx
+ // Unpredictable if (1) is 0: xxxx01101000xxxxxxxx(1)(1)(1)(1)1011xxxx
new OpcodeARM(Index.arm_sel, "sel", "xxxx01101000xxxxxxxxxxxx1011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.159 SHADD16
- // shadd16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100011xxxxxxxx(1)(1)(1)(1)0001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_shadd16, "shadd16", "xxxx01100011xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.160 SHADD8
- // shadd8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100011xxxxxxxx(1)(1)(1)(1)1001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_shadd8, "shadd8", "xxxx01100011xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.161 SHASX
- // shasx<c> <Rd>,<Rn>,<Rm>
- // xxxx01100011xxxxxxxx(1)(1)(1)(1)0011xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_shasx, "shasx", "xxxx01100011xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.162 SHSAX
- // shsax<c> <Rd>,<Rn>,<Rm>
- // xxxx01100011xxxxxxxx(1)(1)(1)(1)0101xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_shsax, "shsax", "xxxx01100011xxxxxxxxxxxx0101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.163 SHSUB16
- // shsub16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100011xxxxxxxx(1)(1)(1)(1)0111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_shsub16, "shsub16", "xxxx01100011xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.164 SHSUB8
- // shsub8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100011xxxxxxxx(1)(1)(1)(1)1111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_shsub8, "shsub8", "xxxx01100011xxxxxxxxxxxx1111xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.166 SMLABB, SMLABT, SMLATB, SMLATT
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// smla<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx00010000xxxxxxxxxxxx1xx0xxxx
new OpcodeARM(Index.arm_smla, "smla", "xxxx00010000xxxxxxxxxxxx1xx0xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.177 SMUAD
+ // Encoding A1 ARMv6*, ARMv7
// smuad{x}<c> <Rd>,<Rn>,<Rm>
- // xxxx01110000xxxx1111xxxx00x1xxxx
- // must precede arm_smlad in search table
new OpcodeARM(Index.arm_smuad, "smuad", "xxxx01110000xxxx1111xxxx00x1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.167 SMLAD
+ // Encoding A1 ARMv6*, ARMv7
// smlad{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx01110000xxxxxxxxxxxx00x1xxxx
- // must follow arm_smuad in search table
+ // must follow arm_smuad in table
new OpcodeARM(Index.arm_smlad, "smlad", "xxxx01110000xxxxxxxxxxxx00x1xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.168 SMLAL
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// smlal{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx0000111xxxxxxxxxxxxx1001xxxx
new OpcodeARM(Index.arm_smlal, "smlal", "xxxx0000111xxxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.169 SMLALBB, SMLALBT, SMLALTB, SMLALTT
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// smlal<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx00010100xxxxxxxxxxxx1xx0xxxx
new OpcodeARM(Index.arm_smlalxy, "smlal", "xxxx00010100xxxxxxxxxxxx1xx0xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.170 SMLALD
+ // Encoding A1 ARMv6*, ARMv7
// smlald{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx01110100xxxxxxxxxxxx00x1xxxx
new OpcodeARM(Index.arm_smlald, "smlald", "xxxx01110100xxxxxxxxxxxx00x1xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.171 SMLAWB, SMLAWT
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// smlaw<y><c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx00010010xxxxxxxxxxxx1x00xxxx
new OpcodeARM(Index.arm_smlaw, "smlaw", "xxxx00010010xxxxxxxxxxxx1x00xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.181 SMUSD
+ // Encoding A1 ARMv6*, ARMv7
// smusd{x}<c> <Rd>,<Rn>,<Rm>
- // xxxx01110000xxxx1111xxxx01x1xxxx
- // must precede arm_smlsd in search table
+ // must precede arm_smlsd in table
new OpcodeARM(Index.arm_smusd, "smusd", "xxxx01110000xxxx1111xxxx01x1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.172 SMLSD
+ // Encoding A1 ARMv6*, ARMv7
// smlsd{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx01110000xxxxxxxxxxxx01x1xxxx
- // must follow arm_smusd in search table
+ // must follow arm_smusd in table
new OpcodeARM(Index.arm_smlsd, "smlsd", "xxxx01110000xxxxxxxxxxxx01x1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.173 SMLSLD
+ // Encoding A1 ARMv6*, ARMv7
// smlsld{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx01110100xxxxxxxxxxxx01x1xxxx
new OpcodeARM(Index.arm_smlsld, "smlsld", "xxxx01110100xxxxxxxxxxxx01x1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.176 SMMUL
+ // Encoding A1 ARMv6*, ARMv7
// smmul{r}<c> <Rd>,<Rn>,<Rm>
- // xxxx01110101xxxx1111xxxx00x1xxxx
- // must precede arm_smmla in search table
+ // must precede arm_smmla in table
new OpcodeARM(Index.arm_smmul, "smmul", "xxxx01110101xxxx1111xxxx00x1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.174 SMMLA
+ // Encoding A1 ARMv6*, ARMv7
// smmla{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx01110101xxxxxxxxxxxx00x1xxxx
- // must follow arm_smmul in search table
+ // must follow arm_smmul in table
new OpcodeARM(Index.arm_smmla, "smmla", "xxxx01110101xxxxxxxxxxxx00x1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.175 SMMLS
+ // Encoding A1 ARMv6*, ARMv7
// smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx01110101xxxxxxxxxxxx11x1xxxx
new OpcodeARM(Index.arm_smmls, "smmls", "xxxx01110101xxxxxxxxxxxx11x1xxxx"),
- // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.178 SMULBB, SMULBT, SMULTB, SMULTT
- // smul<x><y><c> <Rd>,<Rn>,<Rm>
- // xxxx00010110xxxxxxxxxxxx1xx0xxxx
- new OpcodeARM(Index.arm_smul, "smul", "xxxx00010110xxxxxxxxxxxx1xx0xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
- // A8.6.179 SMULL
- // smull{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx0000110xxxxxxxxxxxxx1001xxxx
- new OpcodeARM(Index.arm_smull, "smull", "xxxx0000110xxxxxxxxxxxxx1001xxxx"),
// Encoding A1 ARMv5TE*, ARMv6*, ARMv7
+ // smul<x><y><c> <Rd>,<Rn>,<Rm>
+ new OpcodeARM(Index.arm_smul, "smul", "xxxx00010110xxxxxxxxxxxx1xx0xxxx"),
+ // A8.6.179 SMULL
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // smull{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ new OpcodeARM(Index.arm_smull, "smull", "xxxx0000110xxxxxxxxxxxxx1001xxxx"),
// A8.6.180 SMULWB, SMULWT
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// smulw<y><c> <Rd>,<Rn>,<Rm>
- // xxxx00010010xxxxxxxxxxxx1x10xxxx
new OpcodeARM(Index.arm_smulw, "smulw", "xxxx00010010xxxxxxxxxxxx1x10xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.183 SSAT
+ // Encoding A1 ARMv6*, ARMv7
// ssat<c> <Rd>,#<imm>,<Rn>{,<shift>}
- // xxxx0110101xxxxxxxxxxxxxxx01xxxx
new OpcodeARM(Index.arm_ssat, "ssat", "xxxx0110101xxxxxxxxxxxxxxx01xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.184 SSAT16
+ // Encoding A1 ARMv6*, ARMv7
// ssat16<c> <Rd>,#<imm>,<Rn>
- // xxxx01101010xxxxxxxx(1)(1)(1)(1)0011xxxx
+ // Unpredictable if (1) is 0: xxxx01101010xxxxxxxx(1)(1)(1)(1)0011xxxx
new OpcodeARM(Index.arm_ssat16, "ssat16", "xxxx01101010xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.185 SSAX
- // ssax<c> <Rd>,<Rn>,<Rm>
- // xxxx01100001xxxxxxxx(1)(1)(1)(1)0101xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_ssax, "ssax", "xxxx01100001xxxxxxxxxxxx0101xxxx"),
-//was new OpcodeARM(Index.arm_ssubaddx, "ssubaddx", "xxxx01100001xxxxxxxx11110101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.186 SSUB16
- // ssub16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100001xxxxxxxx(1)(1)(1)(1)0111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_ssub16, "ssub16", "xxxx01100001xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.187 SSUB8
- // ssub8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100001xxxxxxxx(1)(1)(1)(1)1111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_ssub8, "ssub8", "xxxx01100001xxxxxxxxxxxx1111xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.189 STM / STMIA / STMEA
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// stm<c> <Rn>{!},<registers>
- // must precede arm_stm__usr_regs in search table
- // xxxx100010x0xxxxxxxxxxxxxxxxxxxx
+ // must precede arm_stm__usr_regs in table
new OpcodeARM(Index.arm_stm__regs, "stm", "xxxx100010x0xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.190 STMDA / STMED
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// stmda<c> <Rn>{!},<registers>
- // xxxx100000x0xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_stmda, "stmda", "xxxx100000x0xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.123 PUSH
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// push<c> <registers> <registers> contains more than one register
- // xxxx100100101101xxxxxxxxxxxxxxxx
- // must precede arm_stmdb in search table
+ // must precede arm_stmdb in table
new OpcodeARM(Index.arm_push__regs, "push", "xxxx100100101101xxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.191 STMDB / STMFD
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// stmdb<c> <Rn>{!},<registers>
- // xxxx100100x0xxxxxxxxxxxxxxxxxxxx
- // must follow arm_push__regs in search table
+ // must follow arm_push__regs in table
new OpcodeARM(Index.arm_stmdb, "stmdb", "xxxx100100x0xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.192 STMIB / STMFA
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// stmib<c> <Rn>{!},<registers>
- // xxxx100110x0xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_stmib, "stmib", "xxxx100110x0xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.210 STRT
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strt<c> <Rt>, [<Rn>] {, +/-<imm12>}
- // xxxx0100x010xxxxxxxxxxxxxxxxxxxx
- // must precede arm_str__imm in search table
+ // must precede arm_str__imm in table
new OpcodeARM(Index.arm_strt__imm, "strt", "xxxx0100x010xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.123 PUSH
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// push<c> <registers> <registers> contains one register, <Rt>
- // xxxx010100101101xxxx000000000100
- // must precede arm_str__imm in search table
+ // must precede arm_str__imm in table
new OpcodeARM(Index.arm_push__reg, "push", "xxxx010100101101xxxx000000000100"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.194 STR (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// str<c> <Rt>,[<Rn>{,#+/-<imm12>}] str<c> <Rt>,[<Rn>],#+/-<imm12> str<c> <Rt>,[<Rn>,#+/-<imm12>]!
- // xxxx010xx0x0xxxxxxxxxxxxxxxxxxxx
- // must follow arm_strt__imm in search table
- // must follow arm_push__reg in search table
+ // must follow arm_strt__imm in table
+ // must follow arm_push__reg in table
new OpcodeARM(Index.arm_str__imm, "str", "xxxx010xx0x0xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.210 STRT
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strt<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx0110x010xxxxxxxxxxxxxxx0xxxx
- // must precede arm_str__reg in search table
+ // must precede arm_str__reg in table
new OpcodeARM(Index.arm_strt__reg, "strt", "xxxx0110x010xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.195 STR (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// str<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} str<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx011xx0x0xxxxxxxxxxxxxxx0xxxx
- // must follow arm_strt__reg in search table
+ // must follow arm_strt__reg in table
new OpcodeARM(Index.arm_str__reg, "str", "xxxx011xx0x0xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.199 STRBT
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strbt<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx0110x110xxxxxxxxxxxxxxx0xxxx
- // must precede arm_strb__reg in search table
+ // must precede arm_strb__reg in table
new OpcodeARM(Index.arm_strbt__reg, "strbt", "xxxx0110x110xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.198 STRB (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strb<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} strb<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
- // xxxx011xx1x0xxxxxxxxxxxxxxx0xxxx
- // must follow arm_strbt__reg in search table
+ // must follow arm_strbt__reg in table
new OpcodeARM(Index.arm_strb__reg, "strb", "xxxx011xx1x0xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.201 STRD (register)
+ // Encoding A1 ARMv5TE*, ARMv6*, ARMv7
// strd<c> <Rt>,<Rt2>,[<Rn>,+/-<Rm>]{!} strd<c> <Rt>,<Rt2>,[<Rn>],+/-<Rm>
- // xxxx000xx0x0xxxxxxxx(0)(0)(0)(0)1111xxxx
+ // Unpredictable if (0) is 1: xxxx000xx0x0xxxxxxxx(0)(0)(0)(0)1111xxxx
new OpcodeARM(Index.arm_strd__reg, "strd", "xxxx000xx0x0xxxxxxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv6*, ARMv7
// A8.6.202 STREX
+ // Encoding A1 ARMv6*, ARMv7
// strex<c> <Rd>,<Rt>,[<Rn>]
- // xxxx00011000xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // Unpredictable if (1) is 0: xxxx00011000xxxxxxxx(1)(1)(1)(1)1001xxxx
new OpcodeARM(Index.arm_strex, "strex", "xxxx00011000xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
// A8.6.203 STREXB
+ // Encoding A1 ARMv6K, ARMv7
// strexb<c> <Rd>,<Rt>,[<Rn>]
- // xxxx00011100xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // Unpredictable if (1) is 0: xxxx00011100xxxxxxxx(1)(1)(1)(1)1001xxxx
new OpcodeARM(Index.arm_strexb, "strexb", "xxxx00011100xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
// A8.6.204 STREXD
+ // Encoding A1 ARMv6K, ARMv7
// strexd<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
- // xxxx00011010xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // Unpredictable if (1) is 0: xxxx00011010xxxxxxxx(1)(1)(1)(1)1001xxxx
new OpcodeARM(Index.arm_strexd, "strexd", "xxxx00011010xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A1 ARMv6K, ARMv7
// A8.6.205 STREXH
+ // Encoding A1 ARMv6K, ARMv7
// strexh<c> <Rd>,<Rt>,[<Rn>]
- // xxxx00011110xxxxxxxx(1)(1)(1)(1)1001xxxx
+ // Unpredictable if (1) is 0: xxxx00011110xxxxxxxx(1)(1)(1)(1)1001xxxx
new OpcodeARM(Index.arm_strexh, "strexh", "xxxx00011110xxxxxxxxxxxx1001xxxx"),
- // NEW - Encoding A2 ARMv6T2, ARMv7
// A8.6.209 STRHT
+ // Encoding A2 ARMv6T2, ARMv7
// strht<c> <Rt>, [<Rn>], +/-<Rm>
- // xxxx0000x010xxxxxxxx(0)(0)(0)(0)1011xxxx
- // must precede arm_strh__reg in search table
+ // Unpredictable if (0) is 1: xxxx0000x010xxxxxxxx(0)(0)(0)(0)1011xxxx
+ // must precede arm_strh__reg in table
new OpcodeARM(Index.arm_strht__reg, "strht", "xxxx0000x010xxxxxxxxxxxx1011xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.208 STRH (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strh<c> <Rt>,[<Rn>,+/-<Rm>]{!} strh<c> <Rt>,[<Rn>],+/-<Rm>
- // xxxx000xx0x0xxxxxxxx(0)(0)(0)(0)1011xxxx
- // must follow arm_strht__reg in search table
+ // Unpredictable if (0) is 1: xxxx000xx0x0xxxxxxxx(0)(0)(0)(0)1011xxxx
+ // must follow arm_strht__reg in table
new OpcodeARM(Index.arm_strh__reg, "strh", "xxxx000xx0x0xxxxxxxxxxxx1011xxxx"),
-// // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
-// // A8.6.215 SUB (SP minus immediate)
-// // sub{s}<c> <Rd>,sp,#<const>
-// // xxxx0010010x1101xxxxxxxxxxxxxxxx
-// SEE arm_sub__imm
-// new OpcodeARM(Index.arm_sub__sp_imm, "sub", "xxxx0010010x1101xxxxxxxxxxxxxxxx"),
-// // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
-// // A8.6.216 SUB (SP minus register)
-// // sub{s}<c> <Rd>,sp,<Rm>{,<shift>}
-// // xxxx0000010x1101xxxxxxxxxxx0xxxx
-// SEE arm_sub__reg
-// new OpcodeARM(Index.arm_sub__sp_reg, "sub", "xxxx0000010x1101xxxxxxxxxxx0xxxx"),
- // NEW - Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.10 ADR
+ // Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// adr<c> <Rd>,<label> sub<c> <Rd>,pc,#<const> Alternative form
- // xxxx001001001111xxxxxxxxxxxxxxxx
- // must precede arm_sub__imm in search table
+ // must precede arm_sub__imm in table
new OpcodeARM(Index.arm_adr__lower, "sub", "xxxx001001001111xxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.213 SUB (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// sub{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // xxxx0000010xxxxxxxxxxxxxxxx0xxxx
+ // A8.6.216 SUB (SP minus register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // sub{s}<c> <Rd>,sp,<Rm>{,<shift>}
+ //
new OpcodeARM(Index.arm_sub__reg, "sub", "xxxx0000010xxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.214 SUB (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// sub{s}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>
- // xxxx0000010xxxxxxxxxxxxx0xx1xxxx
new OpcodeARM(Index.arm_sub__rsr, "sub", "xxxx0000010xxxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.218 SVC (previously SWI)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// svc<c> #<imm24>
- // xxxx1111xxxxxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_svc, "svc", "xxxx1111xxxxxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6* (deprecated), ARMv7 (deprecated)
// A8.6.219 SWP, SWPB
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6* (deprecated), ARMv7 (deprecated)
// swp{b}<c> <Rt>,<Rt2>,[<Rn>]
- // xxxx00010x00xxxxxxxx(0)(0)(0)(0)1001xxxx
+ // Unpredictable if (0) is 1: xxxx00010x00xxxxxxxx(0)(0)(0)(0)1001xxxx
new OpcodeARM(Index.arm_swp, "swp", "xxxx00010x00xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.223 SXTB
+ // Encoding A1 ARMv6*, ARMv7
// sxtb<c> <Rd>,<Rm>{,<rotation>}
- // xxxx011010101111xxxxxx(0)(0)0111xxxx
- // must precede arm_sxtab in search table
+ // Unpredictable if (0) is 1: xxxx011010101111xxxxxx(0)(0)0111xxxx
+ // must precede arm_sxtab in table
new OpcodeARM(Index.arm_sxtb, "sxtb", "xxxx011010101111xxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.220 SXTAB
+ // Encoding A1 ARMv6*, ARMv7
// sxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // xxxx01101010xxxxxxxxxx(0)(0)0111xxxx
- // must follow arm_sxtb in search table
+ // Unpredictable if (0) is 1: xxxx01101010xxxxxxxxxx(0)(0)0111xxxx
+ // must follow arm_sxtb in table
new OpcodeARM(Index.arm_sxtab, "sxtab", "xxxx01101010xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.224 SXTB16
+ // Encoding A1 ARMv6*, ARMv7
// sxtb16<c> <Rd>,<Rm>{,<rotation>}
- // xxxx011010001111xxxxxx(0)(0)0111xxxx
- // must precede arm_sxtab16 in search table
+ // Unpredictable if (0) is 1: xxxx011010001111xxxxxx(0)(0)0111xxxx
+ // must precede arm_sxtab16 in table
new OpcodeARM(Index.arm_sxtb16, "sxtb16", "xxxx011010001111xxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.221 SXTAB16
+ // Encoding A1 ARMv6*, ARMv7
// sxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // xxxx01101000xxxxxxxxxx(0)(0)0111xxxx
- // must follow arm_sxtb16 in search table
+ // Unpredictable if (0) is 1: xxxx01101000xxxxxxxxxx(0)(0)0111xxxx
+ // must follow arm_sxtb16 in table
new OpcodeARM(Index.arm_sxtab16, "sxtab16", "xxxx01101000xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.225 SXTH
+ // Encoding A1 ARMv6*, ARMv7
// sxth<c> <Rd>,<Rm>{,<rotation>}
- // xxxx011010111111xxxxxx(0)(0)0111xxxx
- // must precede arm_sxtah in search table
+ // Unpredictable if (0) is 1: xxxx011010111111xxxxxx(0)(0)0111xxxx
+ // must precede arm_sxtah in table
new OpcodeARM(Index.arm_sxth, "sxth", "xxxx011010111111xxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
// A8.6.222 SXTAH
+ // Encoding A1 ARMv6*, ARMv7
// sxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // xxxx01101011xxxxxxxxxx(0)(0)0111xxxx
- // must follow arm_sxth in search table
+ // Unpredictable if (0) is 1: xxxx01101011xxxxxxxxxx(0)(0)0111xxxx
+ // must follow arm_sxth in table
new OpcodeARM(Index.arm_sxtah, "sxtah", "xxxx01101011xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.227 TEQ (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// teq<c> <Rn>,#<const>
- // xxxx00110011xxxx(0)(0)(0)(0)xxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx00110011xxxx(0)(0)(0)(0)xxxxxxxxxxxx
new OpcodeARM(Index.arm_teq__imm, "teq", "xxxx00110011xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.228 TEQ (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// teq<c> <Rn>,<Rm>{,<shift>}
- // xxxx00010011xxxx(0)(0)(0)(0)xxxxxxx0xxxx
+ // Unpredictable if (0) is 1: xxxx00010011xxxx(0)(0)(0)(0)xxxxxxx0xxxx
new OpcodeARM(Index.arm_teq__reg, "teq", "xxxx00010011xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.229 TEQ (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// teq<c> <Rn>,<Rm>,<type> <Rs>
- // xxxx00010011xxxx(0)(0)(0)(0)xxxx0xx1xxxx
+ // Unpredictable if (0) is 1: xxxx00010011xxxx(0)(0)(0)(0)xxxx0xx1xxxx
new OpcodeARM(Index.arm_teq__rsr, "teq", "xxxx00010011xxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.230 TST (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// tst<c> <Rn>,#<const>
- // xxxx00110001xxxx(0)(0)(0)(0)xxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx00110001xxxx(0)(0)(0)(0)xxxxxxxxxxxx
new OpcodeARM(Index.arm_tst__imm, "tst", "xxxx00110001xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.231 TST (register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// tst<c> <Rn>,<Rm>{,<shift>}
- // xxxx00010001xxxx(0)(0)(0)(0)xxxxxxx0xxxx
+ // Unpredictable if (0) is 1: xxxx00010001xxxx(0)(0)(0)(0)xxxxxxx0xxxx
new OpcodeARM(Index.arm_tst__reg, "tst", "xxxx00010001xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.232 TST (register-shifted register)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// tst<c> <Rn>,<Rm>,<type> <Rs>
- // xxxx00010001xxxx(0)(0)(0)(0)xxxx0xx1xxxx
+ // Unpredictable if (0) is 1: xxxx00010001xxxx(0)(0)(0)(0)xxxx0xx1xxxx
new OpcodeARM(Index.arm_tst__rsr, "tst", "xxxx00010001xxxxxxxxxxxx0xx1xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.233 UADD16
- // uadd16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100101xxxxxxxx(1)(1)(1)(1)0001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uadd16, "uadd16", "xxxx01100101xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.234 UADD8
- // uadd8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100101xxxxxxxx(1)(1)(1)(1)1001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uadd8, "uadd8", "xxxx01100101xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.235 UASX
- // uasx<c> <Rd>,<Rn>,<Rm>
- // xxxx01100101xxxxxxxx(1)(1)(1)(1)0011xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uasx, "uasx", "xxxx01100101xxxxxxxxxxxx0011xxxx"),
-//was new OpcodeARM(Index.arm_uaddsubx, "uaddsubx", "xxxx01100101xxxxxxxx11110011xxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.236 UBFX
+ // Encoding A1 ARMv6T2, ARMv7
// ubfx<c> <Rd>,<Rn>,#<lsb>,#<width>
- // xxxx0111111xxxxxxxxxxxxxx101xxxx
new OpcodeARM(Index.arm_ubfx, "ubfx", "xxxx0111111xxxxxxxxxxxxxx101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.238 UHADD16
- // uhadd16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100111xxxxxxxx(1)(1)(1)(1)0001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uhadd16, "uhadd16", "xxxx01100111xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.239 UHADD8
- // uhadd8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100111xxxxxxxx(1)(1)(1)(1)1001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uhadd8, "uhadd8", "xxxx01100111xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.240 UHASX
- // uhasx<c> <Rd>,<Rn>,<Rm>
- // xxxx01100111xxxxxxxx(1)(1)(1)(1)0011xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uhasx, "uhasx", "xxxx01100111xxxxxxxxxxxx0011xxxx"),
-//was new OpcodeARM(Index.arm_uhaddsubx, "uhaddsubx", "xxxx01100111xxxxxxxx11110011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.241 UHSAX
- // uhsax<c> <Rd>,<Rn>,<Rm>
- // xxxx01100111xxxxxxxx(1)(1)(1)(1)0101xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uhsax, "uhsax", "xxxx01100111xxxxxxxxxxxx0101xxxx"),
-//was new OpcodeARM(Index.arm_uhsubaddx, "uhsubaddx", "xxxx01100111xxxxxxxx11110101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.242 UHSUB16
- // uhsub16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100111xxxxxxxx(1)(1)(1)(1)0111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uhsub16, "uhsub16", "xxxx01100111xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.243 UHSUB8
- // uhsub8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100111xxxxxxxx(1)(1)(1)(1)1111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uhsub8, "uhsub8", "xxxx01100111xxxxxxxxxxxx1111xxxx"),
- // NEW - Encoding A1 ARMv6*, ARMv7
// A8.6.244 UMAAL
+ // Encoding A1 ARMv6*, ARMv7
// umaal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx00000100xxxxxxxxxxxx1001xxxx
new OpcodeARM(Index.arm_umaal, "umaal", "xxxx00000100xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.245 UMLAL
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// umlal{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx0000101xxxxxxxxxxxxx1001xxxx
new OpcodeARM(Index.arm_umlal, "umlal", "xxxx0000101xxxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.246 UMULL
- // umull{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // xxxx0000100xxxxxxxxxxxxx1001xxxx
- new OpcodeARM(Index.arm_umull, "umull", "xxxx0000100xxxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.247 UQADD16
- // uqadd16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100110xxxxxxxx(1)(1)(1)(1)0001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uqadd16, "uqadd16", "xxxx01100110xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.248 UQADD8
- // uqadd8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100110xxxxxxxx(1)(1)(1)(1)1001xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uqadd8, "uqadd8", "xxxx01100110xxxxxxxxxxxx1001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.249 UQASX
- // uqasx<c> <Rd>,<Rn>,<Rm>
- // xxxx01100110xxxxxxxx(1)(1)(1)(1)0011xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uqasx, "uqasx", "xxxx01100110xxxxxxxxxxxx0011xxxx"),
-//was new OpcodeARM(Index.arm_uqaddsubx, "uqaddsubx", "xxxx01100110xxxxxxxx11110011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.250 UQSAX
- // uqsax<c> <Rd>,<Rn>,<Rm>
- // xxxx01100110xxxxxxxx(1)(1)(1)(1)0101xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uqsax, "uqsax", "xxxx01100110xxxxxxxxxxxx0101xxxx"),
-//was new OpcodeARM(Index.arm_uqsubaddx, "uqsubaddx", "xxxx01100110xxxxxxxx11110101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.251 UQSUB16
- // uqsub16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100110xxxxxxxx(1)(1)(1)(1)0111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uqsub16, "uqsub16", "xxxx01100110xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.252 UQSUB8
- // uqsub8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100110xxxxxxxx(1)(1)(1)(1)1111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_uqsub8, "uqsub8", "xxxx01100110xxxxxxxxxxxx1111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.253 USAD8
- // usad8<c> <Rd>,<Rn>,<Rm>
- // xxxx01111000xxxx1111xxxx0001xxxx
- // must precede arm_usada8 in search table
- new OpcodeARM(Index.arm_usad8, "usad8", "xxxx01111000xxxx1111xxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.254 USADA8
- // usada8<c> <Rd>,<Rn>,<Rm>,<Ra>
- // xxxx01111000xxxxxxxxxxxx0001xxxx
- // must follow arm_usad8 in search table
- new OpcodeARM(Index.arm_usada8, "usada8", "xxxx01111000xxxxxxxxxxxx0001xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.255 USAT
- // usat<c> <Rd>,#<imm5>,<Rn>{,<shift>}
- // xxxx0110111xxxxxxxxxxxxxxx01xxxx
- new OpcodeARM(Index.arm_usat, "usat", "xxxx0110111xxxxxxxxxxxxxxx01xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.256 USAT16
- // usat16<c> <Rd>,#<imm4>,<Rn>
- // xxxx01101110xxxxxxxx(1)(1)(1)(1)0011xxxx
- new OpcodeARM(Index.arm_usat16, "usat16", "xxxx01101110xxxxxxxxxxxx0011xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.257 USAX
- // usax<c> <Rd>,<Rn>,<Rm>
- // xxxx01100101xxxxxxxx(1)(1)(1)(1)0101xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_usax, "usax", "xxxx01100101xxxxxxxxxxxx0101xxxx"),
-//was new OpcodeARM(Index.arm_usubaddx, "usubaddx", "xxxx01100101xxxxxxxx11110101xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.258 USUB16
- // usub16<c> <Rd>,<Rn>,<Rm>
- // xxxx01100101xxxxxxxx(1)(1)(1)(1)0111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_usub16, "usub16", "xxxx01100101xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.259 USUB8
- // usub8<c> <Rd>,<Rn>,<Rm>
- // xxxx01100101xxxxxxxx(1)(1)(1)(1)1111xxxx
-// see arm__r_dnm_math
-// new OpcodeARM(Index.arm_usub8, "usub8", "xxxx01100101xxxxxxxxxxxx1111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.263 UXTB
- // uxtb<c> <Rd>,<Rm>{,<rotation>}
- // xxxx011011101111xxxxxx(0)(0)0111xxxx
- // must precede arm_uxtab in search table
- new OpcodeARM(Index.arm_uxtb, "uxtb", "xxxx011011101111xxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.260 UXTAB
- // uxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // xxxx01101110xxxxxxxxxx(0)(0)0111xxxx
- // must follow arm_uxtb in search table
- new OpcodeARM(Index.arm_uxtab, "uxtab", "xxxx01101110xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.264 UXTB16
- // uxtb16<c> <Rd>,<Rm>{,<rotation>}
- // xxxx011011001111xxxxxx(0)(0)0111xxxx
- // must precede arm_uxtab16 in search table
- new OpcodeARM(Index.arm_uxtb16, "uxtb16", "xxxx011011001111xxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.261 UXTAB16
- // uxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // xxxx01101100xxxxxxxxxx(0)(0)0111xxxx
- // must follow arm_uxtb16 in search table
- new OpcodeARM(Index.arm_uxtab16, "uxtab16", "xxxx01101100xxxxxxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.265 UXTH
- // uxth<c> <Rd>,<Rm>{,<rotation>}
- // xxxx011011111111xxxxxx(0)(0)0111xxxx
- // must precede arm_uxtah in search table
- new OpcodeARM(Index.arm_uxth, "uxth", "xxxx011011111111xxxxxxxx0111xxxx"),
- // Encoding A1 ARMv6*, ARMv7
- // A8.6.262 UXTAH
- // uxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // xxxx01101111xxxxxxxxxx(0)(0)0111xxxx
- // must follow arm_uxth in search table
- new OpcodeARM(Index.arm_uxtah, "uxtah", "xxxx01101111xxxxxxxxxxxx0111xxxx"),
- // NEW - Encoding A1 Security Extensions
- // B6.1.9 SMC (previously SMI)
- // smc<c> #<imm4>
- // xxxx00010110(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)0111xxxx
- new OpcodeARM(Index.arm_smc, "smc", "xxxx00010110xxxxxxxxxxxx0111xxxx"),
- // NEW - Encoding A1 ARMv6*, ARMv7
- // B6.1.10 SRS
- // srs{<amode>} sp{!},#<mode>
- // 1111100xx1x0(1)(1)(0)(1)(0)(0)(0)(0)(0)(1)(0)(1)(0)(0)(0)xxxxx
- new OpcodeARM(Index.arm_srs, "srs", "1111100xx1x0xxxxxxxxxxxxxxxxxxxx"),
// Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // umull{s}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
+ new OpcodeARM(Index.arm_umull, "umull", "xxxx0000100xxxxxxxxxxxxx1001xxxx"),
+ // A8.6.253 USAD8
+ // Encoding A1 ARMv6*, ARMv7
+ // usad8<c> <Rd>,<Rn>,<Rm>
+ // must precede arm_usada8 in table
+ new OpcodeARM(Index.arm_usad8, "usad8", "xxxx01111000xxxx1111xxxx0001xxxx"),
+ // A8.6.254 USADA8
+ // Encoding A1 ARMv6*, ARMv7
+ // usada8<c> <Rd>,<Rn>,<Rm>,<Ra>
+ // must follow arm_usad8 in table
+ new OpcodeARM(Index.arm_usada8, "usada8", "xxxx01111000xxxxxxxxxxxx0001xxxx"),
+ // A8.6.255 USAT
+ // Encoding A1 ARMv6*, ARMv7
+ // usat<c> <Rd>,#<imm5>,<Rn>{,<shift>}
+ new OpcodeARM(Index.arm_usat, "usat", "xxxx0110111xxxxxxxxxxxxxxx01xxxx"),
+ // A8.6.256 USAT16
+ // Encoding A1 ARMv6*, ARMv7
+ // usat16<c> <Rd>,#<imm4>,<Rn>
+ // Unpredictable if (1) is 0: xxxx01101110xxxxxxxx(1)(1)(1)(1)0011xxxx
+ new OpcodeARM(Index.arm_usat16, "usat16", "xxxx01101110xxxxxxxxxxxx0011xxxx"),
+ // A8.6.263 UXTB
+ // Encoding A1 ARMv6*, ARMv7
+ // uxtb<c> <Rd>,<Rm>{,<rotation>}
+ // Unpredictable if (0) is 1: xxxx011011101111xxxxxx(0)(0)0111xxxx
+ // must precede arm_uxtab in table
+ new OpcodeARM(Index.arm_uxtb, "uxtb", "xxxx011011101111xxxxxxxx0111xxxx"),
+ // A8.6.260 UXTAB
+ // Encoding A1 ARMv6*, ARMv7
+ // uxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ // Unpredictable if (0) is 1: xxxx01101110xxxxxxxxxx(0)(0)0111xxxx
+ // must follow arm_uxtb in table
+ new OpcodeARM(Index.arm_uxtab, "uxtab", "xxxx01101110xxxxxxxxxxxx0111xxxx"),
+ // A8.6.264 UXTB16
+ // Encoding A1 ARMv6*, ARMv7
+ // uxtb16<c> <Rd>,<Rm>{,<rotation>}
+ // Unpredictable if (0) is 1: xxxx011011001111xxxxxx(0)(0)0111xxxx
+ // must precede arm_uxtab16 in table
+ new OpcodeARM(Index.arm_uxtb16, "uxtb16", "xxxx011011001111xxxxxxxx0111xxxx"),
+ // A8.6.261 UXTAB16
+ // Encoding A1 ARMv6*, ARMv7
+ // uxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ // Unpredictable if (0) is 1: xxxx01101100xxxxxxxxxx(0)(0)0111xxxx
+ // must follow arm_uxtb16 in table
+ new OpcodeARM(Index.arm_uxtab16, "uxtab16", "xxxx01101100xxxxxxxxxxxx0111xxxx"),
+ // A8.6.265 UXTH
+ // Encoding A1 ARMv6*, ARMv7
+ // uxth<c> <Rd>,<Rm>{,<rotation>}
+ // Unpredictable if (0) is 1: xxxx011011111111xxxxxx(0)(0)0111xxxx
+ // must precede arm_uxtah in table
+ new OpcodeARM(Index.arm_uxth, "uxth", "xxxx011011111111xxxxxxxx0111xxxx"),
+ // A8.6.262 UXTAH
+ // Encoding A1 ARMv6*, ARMv7
+ // uxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
+ // Unpredictable if (0) is 1: xxxx01101111xxxxxxxxxx(0)(0)0111xxxx
+ // must follow arm_uxth in table
+ new OpcodeARM(Index.arm_uxtah, "uxtah", "xxxx01101111xxxxxxxxxxxx0111xxxx"),
+ // B6.1.9 SMC (previously SMI)
+ // Encoding A1 Security Extensions
+ // smc<c> #<imm4>
+ // Unpredictable if (0) is 1: xxxx00010110(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)0111xxxx
+ new OpcodeARM(Index.arm_smc, "smc", "xxxx00010110xxxxxxxxxxxx0111xxxx"),
+ // B6.1.10 SRS
+ // Encoding A1 ARMv6*, ARMv7
+ // srs{<amode>} sp{!},#<mode>
+ // Unpredictable if (1) is 0 or (0) is 1: 1111100xx1x0(1)(1)(0)(1)(0)(0)(0)(0)(0)(1)(0)(1)(0)(0)(0)xxxxx
+ new OpcodeARM(Index.arm_srs, "srs", "1111100xx1x0xxxxxxxxxxxxxxxxxxxx"),
// B6.1.11 STM (user registers)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// stm{amode}<c> <Rn>,<registers>^
- // xxxx100xx1(0)0xxxxxxxxxxxxxxxxxxxx
- // must follow arm_stm__regs in search table
+ // Unpredictable if (0) is 1: xxxx100xx1(0)0xxxxxxxxxxxxxxxxxxxx
+ // must follow arm_stm__regs in table
new OpcodeARM(Index.arm_stm__usr_regs, "stm", "xxxx100xx1x0xxxxxxxxxxxxxxxxxxxx"),
// VFP and Advanced SIMD instructions
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.266 VABA, VABAL
+ // Encoding A1 / T1 Advanced SIMD
// vaba<c>.<dt> <Qd>, <Qn>, <Qm> vaba<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0111xxx1xxxx
new OpcodeARM(Index.arm_vaba, "vaba", "1111001x0xxxxxxxxxxx0111xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.281 VCEQ (immediate #0)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vceq<c>.<dt> <Qd>, <Qm>, #0 vceq<c>.<dt> <Dd>, <Dm>, #0
- // 111100111x11xx01xxxx0x010xx0xxxx
- // must precede arm_vabal
- // must precede arm_vaddl_vaddw
+ // must precede arm_vabal in table
+ // must precede arm_vaddl_vaddw in table
new OpcodeARM(Index.arm_vceq__imm0, "vceq", "111100111x11xx01xxxx0x010xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.287 VCLE (immediate #0)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vcle<c>.<dt> <Qd>, <Qm>, #0 vcle<c>.<dt> <Dd>, <Dm>, #0
- // 111100111x11xx01xxxx0x011xx0xxxx
- // must precede arm_vabal
- // must precede arm_vaddl_vaddw
+ // must precede arm_vabal in table
+ // must precede arm_vaddl_vaddw in table
new OpcodeARM(Index.arm_vcle, "vcle", "111100111x11xx01xxxx0x011xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.293 VCNT
+ // Encoding A1 / T1 Advanced SIMD
// vcnt<c>.8 <Qd>, <Qm> vcnt<c>.8 <Dd>, <Dm>
- // 111100111x11xx00xxxx01010xx0xxxx
- // must precede arm_vabal
+ // must precede arm_vabal in table
new OpcodeARM(Index.arm_vcnt, "vcnt", "111100111x11xx00xxxx01010xx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.267 VABD, VABDL (integer)
+ // Encoding A1 / T1 Advanced SIMD
// vabd<c>.<dt> <Qd>, <Qn>, <Qm> vabd<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0111xxx0xxxx
new OpcodeARM(Index.arm_vabd__int, "vabd", "1111001x0xxxxxxxxxxx0111xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variant)
// A8.6.269 VABS
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variant)
// vabs<c>.<dt> <Qd>, <Qm> vabs<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx01xxxx0x110xx0xxxx
- // must precede arm_vabdl
+ // must precede arm_vabdl in table
new OpcodeARM(Index.arm_vabs, "vabs", "111100111x11xx01xxxx0x110xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.294 VCVT (between floating-point and integer, Advanced SIMD)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vcvt<c>.<Td>.<Tm> <Qd>, <Qm> vcvt<c>.<Td>.<Tm> <Dd>, <Dm>
- // 111100111x11xx11xxxx011xxxx0xxxx
- // must precede arm_vabdl
+ // must precede arm_vabdl in table
new OpcodeARM(Index.arm_vcvt__fp_i_vec, "vcvt", "111100111x11xx11xxxx011xxxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD with half-precision extensions (UNDEFINED in integer-only variant)
// A8.6.299 VCVT (between half-precision and single-precision, Advanced SIMD)
+ // Encoding A1 / T1 Advanced SIMD with half-precision extensions (UNDEFINED in integer-only variant)
// vcvt<c>.f32.f16 <Qd>, <Dm> vcvt<c>.f16.f32 <Dd>, <Qm>
- // 111100111x11xx10xxxx011x00x0xxxx
- // must precede arm_vabdl
+ // must precede arm_vabdl in table
new OpcodeARM(Index.arm_vcvt__hp_sp_vec, "vcvt", "111100111x11xx10xxxx011x00x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.342 VNEG
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vneg<c>.<dt> <Qd>, <Qm> vneg<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx01xxxx0x111xx0xxxx
- // must precede arm_vabdl
- // must precede arm_vmlal
- // must precede arm_vmlsl
+ // must precede arm_vabdl in table
+ // must precede arm_vmlal in table
+ // must precede arm_vmlsl in table
new OpcodeARM(Index.arm_vneg, "vneg", "111100111x11xx01xxxx0x111xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.356 VQABS
+ // Encoding A1 / T1 Advanced SIMD
// vqabs<c>.<dt> <Qd>,<Qm> vqabs<c>.<dt> <Dd>,<Dm>
- // 111100111x11xx00xxxx01110xx0xxxx
- // must precede arm_vabdl
- // must precede arm_vmlal
+ // must precede arm_vabdl in table
+ // must precede arm_vmlal in table
new OpcodeARM(Index.arm_vqabs, "vqabs", "111100111x11xx00xxxx01110xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.362 VQNEG
+ // Encoding A1 / T1 Advanced SIMD
// vqneg<c>.<dt> <Qd>,<Qm> vqneg<c>.<dt> <Dd>,<Dm>
- // 111100111x11xx00xxxx01111xx0xxxx
- // must precede arm_vabdl
- // must precede arm_vmlsl
+ // must precede arm_vabdl in table
+ // must precede arm_vmlsl in table
new OpcodeARM(Index.arm_vqneg, "vqneg", "111100111x11xx00xxxx01111xx0xxxx"),
- // NEW - Encoding A2 Advanced SIMD
// A8.6.267 VABD, VABDL (integer)
+ // Encoding A2 Advanced SIMD
// vabdl<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1111001x1xxxxxxxxxxx0111x0x0xxxx
- // must follow arm_vabs
- // must follow arm_vcvt__fp_i_vec
- // must follow arm_vcvt__hp_sp_vec
- // must follow arm_vneg
- // must follow arm_vqabs
- // must follow arm_vqneg
+ // must follow arm_vabs in table
+ // must follow arm_vcvt__fp_i_vec in table
+ // must follow arm_vcvt__hp_sp_vec in table
+ // must follow arm_vneg in table
+ // must follow arm_vqabs in table
+ // must follow arm_vqneg in table
new OpcodeARM(Index.arm_vabdl, "vabdl", "1111001x1xxxxxxxxxxx0111x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.268 VABD (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vabd<c>.f32 <Qd>, <Qn>, <Qm> vabd<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110x1xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.arm_vabd__f32, "vabd", "111100110x1xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.269 VABS
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vabs<c>.f64 <Dd>, <Dm> vabs<c>.f32 <Sd>, <Sm>
- // xxxx11101x110000xxxx101x11x0xxxx
new OpcodeARM(Index.arm_vabs__f, "vabs", "xxxx11101x110000xxxx101x11x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.270 VACGE, VACGT, VACLE, VACLT
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vacge<c>.f32 <Qd>, <Qn>, <Qm> vacge<c>.f32 <Dd>, <Dn>, <Dm>
// vacgt<c>.f32 <Qd>, <Qn>, <Qm> vacgt<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110xxxxxxxxxxx1110xxx1xxxx
new OpcodeARM(Index.arm_vacge_vacgt, "vac", "111100110xxxxxxxxxxx1110xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.271 VADD (integer)
+ // Encoding A1 / T1 Advanced SIMD
// vadd<c>.<dt> <Qd>, <Qn>, <Qm> vadd<c>.<dt> <Dd>, <Dn>, <Dm>
- // 111100100xxxxxxxxxxx1000xxx0xxxx
new OpcodeARM(Index.arm_vadd__int, "vadd", "111100100xxxxxxxxxxx1000xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variants)
// A8.6.272 VADD (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variants)
// vadd<c>.f32 <Qd>, <Qn>, <Qm> vadd<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100x0xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.arm_vadd__f32, "vadd", "111100100x0xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.272 VADD (floating-point)
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vadd<c>.f64 <Dd>, <Dn>, <Dm> vadd<c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11100x11xxxxxxxx101xx0x0xxxx
new OpcodeARM(Index.arm_vadd__fp_f, "vadd", "xxxx11100x11xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.305 VEXT
+ // Encoding A1 / T1 Advanced SIMD
// vext<c>.8 <Qd>, <Qn>, <Qm>, #<imm> vext<c>.8 <Dd>, <Dn>, <Dm>, #<imm>
- // 111100101x11xxxxxxxxxxxxxxx0xxxx
- // must precede arm_vabal
- // must precede arm_vaddhn
+ // must precede arm_vabal in table
+ // must precede arm_vaddhn in table
new OpcodeARM(Index.arm_vext, "vext", "111100101x11xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.273 VADDHN
+ // Encoding A1 / T1 Advanced SIMD
// vaddhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 111100101xxxxxxxxxxx0100x0x0xxxx
- // must follow arm_vext
+ // must follow arm_vext in table
new OpcodeARM(Index.arm_vaddhn, "vaddhn", "111100101xxxxxxxxxxx0100x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.283 VCGE (immediate #0)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vcge<c>.<dt> <Qd>, <Qm>, #0 vcge<c>.<dt> <Dd>, <Dm>, #0
- // 111100111x11xx01xxxx0x001xx0xxxx
- // must precede arm_vaddl_vaddw
+ // must precede arm_vaddl_vaddw in table
new OpcodeARM(Index.arm_vcge__imm0, "vcge", "111100111x11xx01xxxx0x001xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.285 VCGT (immediate #0)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vcgt<c>.<dt> <Qd>, <Qm>, #0 vcgt<c>.<dt> <Dd>, <Dm>, #0
- // 111100111x11xx01xxxx0x000xx0xxxx
- // must precede arm_vaddl_vaddw
+ // must precede arm_vaddl_vaddw in table
new OpcodeARM(Index.arm_vcgt__imm0, "vcgt", "111100111x11xx01xxxx0x000xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.373 VREV16, VREV32, VREV64
+ // Encoding A1 / T1 Advanced SIMD
// vrev<n><c>.<size> <Qd>, <Qm> vrev<n><c>.<size> <Dd>, <Dm>
- // 111100111x11xx00xxxx000xxxx0xxxx
- // must precede arm_vaddl_vaddw
+ // must precede arm_vaddl_vaddw in table
new OpcodeARM(Index.arm_vrev, "vrev", "111100111x11xx00xxxx000xxxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.405 VSWP
+ // Encoding A1 / T1 Advanced SIMD
// vswp<c> <Qd>, <Qm> vswp<c> <Dd>, <Dm>
- // 111100111x11xx10xxxx00000xx0xxxx
- // must precede arm_vaddl_vaddw
+ // must precede arm_vaddl_vaddw in table
new OpcodeARM(Index.arm_vswp, "vswp", "111100111x11xx10xxxx00000xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.409 VUZP
+ // Encoding A1 / T1 Advanced SIMD
// vuzp<c>.<size> <Qd>, <Qm> vuzp<c>.<size> <Dd>, <Dm>
- // 111100111x11xx10xxxx00010xx0xxxx
- // must precede arm_vaddl_vaddw
- // must precede arm_vtrn
+ // must precede arm_vaddl_vaddw in table
+ // must precede arm_vtrn in table
new OpcodeARM(Index.arm_vuzp, "vuzp", "111100111x11xx10xxxx00010xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.410 VZIP
+ // Encoding A1 / T1 Advanced SIMD
// vzip<c>.<size> <Qd>, <Qm> vzip<c>.<size> <Dd>, <Dm>
- // 111100111x11xx10xxxx00011xx0xxxx
- // must precede arm_vaddl_vaddw
- // must precede arm_vtrn
+ // must precede arm_vaddl_vaddw in table
+ // must precede arm_vtrn in table
new OpcodeARM(Index.arm_vzip, "vzip", "111100111x11xx10xxxx00011xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.407 VTRN
+ // Encoding A1 / T1 Advanced SIMD
// vtrn<c>.<size> <Qd>, <Qm> vtrn<c>.<size> <Dd>, <Dm>
- // 111100111x11xx10xxxx00001xx0xxxx
- // must precede arm_vaddl_vaddw
- // must follow arm_vuzp
- // must follow arm_vzip
+ // must precede arm_vaddl_vaddw in table
+ // must follow arm_vuzp in table
+ // must follow arm_vzip in table
new OpcodeARM(Index.arm_vtrn, "vtrn", "111100111x11xx10xxxx00001xx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.274 VADDL, VADDW
+ // Encoding A1 / T1 Advanced SIMD
// vaddl<c>.<dt> <Qd>, <Dn>, <Dm> vaddw<c>.<dt> <Qd>, <Qn>, <Dm>
- // 1111001x1xxxxxxxxxxx000xx0x0xxxx
- // must follow arm_vceq__imm0
- // must follow arm_vcge__imm0
- // must follow arm_vcgt__imm0
- // must follow arm_vcle
- // must follow arm_vrev
- // must follow arm_vswp
- // must follow arm_vtrn
- // must follow arm_vuzp
- // must follow arm_vzip
+ // must follow arm_vceq__imm0 in table
+ // must follow arm_vcge__imm0 in table
+ // must follow arm_vcgt__imm0 in table
+ // must follow arm_vcle in table
+ // must follow arm_vrev in table
+ // must follow arm_vswp in table
+ // must follow arm_vtrn in table
+ // must follow arm_vuzp in table
+ // must follow arm_vzip in table
new OpcodeARM(Index.arm_vaddl_vaddw, "vadd", "1111001x1xxxxxxxxxxx000xx0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.276 VAND (register)
+ // Encoding A1 / T1 Advanced SIMD
// vand<c> <Qd>, <Qn>, <Qm> vand<c> <Dd>, <Dn>, <Dm>
- // 111100100x00xxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.arm_vand, "vand", "111100100x00xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.278 VBIC (register)
+ // Encoding A1 / T1 Advanced SIMD
// vbic<c> <Qd>, <Qn>, <Qm> vbic<c> <Dd>, <Dn>, <Dm>
- // 111100100x01xxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.arm_vbic, "vbic", "111100100x01xxxxxxxx0001xxx1xxxx"),
-// // NEW - Encoding A1 / T1 Advanced SIMD
-// // A8.6.304 VEOR
-// // veor<c> <Qd>, <Qn>, <Qm> veor<c> <Dd>, <Dn>, <Dm>
-// // 111100110x00xxxxxxxx0001xxx1xxxx
-// SEE arm_vbif_vbit_vbsl_veor
- // NEW - Encoding A1 / T1 Advanced SIMD
+ // A8.6.304 VEOR
+ // Encoding A1 / T1 Advanced SIMD
+ // veor<c> <Qd>, <Qn>, <Qm> veor<c> <Dd>, <Dn>, <Dm>
// A8.6.279 VBIF, VBIT, VBSL
+ // Encoding A1 / T1 Advanced SIMD
// vbif<c> <Qd>, <Qn>, <Qm> vbif<c> <Dd>, <Dn>, <Dm>
// vbit<c> <Qd>, <Qn>, <Qm> vbit<c> <Dd>, <Dn>, <Dm>
// vbsl<c> <Qd>, <Qn>, <Qm> vbsl<c> <Dd>, <Dn>, <Dm>
- // 111100110xxxxxxxxxxx0001xxx1xxxx
//
new OpcodeARM(Index.arm_vbif_vbit_vbsl_veor, "v", "111100110xxxxxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.280 VCEQ (register)
+ // Encoding A1 / T1 Advanced SIMD
// vceq<c>.<dt> <Qd>, <Qn>, <Qm> vceq<c>.<dt> <Dd>, <Dn>, <Dm>
- // 111100110xxxxxxxxxxx1000xxx1xxxx
new OpcodeARM(Index.arm_vceq__reg_int, "vceq", "111100110xxxxxxxxxxx1000xxx1xxxx"),
- // NEW - Encoding A2 / T2 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.280 VCEQ (register)
+ // Encoding A2 / T2 Advanced SIMD (UNDEFINED in integer-only variant)
// vceq<c>.f32 <Qd>, <Qn>, <Qm> vceq<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100x0xxxxxxxxx1110xxx0xxxx
new OpcodeARM(Index.arm_vceq__reg_f32, "vceq", "111100100x0xxxxxxxxx1110xxx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.282 VCGE (register)
+ // Encoding A1 / T1 Advanced SIMD
// vcge<c>.<dt> <Qd>, <Qn>, <Qm> vcge<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0011xxx1xxxx
new OpcodeARM(Index.arm_vcge__reg_int, "vcge", "1111001x0xxxxxxxxxxx0011xxx1xxxx"),
- // NEW - Encoding A2 / T2 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.282 VCGE (register)
+ // Encoding A2 / T2 Advanced SIMD (UNDEFINED in integer-only variant)
// vcge<c>.f32 <Qd>, <Qn>, <Qm> vcge<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110x0xxxxxxxxx1110xxx0xxxx
new OpcodeARM(Index.arm_vcge__reg_f32, "vcge", "111100110x0xxxxxxxxx1110xxx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.284 VCGT (register)
+ // Encoding A1 / T1 Advanced SIMD
// vcgt<c>.<dt> <Qd>, <Qn>, <Qm> vcgt<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0011xxx0xxxx
new OpcodeARM(Index.arm_vcgt__reg_int, "vcgt", "1111001x0xxxxxxxxxxx0011xxx0xxxx"),
- // NEW - Encoding A2 / T2 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.284 VCGT (register)
+ // Encoding A2 / T2 Advanced SIMD (UNDEFINED in integer-only variant)
// vcgt<c>.f32 <Qd>, <Qn>, <Qm> vcgt<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110x1xxxxxxxxx1110xxx0xxxx
new OpcodeARM(Index.arm_vcgt__reg_f32, "vcgt", "111100110x1xxxxxxxxx1110xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.288 VCLS
+ // Encoding A1 / T1 Advanced SIMD
// vcls<c>.<dt> <Qd>, <Qm> vcls<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx00xxxx01000xx0xxxx
new OpcodeARM(Index.arm_vcls, "vcls", "111100111x11xx00xxxx01000xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.290 VCLT (immediate #0)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vclt<c>.<dt> <Qd>, <Qm>, #0 vclt<c>.<dt> <Dd>, <Dm>, #0
- // 111100111x11xx01xxxx0x100xx0xxxx
new OpcodeARM(Index.arm_vclt, "vclt", "111100111x11xx01xxxx0x100xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.291 VCLZ
+ // Encoding A1 / T1 Advanced SIMD
// vclz<c>.<dt> <Qd>, <Qm> vclz<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx00xxxx01001xx0xxxx
new OpcodeARM(Index.arm_vclz, "vclz", "111100111x11xx00xxxx01001xx0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.292 VCMP, VCMPE
+ // Encoding A1 / T1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vcmp{e}<c>.f64 <Dd>, <Dm> vcmp{e}<c>.f32 <Sd>, <Sm>
- // xxxx11101x110100xxxx101xx1x0xxxx
new OpcodeARM(Index.arm_vcmp__reg, "vcmp", "xxxx11101x110100xxxx101xx1x0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.292 VCMP, VCMPE
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vcmp{e}<c>.f64 <Dd>, #0.0 vcmp{e}<c>.f32 <Sd>, #0.0
- // xxxx11101x110101xxxx101xx1(0)0(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx11101x110101xxxx101xx1(0)0(0)(0)(0)(0)
new OpcodeARM(Index.arm_vcmp__to_0, "vcmp", "xxxx11101x110101xxxx101xx1x0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv3 (sf = 1 UNDEFINED in single-precision only variants)
// A8.6.297 VCVT (between floating-point and fixed-point, VFP)
+ // Encoding A1 / T1 VFPv3 (sf = 1 UNDEFINED in single-precision only variants)
// vcvt<c>.<Td>.f64 <Dd>, <Dd>, #<fbits> vcvt<c>.<Td>.f32 <Sd>, <Sd>, #<fbits>
// vcvt<c>.f64.<Td> <Dd>, <Dd>, #<fbits> vcvt<c>.f32.<Td> <Sd>, <Sd>, #<fbits>
- // xxxx11101x111x1xxxxx101xx1x0xxxx
- // must precede arm_vcvt__fp_i_reg in search table
+ // must precede arm_vcvt__fp_i_reg in table
new OpcodeARM(Index.arm_vcvt__fp_fix_reg, "vcvt", "xxxx11101x111x1xxxxx101xx1x0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.295 VCVT, VCVTR (between floating-point and integer, VFP)
+ // Encoding A1 / T1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vcvt{r}<c>.s32.f64 <Sd>, <Dm> vcvt{r}<c>.s32.f32 <Sd>, <Sm> vcvt{r}<c>.u32.f64 <Sd>, <Dm>
// vcvt{r}<c>.u32.f32 <Sd>, <Sm> vcvt<c>.f64.<Tm> <Dd>, <Sm> vcvt<c>.f32.<Tm> <Sd>, <Sm>
- // xxxx11101x111xxxxxxx101xx1x0xxxx
- // must follow arm_vcvt__fp_fix_reg in search table
+ // must follow arm_vcvt__fp_fix_reg in table
new OpcodeARM(Index.arm_vcvt__fp_i_reg, "vcvt", "xxxx11101x111xxxxxxx101xx1x0xxxx"),
- // NEW - Encoding A1 / T1 (i) Advanced SIMD
// A8.6.277 VBIC (immediate)
+ // Encoding A1 / T1 Advanced SIMD
// vbic<c>.<dt> <Qd>, #<imm> vbic<c>.<dt> <Dd>, #<imm>
-// SEE arm_vmov_vbitwise
- // NEW - Encoding A1 / T1 (i) Advanced SIMD
// A8.6.346 VORR (immediate)
+ // Encoding A1 / T1 Advanced SIMD
// vorr<c>.<dt> <Qd>, #<imm> vorr<c>.<dt> <Dd>, #<imm>
-// SEE arm_vmov_vbitwise
- // NEW - Encoding A1 / T1 (i) Advanced SIMD
// A8.6.340 VMVN (immediate)
+ // Encoding A1 / T1 Advanced SIMD
// vmvn<c>.<dt> <Qd>, #<imm> vmvn<c>.<dt> <Dd>, #<imm>
-// SEE arm_vmov_vbitwise
- // NEW - Encoding A1 / T1 (i) Advanced SIMD
// A8.6.326 VMOV (immediate)
+ // Encoding A1 / T1 Advanced SIMD
// vmov<c>.<dt> <Qd>, #<imm> vmov<c>.<dt> <Dd>, #<imm>
//
- // 1111001x1x000xxxxxxxxxxx0x11xxxx
- // 1111001x1x000xxxxxxxxxxx0x01xxxx
- // 1111001x1x000xxxxxxxxxxx0x11xxxx
- // 1111001x1x000xxxxxxxxxxx0xx1xxxx
- // must precede arm_vcvt__fp_fix_vec
+ // must precede arm_vcvt__fp_fix_vec in table
new OpcodeARM(Index.arm_vmov_vbitwise, "_", "1111001x1x000xxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vcvt<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> vcvt<c>.<Td>.<Tm> <Dd>, <Dm>, #<fbits>
- // 1111001x1xxxxxxxxxxx111x0xx1xxxx
- // must follow arm_vmov_vbitwise
+ // must follow arm_vmov_vbitwise in table
new OpcodeARM(Index.arm_vcvt__fp_fix_vec, "vcvt", "1111001x1xxxxxxxxxxx111x0xx1xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3 (UNDEFINED in single-precision only variants)
// A8.6.298 VCVT (between double-precision and single-precision)
+ // Encoding A1 / T1 VFPv2, VFPv3 (UNDEFINED in single-precision only variants)
// vcvt<c>.f64.f32 <Dd>, <Sm> vcvt<c>.f32.f64 <Sd>, <Dm>
- // xxxx11101x110111xxxx101x11x0xxxx
new OpcodeARM(Index.arm_vcvt__dp_sp, "vcvt", "xxxx11101x110111xxxx101x11x0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv3 half-precision extensions
// A8.6.300 VCVTB, VCVTT (between half-precision and single-precision, VFP)
+ // Encoding A1 / T1 VFPv3 half-precision extensions
// vcvt<y><c>.f32.f16 <Sd>, <Sm> vcvt<y><c>.f16.f32 <Sd>, <Sm>
- // xxxx11101x11001xxxxx1010x1x0xxxx
new OpcodeARM(Index.arm_vcvt__hp_sp_reg, "vcvt", "xxxx11101x11001xxxxx1010x1x0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.301 VDIV
+ // Encoding A1 / T1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vdiv<c>.f64 <Dd>, <Dn>, <Dm> vdiv<c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11101x00xxxxxxxx101xx0x0xxxx
new OpcodeARM(Index.arm_vdiv, "vdiv", "xxxx11101x00xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.302 VDUP (scalar)
+ // Encoding A1 / T1 Advanced SIMD
// vdup<c>.<size> <Qd>, <Dm[x]> vdup<c>.<size> <Dd>, <Dm[x]>
- // 111100111x11xxxxxxxx11000xx0xxxx
new OpcodeARM(Index.arm_vdup__scalar, "vdup", "111100111x11xxxxxxxx11000xx0xxxx"),
- // NEW - Encoding A1 / T1 (cond) Advanced SIMD
// A8.6.303 VDUP (ARM core register)
+ // Encoding A1 / T1 Advanced SIMD
// vdup<c>.<size> <Qd>, <Rt> vdup<c>.<size> <Dd>, <Rt>
- // xxxx11101xx0xxxxxxxx1011x0x1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx11101xx0xxxxxxxx1011x0x1(0)(0)(0)(0)
new OpcodeARM(Index.arm_vdup__reg, "vdup", "xxxx11101xx0xxxxxxxx1011x0x1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.306 VHADD, VHSUB
+ // Encoding A1 / T1 Advanced SIMD
// vh<op><c> <Qd>, <Qn>, <Qm> vh<op><c> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx00x0xxx0xxxx
new OpcodeARM(Index.arm_vhadd_vhsub, "vh", "1111001x0xxxxxxxxxxx00x0xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.307 VLD1 (multiple single elements)
+ // Encoding A1 / T1 Advanced SIMD
// vld1<c>.<size> <list>, [<Rn>{@<align>}]{!} vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x10xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.310 VLD2 (multiple 2-element structures)
+ // Encoding A1 / T1 Advanced SIMD
// vld2<c>.<size> <list>, [<Rn>{@<align>}]{!} vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x10xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.313 VLD3 (multiple 3-element structures)
+ // Encoding A1 / T1 Advanced SIMD
// vld3<c>.<size> <list>, [<Rn>{@<align>}]{!} vld3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x10xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.316 VLD4 (multiple 4-element structures)
+ // Encoding A1 / T1 Advanced SIMD
// vld4<c>.<size> <list>, [<Rn>{@<align>}]{!} vld4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x10xxxxxxxxxxxxxxxxxxxx
+ //
new OpcodeARM(Index.arm_vld__multi, "vld", "111101000x10xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.308 VLD1 (single element to one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vld1<c>.<size> <list>, [<Rn>{@<align>}]{!} vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x10xxxxxxxxxx00xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.309 VLD1 (single element to all lanes)
+ // Encoding A1 / T1 Advanced SIMD
// vld1<c>.<size> <list>, [<Rn>{@<align>}]{!} vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x10xxxxxxxx1100xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.311 VLD2 (single 2-element structure to one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vld2<c>.<size> <list>, [<Rn>{@<align>}]{!} vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x10xxxxxxxxxx01xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.312 VLD2 (single 2-element structure to all lanes)
+ // Encoding A1 / T1 Advanced SIMD
// vld2<c>.<size> <list>, [<Rn>{@<align>}]{!} vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x10xxxxxxxx1101xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.314 VLD3 (single 3-element structure to one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vld3<c>.<size> <list>, [<Rn>]{!} vld3<c>.<size> <list>, [<Rn>], <Rm>
- // 111101001x10xxxxxxxxxx10xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.315 VLD3 (single 3-element structure to all lanes)
+ // Encoding A1 / T1 Advanced SIMD
// vld3<c>.<size> <list>, [<Rn>]{!} vld3<c>.<size> <list>, [<Rn>], <Rm>
- // 111101001x10xxxxxxxx1110xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.317 VLD4 (single 4-element structure to one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vld4<c>.<size> <list>, [<Rn>{@<align>}]{!} vld4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x10xxxxxxxxxx11xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.318 VLD4 (single 4-element structure to all lanes)
+ // Encoding A1 / T1 Advanced SIMD
// vld4<c>.<size> <list>, [<Rn>{ @<align>}]{!} vld4<c>.<size> <list>, [<Rn>{ @<align>}], <Rm>
- // 111101001x10xxxxxxxx1111xxxxxxxx
- //
+ //
new OpcodeARM(Index.arm_vld__xlane, "vld", "111101001x10xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.320 VLDR
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vldr<c> <Dd>, [<Rn>{, #+/-<imm>}] vldr<c> <Dd>, <label> vldr<c> <Dd>, [pc,#-0] Special case
- // xxxx1101xx01xxxxxxxx1011xxxxxxxx
- // must precede arm_vldm_1 in search table
+ // must precede arm_vldm_1 in table
new OpcodeARM(Index.arm_vldr__64, "vldr", "xxxx1101xx01xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.332 VMOV (between two ARM core registers and a doubleword extension register)
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vmov<c> <Dm>, <Rt>, <Rt2> vmov<c> <Rt>, <Rt2>, <Dm>
- // xxxx1100010xxxxxxxxx101100x1xxxx
- // must precede arm_vldm__64
+ // must precede arm_vldm__64 in table
new OpcodeARM(Index.arm_vmov_9, "vmov", "xxxx1100010xxxxxxxxx101100x1xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.354 VPOP
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vpop <list> <list> is consecutive 64-bit registers
- // xxxx11001x111101xxxx1011xxxxxxxx
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3
// A8.6.354 VPOP
+ // Encoding A2 / T2 VFPv2, VFPv3
// vpop <list> <list> is consecutive 32-bit registers
- // xxxx11001x111101xxxx1010xxxxxxxx
- // must precede arm_vldm_1 in search table
- // must precede arm_vldm_2 in search table
- // must precede arm_vldm__64
+ // must precede arm_vldm_1 in table
+ // must precede arm_vldm_2 in table
+ // must precede arm_vldm__64 in table
new OpcodeARM(Index.arm_vpop, "vpop", "xxxx11001x111101xxxx101xxxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.319 VLDM
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vldm{mode}<c> <Rn>{!}, <list> <list> is consecutive 64-bit registers
- // xxxx110xxxx1xxxxxxxx1011xxxxxxxx
- // must follow arm_vldr_1 in search table
- // must follow arm_vmov_9
- // must follow arm_vpop in search table
+ // must follow arm_vldr_1 in table
+ // must follow arm_vmov_9 in table
+ // must follow arm_vpop in table
new OpcodeARM(Index.arm_vldm__64, "vldm", "xxxx110xxxx1xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3
// A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
+ // Encoding A1 / T1 VFPv2, VFPv3
// vmov<c> <Sm>, <Sm1>, <Rt>, <Rt2> vmov<c> <Rt>, <Rt2>, <Sm>, <Sm1>
- // xxxx1100010xxxxxxxxx101000x1xxxx
- // must precede arm_vldr__32
+ // must precede arm_vldr__32 in table
new OpcodeARM(Index.arm_vmov_8, "vmov", "xxxx1100010xxxxxxxxx101000x1xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3
// A8.6.320 VLDR
+ // Encoding A2 / T2 VFPv2, VFPv3
// vldr<c> <Sd>, [<Rn>{, #+/-<imm>}] vldr<c> <Sd>, <label> vldr<c> <Sd>, [pc,#-0] Special case
- // xxxx1101xx01xxxxxxxx1010xxxxxxxx
- // must precede arm_vldm_2 in search table
- // must follow arm_vmov_8
+ // must precede arm_vldm_2 in table
+ // must follow arm_vmov_8 in table
new OpcodeARM(Index.arm_vldr__32, "vldr", "xxxx1101xx01xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3
// A8.6.319 VLDM
+ // Encoding A2 / T2 VFPv2, VFPv3
// vldm{mode}<c> <Rn>{!}, <list> <list> is consecutive 32-bit registers
- // xxxx110xxxx1xxxxxxxx1010xxxxxxxx
- // must follow arm_vldr_2 in search table
- // must follow arm_vpop in search table
+ // must follow arm_vldr_2 in table
+ // must follow arm_vpop in table
new OpcodeARM(Index.arm_vldm__32, "vldm", "xxxx110xxxx1xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.321 VMAX, VMIN (integer)
+ // Encoding A1 / T1 Advanced SIMD
// vmax<c>.<dt> <Qd>, <Qn>, <Qm> vmax<c>.<dt> <Dd>, <Dn>, <Dm>
// vmin<c>.<dt> <Qd>, <Qn>, <Qm> vmin<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0110xxxxxxxx
new OpcodeARM(Index.arm_vmax_vmin__int, "v", "1111001x0xxxxxxxxxxx0110xxxxxxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.322 VMAX, VMIN (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vmax<c>.f32 <Qd>, <Qn>, <Qm> vmax<c>.f32 <Dd>, <Dn>, <Dm>
// vmin<c>.f32 <Qd>, <Qn>, <Qm> vmin<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100xxxxxxxxxxx1111xxx0xxxx
new OpcodeARM(Index.arm_vmax_vmin__fp, "v", "111100100xxxxxxxxxxx1111xxx0xxxx"),
- // NEW - Encoding A1 / T1 (op) Advanced SIMD
// A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
+ // Encoding A1 / T1 Advanced SIMD
// v<op><c>.<dt> <Qd>, <Qn>, <Qm> v<op><c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx1001xxx0xxxx
new OpcodeARM(Index.arm_vml__int, "vml", "1111001x0xxxxxxxxxxx1001xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.406 VTBL, VTBX
+ // Encoding A1 / T1 Advanced SIMD
// v<op><c>.8 <Dd>, <list>, <Dm>
- // 111100111x11xxxxxxxx10xxxxx0xxxx
- // must precede arm_vml__int_long
+ // must precede arm_vml__int_long in table
new OpcodeARM(Index.arm_vtb, "vtb", "111100111x11xxxxxxxx10xxxxx0xxxx"),
- // NEW - Encoding A2 / T2 (U) Advanced SIMD
// A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
+ // Encoding A2 / T2 Advanced SIMD
// v<op>l<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1111001x1xxxxxxxxxxx10x0x0x0xxxx
- // must follow arm_vtb
+ // must follow arm_vtb in table
new OpcodeARM(Index.arm_vml__int_long, "vml", "1111001x1xxxxxxxxxxx10x0x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.324 VMLA, VMLS (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// v<op><c>.f32 <Qd>, <Qn>, <Qm> v<op><c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100xxxxxxxxxxx1101xxx1xxxx
new OpcodeARM(Index.arm_vml__f32, "vml", "111100100xxxxxxxxxxx1101xxx1xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.324 VMLA, VMLS (floating-point)
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// v<op><c>.f64 <Dd>, <Dn>, <Dm> v<op><c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11100x00xxxxxxxx101xxxx0xxxx
new OpcodeARM(Index.arm_vml__fp, "vml", "xxxx11100x00xxxxxxxx101xxxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.341 VMVN (register)
+ // Encoding A1 / T1 Advanced SIMD
// vmvn<c> <Qd>, <Qm> vmvn<c> <Dd>, <Dm>
- // 111100111x11xx00xxxx01011xx0xxxx
- // must precede arm_vml__scalar
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vmvn, "vmvn", "111100111x11xx00xxxx01011xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.348 VPADAL
+ // Encoding A1 / T1 Advanced SIMD
// vpadal<c>.<dt> <Qd>, <Qm> vpadal<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx00xxxx0110xxx0xxxx
- // must precede arm_vml__scalar
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vpadal, "vpadal", "111100111x11xx00xxxx0110xxx0xxxx"),
- // NEW - Encoding A2 / T2 Advanced SIMD
// A8.6.358 VQDMLAL, VQDMLSL
+ // Encoding A2 / T2 Advanced SIMD
// vqd<op><c>.<dt> <Qd>,<Dn>,<Dm[x]>
- // 111100101xxxxxxxxxxx0x11x1x0xxxx
- // must precede arm_vml__scalar
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vqdml__scalar, "vqdml", "111100101xxxxxxxxxxx0x11x1x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.334 VMOVN
+ // Encoding A1 / T1 Advanced SIMD
// vmovn<c>.<dt> <Dd>, <Qm>
- // 111100111x11xx10xxxx001000x0xxxx
- // must precede arm_vqmov in search table
+ // must precede arm_vqmov in table
new OpcodeARM(Index.arm_vmovn, "vmovn", "111100111x11xx10xxxx001000x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.351 VPADDL
+ // Encoding A1 / T1 Advanced SIMD
// vpaddl<c>.<dt> <Qd>, <Qm> vpaddl<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx00xxxx0010xxx0xxxx
- // must precede arm_vml__scalar
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vpaddl, "vpaddl", "111100111x11xx00xxxx0010xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.361 VQMOVN, VQMOVUN
+ // Encoding A1 / T1 Advanced SIMD
// vqmov{u}n<c>.<type><size> <Dd>, <Qm>
- // 111100111x11xx10xxxx0010xxx0xxxx
- // must follow arm_vmovn in search table
- // must precede arm_vml__scalar
+ // must follow arm_vmovn in table
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vqmov, "vqmov", "111100111x11xx10xxxx0010xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.371 VRECPE
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vrecpe<c>.<dt> <Qd>, <Qm> vrecpe<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx11xxxx010x0xx0xxxx
- // must precede arm_vml__scalar
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vrecpe, "vrecpe", "111100111x11xx11xxxx010x0xx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.378 VRSQRTE
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vrsqrte<c>.<dt> <Qd>, <Qm> vrsqrte<c>.<dt> <Dd>, <Dm>
- // 111100111x11xx11xxxx010x1xx0xxxx
- // must precede arm_vabal
- // must precede arm_vml__scalar
+ // must precede arm_vabal in table
+ // must precede arm_vml__scalar in table
new OpcodeARM(Index.arm_vrsqrte, "vrsqrte", "111100111x11xx11xxxx010x1xx0xxxx"),
- // NEW - Encoding A1 / T1 (Q) Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// v<op><c>.<dt> <Qd>, <Qn>, <Dm[x]> v<op><c>.<dt> <Dd>, <Dn>, <Dm[x]>
- // NEW - Encoding A2 / T2 (U) Advanced SIMD
// A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
+ // Encoding A2 / T2 Advanced SIMD
// v<op>l<c>.<dt> <Qd>, <Dn>, <Dm[x]>
- // 1111001x1xxxxxxxxxxx0xxxx1x0xxxx
- // must follow arm_vmvn
- // must follow arm_vpadal
- // must follow arm_vpaddl
- // must follow arm_vqdml__scalar
- // must follow arm_vqmov
- // must follow arm_vrecpe
- // must follow arm_vrsqrte
+ // must follow arm_vmvn in table
+ // must follow arm_vpadal in table
+ // must follow arm_vpaddl in table
+ // must follow arm_vqdml__scalar in table
+ // must follow arm_vqmov in table
+ // must follow arm_vrecpe in table
+ // must follow arm_vrsqrte in table
new OpcodeARM(Index.arm_vml__scalar, "vml", "1111001x1xxxxxxxxxxx0xxxx1x0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.326 VMOV (immediate)
+ // Encoding A2 / T2 VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vmov<c>.f64 <Dd>, #<imm> vmov<c>.f32 <Sd>, #<imm>
- // xxxx11101x11xxxxxxxx101x(0)0(0)0xxxx
+ // Unpredictable if (0) is 1: xxxx11101x11xxxxxxxx101x(0)0(0)0xxxx
new OpcodeARM(Index.arm_vmov__imm, "vmov", "xxxx11101x11xxxxxxxx101xx0x0xxxx"),
-// // NEW - Encoding A1 / T1 Advanced SIMD
-// // A8.6.327 VMOV (register)
-// // vmov<c> <Qd>, <Qm> vmov<c> <Dd>, <Dm>
-// // 111100100x10xxxxxxxx0001xxx1xxxx
-// SEE arm_vorr_2 parse
-// new OpcodeARM(Index.arm_vmov__reg, "vmov", "111100100x10xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.327 VMOV (register)
+ // Encoding A1 / T1 Advanced SIMD
+ // vmov<c> <Qd>, <Qm> vmov<c> <Dd>, <Dm>
+ // A8.6.347 VORR (register)
+ // Encoding A1 / T1 Advanced SIMD
+ // vorr<c> <Qd>, <Qn>, <Qm> vorr<c> <Dd>, <Dn>, <Dm>
+ //
+ new OpcodeARM(Index.arm_vmov_vorr, "vmov", "111100100x10xxxxxxxx0001xxx1xxxx"),
+ // A8.6.327 VMOV (register)
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vmov<c>.f64 <Dd>, <Dm> vmov<c>.f32 <Sd>, <Sm>
- // xxxx11101x110000xxxx101x01x0xxxx
new OpcodeARM(Index.arm_vmov__reg_f, "vmov", "xxxx11101x110000xxxx101x01x0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD if opc1 == '0x' && opc2 == '00'; Advanced SIMD otherwise
// A8.6.328 VMOV (ARM core register to scalar)
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD for word version (opc1:opc2 == '00x00'); Advanced SIMD otherwise
// vmov<c>.<size> <Dd[x]>, <Rt>
- // xxxx11100xx0xxxxxxxx1011xxx1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx11100xx0xxxxxxxx1011xxx1(0)(0)(0)(0)
new OpcodeARM(Index.arm_vmov_5, "vmov", "xxxx11100xx0xxxxxxxx1011xxx1xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD if opc1 == '0x' && opc2 == '00';Advanced SIMD otherwise
// A8.6.329 VMOV (scalar to ARM core register)
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD for word version (U:opc1:opc2 == '00x00'); Advanced SIMD otherwise
// vmov<c>.<dt> <Rt>, <Dn[x]>
- // xxxx1110xxx1xxxxxxxx1011xxx1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx1110xxx1xxxxxxxx1011xxx1(0)(0)(0)(0)
new OpcodeARM(Index.arm_vmov_6, "vmov", "xxxx1110xxx1xxxxxxxx1011xxx1xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3
// A8.6.330 VMOV (between ARM core register and single-precision register)
+ // Encoding A1 / T1 VFPv2, VFPv3
// vmov<c> <Sn>, <Rt> vmov<c> <Sn>, <Rt> vmov<c> <Rt>, <Sn>
- // xxxx1110000xxxxxxxxx1010x(0)(0)1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx1110000xxxxxxxxx1010x(0)(0)1(0)(0)(0)(0)
new OpcodeARM(Index.arm_vmov_7, "vmov", "xxxx1110000xxxxxxxxx1010xxx1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.333 VMOVL
+ // Encoding A1 / T1 Advanced SIMD
// vmovl<c>.<dt> <Qd>, <Dm>
- // 1111001x1xxxx000xxxx101000x1xxxx
- // must precede arm_vshll_1 in search table
+ // must precede arm_vshll_1 in table
new OpcodeARM(Index.arm_vmovl, "vmovl", "1111001x1xxxx000xxxx101000x1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.384 VSHLL
+ // Encoding A1 / T1 Advanced SIMD
// vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (0 < <imm> < <size>)
- // 1111001x1xxxxxxxxxxx101000x1xxxx
- // must follow arm_vmovl in search table
+ // must follow arm_vmovl in table
new OpcodeARM(Index.arm_vshll__various, "vshll", "1111001x1xxxxxxxxxxx101000x1xxxx"),
-// // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
-// // A8.6.335 VMRS
-// // vmrs<c> <Rt>, fpscr
-// // xxxx111011110001xxxx10100(0)(0)1(0)(0)(0)(0)
-// SEE arm_vmrs
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
+ // A8.6.335 VMRS
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
+ // vmrs<c> <Rt>, fpscr
+ // Unpredictable if (0) is 1: xxxx111011110001xxxx10100(0)(0)1(0)(0)(0)(0)
// B6.1.14 VMRS
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vmrs<c> <Rt>,<spec_reg>
- // xxxx11101111xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx11101111xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ //
new OpcodeARM(Index.arm_vmrs, "vmrs", "xxxx11101111xxxxxxxx1010xxx1xxxx"),
-// // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
-// // A8.6.336 VMSR
-// // vmsr<c> fpscr, <Rt>
-// // xxxx111011100001xxxx10100(0)(0)1(0)(0)(0)(0)
-// SEE arm_vmsr
-// new OpcodeARM(Index.arm_vmsr_1, "vmsr", "xxxx111011100001xxxx10100xx1xxxx"),
- // NEW - Encoding A1 / T2 (cond) VFPv2, VFPv3, Advanced SIMD
+ // A8.6.336 VMSR
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
+ // vmsr<c> fpscr, <Rt>
+ // Unpredictable if (0) is 1: xxxx111011100001xxxx10100(0)(0)1(0)(0)(0)(0)
// B6.1.15 VMSR
+ // Encoding A1 / T2 VFPv2, VFPv3, Advanced SIMD
// vmsr<c> <spec_reg>,<Rt>
- // xxxx11101110xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: xxxx11101110xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ //
new OpcodeARM(Index.arm_vmsr, "vmsr", "xxxx11101110xxxxxxxx1010xxx1xxxx"),
- // NEW - Encoding A1 / T1 (op) Advanced SIMD
// A8.6.337 VMUL, VMULL (integer and polynomial)
+ // Encoding A1 / T1 Advanced SIMD
// vmul<c>.<dt> <Qd>, <Qn>, <Qm> vmul<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx1001xxx1xxxx
new OpcodeARM(Index.arm_vmul_1, "vmul", "1111001x0xxxxxxxxxxx1001xxx1xxxx"),
- // NEW - Encoding A2 / T2 (U) Advanced SIMD
// A8.6.337 VMUL, VMULL (integer and polynomial)
+ // Encoding A2 / T2 Advanced SIMD
// vmull<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1111001x1xxxxxxxxxxx11x0x0x0xxxx
new OpcodeARM(Index.arm_vmull, "vmull", "1111001x1xxxxxxxxxxx11x0x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.338 VMUL (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vmul<c>.f32 <Qd>, <Qn>, <Qm> vmul<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110x0xxxxxxxxx1101xxx1xxxx
new OpcodeARM(Index.arm_vmul_f32, "vmul", "111100110x0xxxxxxxxx1101xxx1xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.338 VMUL (floating-point)
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vmul<c>.f64 <Dd>, <Dn>, <Dm> vmul<c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11100x10xxxxxxxx101xx0x0xxxx
new OpcodeARM(Index.arm_vmul__fp_2, "vmul", "xxxx11100x10xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding A2 / T2 Advanced SIMD
// A8.6.360 VQDMULL
+ // Encoding A2 / T2 Advanced SIMD
// vqdmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
- // 111100101xxxxxxxxxxx1011x1x0xxxx
- // must precede arm_vmul__scalar
+ // must precede arm_vmul__scalar in table
new OpcodeARM(Index.arm_vqdmull__scalar, "vqdmul", "111100101xxxxxxxxxxx1011x1x0xxxx"),
- // NEW - Encoding A1 / T1 (Q) Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.339 VMUL, VMULL (by scalar)
+ // Encoding A1 / T1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vmul<c>.<dt> <Qd>, <Qn>, <Dm[x]> vmul<c>.<dt> <Dd>, <Dn>, <Dm[x]>
- // 1111001x1xxxxxxxxxxx100xx1x0xxxx
- // NEW - Encoding A2 / T2 (U) Advanced SIMD
// A8.6.339 VMUL, VMULL (by scalar)
+ // Encoding A2 / T2 Advanced SIMD
// vmull<c>.<dt> <Qd>, <Dn>, <Dm[x]>
- // 1111001x1xxxxxxxxxxx1010x1x0xxxx
- // must follow arm_vqdmull__scalar
+ // must follow arm_vqdmull__scalar in table
new OpcodeARM(Index.arm_vmul__scalar, "vmul", "1111001x1xxxxxxxxxxx10xxx1x0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.342 VNEG
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vneg<c>.f64 <Dd>, <Dm> vneg<c>.f32 <Sd>, <Sm>
- // xxxx11101x110001xxxx101x01x0xxxx
new OpcodeARM(Index.arm_vneg__f, "vneg", "xxxx11101x110001xxxx101x01x0xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.343 VNMLA, VNMLS, VNMUL
+ // Encoding A1 / T1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vnmla<c>.f64 <Dd>, <Dn>, <Dm> vnmla<c>.f32 <Sd>, <Sn>, <Sm>
// vnmls<c>.f64 <Dd>, <Dn>, <Dm> vnmls<c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11100x01xxxxxxxx101xxxx0xxxx
new OpcodeARM(Index.arm_vnml, "vnml", "xxxx11100x01xxxxxxxx101xxxx0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.343 VNMLA, VNMLS, VNMUL
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vnmul<c>.f64 <Dd>, <Dn>, <Dm> vnmul<c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11100x10xxxxxxxx101xx1x0xxxx
new OpcodeARM(Index.arm_vnmul, "vnmul", "xxxx11100x10xxxxxxxx101xx1x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
- // A8.6.347 VORR (register)
- // vorr<c> <Qd>, <Qn>, <Qm> vorr<c> <Dd>, <Dn>, <Dm>
- // 111100100x10xxxxxxxx0001xxx1xxxx
- new OpcodeARM(Index.arm_vorr, "vorr", "111100100x10xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.345 VORN (register)
+ // Encoding A1 / T1 Advanced SIMD
// vorn<c> <Qd>, <Qn>, <Qm> vorn<c> <Dd>, <Dn>, <Dm>
- // 111100100x11xxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.arm_vorn, "vorn", "111100100x11xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.349 VPADD (integer)
+ // Encoding A1 / T1 Advanced SIMD
// vpadd<c>.<dt> <Dd>, <Dn>, <Dm>
- // 111100100xxxxxxxxxxx1011xxx1xxxx
new OpcodeARM(Index.arm_vpadd__int, "vpadd", "111100100xxxxxxxxxxx1011xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.350 VPADD (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vpadd<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110x0xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.arm_vpadd__f32, "vpadd", "111100110x0xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.352 VPMAX, VPMIN (integer)
+ // Encoding A1 / T1 Advanced SIMD
// vp<op><c>.<dt> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx1010xxxxxxxx
new OpcodeARM(Index.arm_vpmax_vpmin__int, "vp", "1111001x0xxxxxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.353 VPMAX, VPMIN (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vp<op><c>.f32 <Dd>, <Dn>, <Dm>
- // 111100110xxxxxxxxxxx1111xxx0xxxx
new OpcodeARM(Index.arm_vpmax_vpmin__fp, "vp", "111100110xxxxxxxxxxx1111xxx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.357 VQADD
+ // Encoding A1 / T1 Advanced SIMD
// vqadd<c>.<dt> <Qd>,<Qn>,<Qm> vqadd<c>.<dt> <Dd>,<Dn>,<Dm>
- // 1111001x0xxxxxxxxxxx0000xxx1xxxx
new OpcodeARM(Index.arm_vqadd, "vqadd", "1111001x0xxxxxxxxxxx0000xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.358 VQDMLAL, VQDMLSL
+ // Encoding A1 / T1 Advanced SIMD
// vqd<op><c>.<dt> <Qd>,<Dn>,<Dm>
- // 111100101xxxxxxxxxxx10x1x0x0xxxx
new OpcodeARM(Index.arm_vqdml__vec, "vqdml", "111100101xxxxxxxxxxx10x1x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.359 VQDMULH
+ // Encoding A1 / T1 Advanced SIMD
// vqdmulh<c>.<dt> <Qd>,<Qn>,<Qm> vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
- // 111100100xxxxxxxxxxx1011xxx0xxxx
new OpcodeARM(Index.arm_vqdmulh__vec, "vqdmulh", "111100100xxxxxxxxxxx1011xxx0xxxx"),
- // NEW - Encoding A2 / T2 (Q) Advanced SIMD
// A8.6.359 VQDMULH
+ // Encoding A2 / T2 Advanced SIMD
// vqdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]> vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
- // 1111001x1xxxxxxxxxxx1100x1x0xxxx
new OpcodeARM(Index.arm_vqdmulh__scalar, "vqdmulh", "1111001x1xxxxxxxxxxx1100x1x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.360 VQDMULL
+ // Encoding A1 / T1 Advanced SIMD
// vqdmull<c>.<dt> <Qd>,<Dn>,<Dm> vqdmull<c>.<dt> <Qd>,<Dn>,<Dm>
- // 111100101xxxxxxxxxxx1101x0x0xxxx
new OpcodeARM(Index.arm_vqdmull__vec, "vqdmull", "111100101xxxxxxxxxxx1101x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.363 VQRDMULH
+ // Encoding A1 / T1 Advanced SIMD
// vqrdmulh<c>.<dt> <Qd>,<Qn>,<Qm> vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
- // 111100110xxxxxxxxxxx1011xxx0xxxx
new OpcodeARM(Index.arm_vqrdmulh__vec, "vqrdmulh", "111100110xxxxxxxxxxx1011xxx0xxxx"),
- // NEW - Encoding A2 / T2 (Q) Advanced SIMD
// A8.6.363 VQRDMULH
+ // Encoding A2 / T2 Advanced SIMD
// vqrdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]> vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
- // 1111001x1xxxxxxxxxxx1101x1x0xxxx
new OpcodeARM(Index.arm_vqrdmulh__scalar, "vqrdmulh", "1111001x1xxxxxxxxxxx1101x1x0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.364 VQRSHL
+ // Encoding A1 / T1 Advanced SIMD
// vqrshl<c>.<type><size> <Qd>,<Qm>,<Qn> vqrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- // 1111001x0xxxxxxxxxxx0101xxx1xxxx
new OpcodeARM(Index.arm_vqrshl, "vqrshl", "1111001x0xxxxxxxxxxx0101xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.377 VRSHRN
+ // Encoding A1 / T1 Advanced SIMD
// vrshrn<c>.i<size> <Dd>, <Qm>, #<imm>
- // 111100101xxxxxxxxxxx100001x1xxxx
- // must precede arm_vqrshr in search table
+ // must precede arm_vqrshr in table
new OpcodeARM(Index.arm_vrshrn, "vrshrn", "111100101xxxxxxxxxxx100001x1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.365 VQRSHRN, VQRSHRUN
+ // Encoding A1 / T1 Advanced SIMD
// vqrshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- // 1111001x1xxxxxxxxxxx100x01x1xxxx
- // must follow arm_vrshrn in search table
+ // must follow arm_vrshrn in table
new OpcodeARM(Index.arm_vqrshr, "vqrshr", "1111001x1xxxxxxxxxxx100x01x1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.366 VQSHL (register)
+ // Encoding A1 / T1 Advanced SIMD
// vqshl<c>.<type><size> <Qd>,<Qm>,<Qn> vqshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- // 1111001x0xxxxxxxxxxx0100xxx1xxxx
new OpcodeARM(Index.arm_vqshl__reg, "vqshl", "1111001x0xxxxxxxxxxx0100xxx1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.367 VQSHL, VQSHLU (immediate)
+ // Encoding A1 / T1 Advanced SIMD
// vqshl{u}<c>.<type><size> <Qd>,<Qm>,#<imm> vqshl{u}<c>.<type><size> <Dd>,<Dm>,#<imm>
- // 1111001x1xxxxxxxxxxx011xxxx1xxxx
new OpcodeARM(Index.arm_vqshl__imm, "vqshl", "1111001x1xxxxxxxxxxx011xxxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.386 VSHRN
+ // Encoding A1 / T1 Advanced SIMD
// vshrn<c>.i<size> <Dd>, <Qm>, #<imm>
- // 111100101xxxxxxxxxxx100000x1xxxx
- // must precede arm_vqshr in search table
+ // must precede arm_vqshr in table
new OpcodeARM(Index.arm_vshrn, "vshrn", "111100101xxxxxxxxxxx100000x1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.368 VQSHRN, VQSHRUN
+ // Encoding A1 / T1 Advanced SIMD
// vqshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- // 1111001x1xxxxxxxxxxx100x00x1xxxx
- // must follow arm_vshrn in search table
+ // must follow arm_vshrn in table
new OpcodeARM(Index.arm_vqshr, "vqshr", "1111001x1xxxxxxxxxxx100x00x1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.369 VQSUB
+ // Encoding A1 / T1 Advanced SIMD
// vqsub<c>.<type><size> <Qd>, <Qn>, <Qm> vqsub<c>.<type><size> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0010xxx1xxxx
new OpcodeARM(Index.arm_vqsub, "vqsub", "1111001x0xxxxxxxxxxx0010xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.370 VRADDHN
+ // Encoding A1 / T1 Advanced SIMD
// vraddhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 111100111xxxxxxxxxxx0100x0x0xxxx
new OpcodeARM(Index.arm_vraddhn, "vraddhn", "111100111xxxxxxxxxxx0100x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.372 VRECPS
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vrecps<c>.f32 <Qd>, <Qn>, <Qm> vrecps<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100x0xxxxxxxxx1111xxx1xxxx
new OpcodeARM(Index.arm_vrecps, "vrecps", "111100100x0xxxxxxxxx1111xxx1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.374 VRHADD
+ // Encoding A1 / T1 Advanced SIMD
// vrhadd<c> <Qd>, <Qn>, <Qm> vrhadd<c> <Dd>, <Dn>, <Dm>
- // 1111001x0xxxxxxxxxxx0001xxx0xxxx
new OpcodeARM(Index.arm_vrhadd, "vrhadd", "1111001x0xxxxxxxxxxx0001xxx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.375 VRSHL
+ // Encoding A1 / T1 Advanced SIMD
// vrshl<c>.<type><size> <Qd>, <Qm>, <Qn> vrshl<c>.<type><size> <Dd>, <Dm>, <Dn>
- // 1111001x0xxxxxxxxxxx0101xxx0xxxx
new OpcodeARM(Index.arm_vrshl, "vrshl", "1111001x0xxxxxxxxxxx0101xxx0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.376 VRSHR
+ // Encoding A1 / T1 Advanced SIMD
// vrshr<c>.<type><size> <Qd>, <Qm>, #<imm> vrshr<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1111001x1xxxxxxxxxxx0010xxx1xxxx
new OpcodeARM(Index.arm_vrshr, "vrshr", "1111001x1xxxxxxxxxxx0010xxx1xxxx"),
- // NEW - Encoding A2 / T2 (U) Advanced SIMD
// A8.6.266 VABA, VABAL
+ // Encoding A2 / T2 Advanced SIMD
// vabal<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1111001x1xxxxxxxxxxx0101x0x0xxxx
- // must follow arm_vceq__imm0
- // must follow arm_vcle
- // must follow arm_vcnt
- // must follow arm_vext
- // must follow arm_vrsqrte
+ // must follow arm_vceq__imm0 in table
+ // must follow arm_vcle in table
+ // must follow arm_vcnt in table
+ // must follow arm_vext in table
+ // must follow arm_vrsqrte in table
new OpcodeARM(Index.arm_vabal, "vabal", "1111001x1xxxxxxxxxxx0101x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.379 VRSQRTS
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vrsqrts<c>.f32 <Qd>, <Qn>, <Qm> vrsqrts<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100x1xxxxxxxxx1111xxx1xxxx
new OpcodeARM(Index.arm_vrsqrts, "vrsqrts", "111100100x1xxxxxxxxx1111xxx1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.380 VRSRA
+ // Encoding A1 / T1 Advanced SIMD
// vrsra<c>.<type><size> <Qd>, <Qm>, #<imm> vrsra<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1111001x1xxxxxxxxxxx0011xxx1xxxx
new OpcodeARM(Index.arm_vrsra, "vrsra", "1111001x1xxxxxxxxxxx0011xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.381 VRSUBHN
+ // Encoding A1 / T1 Advanced SIMD
// vrsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 111100111xxxxxxxxxxx0110x0x0xxxx
new OpcodeARM(Index.arm_vrsubhn, "vrsubhn", "111100111xxxxxxxxxxx0110x0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.382 VSHL (immediate)
+ // Encoding A1 / T1 Advanced SIMD
// vshl<c>.i<size> <Qd>, <Qm>, #<imm> vshl<c>.i<size> <Dd>, <Dm>, #<imm>
- // 111100101xxxxxxxxxxx0101xxx1xxxx
new OpcodeARM(Index.arm_vshl__imm, "vshl.i", "111100101xxxxxxxxxxx0101xxx1xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.383 VSHL (register)
+ // Encoding A1 / T1 Advanced SIMD
// vshl<c>.i<size> <Qd>, <Qm>, <Qn> vshl<c>.i<size> <Dd>, <Dm>, <Dn>
- // 1111001x0xxxxxxxxxxx0100xxx0xxxx
new OpcodeARM(Index.arm_vshl__reg, "vshl", "1111001x0xxxxxxxxxxx0100xxx0xxxx"),
- // NEW - Encoding A2 / T2 Advanced SIMD
// A8.6.384 VSHLL
+ // Encoding A2 / T2 Advanced SIMD
// vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (<imm> == <size>)
- // 111100111x11xx10xxxx001100x0xxxx
new OpcodeARM(Index.arm_vshll__max, "vshll", "111100111x11xx10xxxx001100x0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.385 VSHR
+ // Encoding A1 / T1 Advanced SIMD
// vshr<c>.<type><size> <Qd>, <Qm>, #<imm> vshr<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1111001x1xxxxxxxxxxx0000xxx1xxxx
new OpcodeARM(Index.arm_vshr, "vshr", "1111001x1xxxxxxxxxxx0000xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.387 VSLI
+ // Encoding A1 / T1 Advanced SIMD
// vsli<c>.<size> <Qd>, <Qm>, #<imm> vsli<c>.<size> <Dd>, <Dm>, #<imm>
- // 111100111xxxxxxxxxxx0101xxx1xxxx
new OpcodeARM(Index.arm_vsli, "vsli.", "111100111xxxxxxxxxxx0101xxx1xxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.388 VSQRT
+ // Encoding A1 / T1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vsqrt<c>.f64 <Dd>, <Dm> vsqrt<c>.f32 <Sd>, <Sm>
- // xxxx11101x110001xxxx101x11x0xxxx
new OpcodeARM(Index.arm_vsqrt, "vsqrt", "xxxx11101x110001xxxx101x11x0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.389 VSRA
+ // Encoding A1 / T1 Advanced SIMD
// vsra<c>.<type><size> <Qd>, <Qm>, #<imm> vsra<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1111001x1xxxxxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.arm_vsra, "vsra", "1111001x1xxxxxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.390 VSRI
+ // Encoding A1 / T1 Advanced SIMD
// vsri<c>.<size> <Qd>, <Qm>, #<imm> vsri<c>.<size> <Dd>, <Dm>, #<imm>
- // 111100111xxxxxxxxxxx0100xxx1xxxx
new OpcodeARM(Index.arm_vsri, "vsri.", "111100111xxxxxxxxxxx0100xxx1xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.391 VST1 (multiple single elements)
+ // Encoding A1 / T1 Advanced SIMD
// vst1<c>.<size> <list>, [<Rn>{@<align>}]{!} vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x00xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.393 VST2 (multiple 2-element structures)
+ // Encoding A1 / T1 Advanced SIMD
// vst2<c>.<size> <list>, [<Rn>{@<align>}]{!} vst2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x00xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.395 VST3 (multiple 3-element structures)
+ // Encoding A1 / T1 Advanced SIMD
// vst3<c>.<size> <list>, [<Rn>{@<align>}]{!} vst3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x00xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.397 VST4 (multiple 4-element structures)
+ // Encoding A1 / T1 Advanced SIMD
// vst4<c>.<size> <list>, [<Rn>{@<align>}]{!} vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101000x00xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_vst__multi, "vst", "111101000x00xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.392 VST1 (single element from one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vst1<c>.<size> <list>, [<Rn>{@<align>}]{!} vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x00xxxxxxxxxx00xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.394 VST2 (single 2-element structure from one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vst2<c>.<size> <list>, [<Rn>{@<align>}]{!} vst2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x00xxxxxxxxxx01xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.396 VST3 (single 3-element structure from one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vst3<c>.<size> <list>, [<Rn>]{!} vst3<c>.<size> <list>, [<Rn>], <Rm>
- // 111101001x00xxxxxxxxxx10xxxxxxxx
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.398 VST4 (single 4-element structure from one lane)
+ // Encoding A1 / T1 Advanced SIMD
// vst4<c>.<size> <list>, [<Rn>{@<align>}]{!} vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 111101001x00xxxxxxxxxx11xxxxxxxx
- //
+ //
new OpcodeARM(Index.arm_vst__xlane, "vst", "111101001x00xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.355 VPUSH
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vpush<c> <list> <list> is consecutive 64-bit registers
- // xxxx11010x101101xxxx1011xxxxxxxx
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3
// A8.6.355 VPUSH
+ // Encoding A2 / T2 VFPv2, VFPv3
// vpush<c> <list> <list> is consecutive 32-bit registers
- // xxxx11010x101101xxxx1010xxxxxxxx
- // must precede arm_vstm_1 in search table
- // must precede arm_vstm_2 in search table
+ // must precede arm_vstm_1 in table
+ // must precede arm_vstm_2 in table
new OpcodeARM(Index.arm_vpush, "vpush", "xxxx11010x101101xxxx101xxxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.400 VSTR
+ // Encoding A1 / T1 VFPv2, VFPv3, Advanced SIMD
// vstr<c> <Dd>, [<Rn>{, #+/-<imm>}]
- // xxxx1101xx00xxxxxxxx1011xxxxxxxx
- // must precede arm_vstm_1 in search table
+ // must precede arm_vstm_1 in table
new OpcodeARM(Index.arm_vstr__64, "vstr", "xxxx1101xx00xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) Advanced SIMD
// A8.6.399 VSTM
+ // Encoding A1 / T1 Advanced SIMD
// vstm{mode}<c> <Rn>{!}, <list> <list> is consecutive 64-bit registers
- // xxxx110xxxx0xxxxxxxx1011xxxxxxxx
- // must follow arm_vpush in search table
- // must follow arm_vstr_1 in search table
+ // must follow arm_vpush in table
+ // must follow arm_vstr_1 in table
new OpcodeARM(Index.arm_vstm__64, "vstm", "xxxx110xxxx0xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3
// A8.6.400 VSTR
+ // Encoding A2 / T2 VFPv2, VFPv3
// vstr<c> <Sd>, [<Rn>{, #+/-<imm>}]
- // xxxx1101xx00xxxxxxxx1010xxxxxxxx
- // must precede arm_vstm_2 in search table
+ // must precede arm_vstm_2 in table
new OpcodeARM(Index.arm_vstr__32, "vstr", "xxxx1101xx00xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3
// A8.6.399 VSTM
+ // Encoding A2 / T2 VFPv2, VFPv3
// vstm{mode}<c> <Rn>{!}, <list> <list> is consecutive 32-bit registers
- // xxxx110xxxx0xxxxxxxx1010xxxxxxxx
- // must follow arm_vpush in search table
- // must follow arm_vstr_2 in search table
+ // must follow arm_vpush in table
+ // must follow arm_vstr_2 in table
new OpcodeARM(Index.arm_vstm__32, "vstm", "xxxx110xxxx0xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.401 VSUB (integer)
+ // Encoding A1 / T1 Advanced SIMD
// vsub<c>.<dt> <Qd>, <Qn>, <Qm> vsub<c>.<dt> <Dd>, <Dn>, <Dm>
- // 111100110xxxxxxxxxxx1000xxx0xxxx
new OpcodeARM(Index.arm_vsub__int, "vsub", "111100110xxxxxxxxxxx1000xxx0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.402 VSUB (floating-point)
+ // Encoding A1 / T1 Advanced SIMD (UNDEFINED in integer-only variant)
// vsub<c>.f32 <Qd>, <Qn>, <Qm> vsub<c>.f32 <Dd>, <Dn>, <Dm>
- // 111100100x1xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.arm_vsub__f32, "vsub", "111100100x1xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding A2 / T2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.402 VSUB (floating-point)
+ // Encoding A2 / T2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vsub<c>.f64 <Dd>, <Dn>, <Dm> vsub<c>.f32 <Sd>, <Sn>, <Sm>
- // xxxx11100x11xxxxxxxx101xx1x0xxxx
new OpcodeARM(Index.arm_vsub__fp_f, "vsub", "xxxx11100x11xxxxxxxx101xx1x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.403 VSUBHN
+ // Encoding A1 / T1 Advanced SIMD
// vsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 111100101xxxxxxxxxxx0110x0x0xxxx
new OpcodeARM(Index.arm_vsubhn, "vsubhn", "111100101xxxxxxxxxxx0110x0x0xxxx"),
- // NEW - Encoding A1 / T1 (U) Advanced SIMD
// A8.6.404 VSUBL, VSUBW
+ // Encoding A1 / T1 Advanced SIMD
// vsubl<c>.<dt> <Qd>, <Dn>, <Dm> vsubw<c>.<dt> {<Qd>,} <Qn>, <Dm>
- // 1111001x1xxxxxxxxxxx001xx0x0xxxx
new OpcodeARM(Index.arm_vsubl_vsubw, "vsub", "1111001x1xxxxxxxxxxx001xx0x0xxxx"),
- // NEW - Encoding A1 / T1 Advanced SIMD
// A8.6.408 VTST
+ // Encoding A1 / T1 Advanced SIMD
// vtst<c>.<size> <Qd>, <Qn>, <Qm> vtst<c>.<size> <Dd>, <Dn>, <Dm>
- // 111100100xxxxxxxxxxx1000xxx1xxxx
new OpcodeARM(Index.arm_vtst, "vtst", "111100100xxxxxxxxxxx1000xxx1xxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.19 BIC (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// bic{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0011110xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_bic__imm, "bic", "xxxx0011110xxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.32 CMN (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cmn<c> <Rn>,#<const>
- // xxxx00110111xxxx(0)(0)(0)(0)xxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx00110111xxxx(0)(0)(0)(0)xxxxxxxxxxxx
new OpcodeARM(Index.arm_cmn__imm, "cmn", "xxxx00110111xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.35 CMP (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cmp<c> <Rn>,#<const>
- // xxxx00110101xxxx(0)(0)(0)(0)xxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx00110101xxxx(0)(0)(0)(0)xxxxxxxxxxxx
new OpcodeARM(Index.arm_cmp__imm, "cmp", "xxxx00110101xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv6T2, ARMv7
// A8.6.99 MOVT
+ // Encoding A1 ARMv6T2, ARMv7
// movt<c> <Rd>,#<imm16>
- // xxxx00110100xxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_movt, "movt", "xxxx00110100xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.103 MSR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// msr<c> <spec_reg>,#<const>
- // xxxx00110010xx00(1)(1)(1)(1)xxxxxxxxxxxx
- // must precede arm_msr__sys_imm in search table
- // must follow arm_nop in search table
- // must follow arm_sev in search table
- // must follow arm_wfe in search table
- // must follow arm_wfi in search table
- // must follow arm_yield in search table
+ // Unpredictable if (1) is 0: xxxx00110010xx00(1)(1)(1)(1)xxxxxxxxxxxx
+ // must precede arm_msr__sys_imm in table
+ // must follow arm_nop in table
+ // must follow arm_sev in table
+ // must follow arm_wfe in table
+ // must follow arm_wfi in table
+ // must follow arm_yield in table
new OpcodeARM(Index.arm_msr__imm, "msr", "xxxx00110010xx00xxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// B6.1.6 MSR (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// msr<c> <spec_reg>,#<const>
- // xxxx00110x10xxxx(1)(1)(1)(1)xxxxxxxxxxxx
- // must follow arm_msr__imm in table
+ // Unpredictable if (1) is 0: xxxx00110x10xxxx(1)(1)(1)(1)xxxxxxxxxxxx
+ // must follow arm_msr__imm in table in table
new OpcodeARM(Index.arm_msr__sys_imm, "msr", "xxxx00110x10xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.106 MVN (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mvn{s}<c> <Rd>,#<const>
- // xxxx0011111x(0)(0)(0)(0)xxxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: xxxx0011111x(0)(0)(0)(0)xxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_mvn__imm, "mvn", "xxxx0011111xxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.142 RSB (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rsb{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010011xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_rsb__imm, "rsb", "xxxx0010011xxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.145 RSC (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// rsc{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010111xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_rsc__imm, "rsc", "xxxx0010111xxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.151 SBC (immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// sbc{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010110xxxxxxxxxxxxxxxxxxxxx
new OpcodeARM(Index.arm_sbc__imm, "sbc", "xxxx0010110xxxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.199 STRBT
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// strbt<c> <Rt>,[<Rn>],#+/-<imm12>
- // xxxx0100x110xxxxxxxxxxxxxxxxxxxx
- // must precede arm_strb__imm in search table
+ // must precede arm_strb__imm in table
new OpcodeARM(Index.arm_strbt__imm, "strbt", "xxxx0100x110xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.197 STRB (immediate, ARM)
- // strb<c> <Rt>,[<Rn>{,#+/-<imm12>}] strb<c> <Rt>,[<Rn>],#+/-<imm12> strb<c> <Rt>,[<Rn>,#+/-<imm12>]!
- // xxxx010xx1x0xxxxxxxxxxxxxxxxxxxx
- // must follow arm_strbt__imm in search table
- new OpcodeARM(Index.arm_strb__imm, "strb", "xxxx010xx1x0xxxxxxxxxxxxxxxxxxxx"),
// Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // strb<c> <Rt>,[<Rn>{,#+/-<imm12>}] strb<c> <Rt>,[<Rn>],#+/-<imm12> strb<c> <Rt>,[<Rn>,#+/-<imm12>]!
+ // must follow arm_strbt__imm in table
+ new OpcodeARM(Index.arm_strb__imm, "strb", "xxxx010xx1x0xxxxxxxxxxxxxxxxxxxx"),
// A8.6.212 SUB (immediate, ARM)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// sub{s}<c> <Rd>,<Rn>,#<const>
- // xxxx0010010xxxxxxxxxxxxxxxxxxxxx
- // must follow arm_adr__lower in search table
+ // A8.6.215 SUB (SP minus immediate)
+ // Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // sub{s}<c> <Rd>,sp,#<const>
+ //
+ // must follow arm_adr__lower in table
new OpcodeARM(Index.arm_sub__imm, "sub", "xxxx0010010xxxxxxxxxxxxxxxxxxxxx"),
// Coprocessor instructions
-
- // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
+
// A8.6.28 CDP, CDP2
+ // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
// cdp2<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- // 11111110xxxxxxxxxxxxxxxxxxx0xxxx
- // must precede arm_cdp in the search table
+ // must precede arm_cdp in table
new OpcodeARM(Index.arm_cdp2, "cdp2", "11111110xxxxxxxxxxxxxxxxxxx0xxxx"),
- // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.28 CDP, CDP2
+ // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// cdp<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- // xxxx1110xxxxxxxxxxxxxxxxxxx0xxxx
- // must follow arm_cdp2 in the search table
+ // must follow arm_cdp2 in table
new OpcodeARM(Index.arm_cdp, "cdp", "xxxx1110xxxxxxxxxxxxxxxxxxx0xxxx"),
- // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
// A8.6.92 MCR, MCR2
+ // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
// mcr2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // 11111110xxx0xxxxxxxxxxxxxxx1xxxx
- // must precede arm_mcr in the search table
+ // must precede arm_mcr in table
new OpcodeARM(Index.arm_mcr2, "mcr2", "11111110xxx0xxxxxxxxxxxxxxx1xxxx"),
- // Encoding A1 / T2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.92 MCR, MCR2
+ // Encoding A1 / T2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mcr<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // xxxx1110xxx0xxxxxxxxxxxxxxx1xxxx
- // must follow arm_mcr2 in the search table
+ // must follow arm_mcr2 in table
new OpcodeARM(Index.arm_mcr, "mcr", "xxxx1110xxx0xxxxxxxxxxxxxxx1xxxx"),
- // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
// A8.6.100 MRC, MRC2
+ // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
// mrc2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // 11111110xxx1xxxxxxxxxxxxxxx1xxxx
- // must precede arm_mrc in the search table
+ // must precede arm_mrc in table
new OpcodeARM(Index.arm_mrc2, "mrc2", "11111110xxx1xxxxxxxxxxxxxxx1xxxx"),
- // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// A8.6.100 MRC, MRC2
+ // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
// mrc<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // xxxx1110xxx1xxxxxxxxxxxxxxx1xxxx
- // must follow arm_mrc2 in the search table
+ // must follow arm_mrc2 in table
new OpcodeARM(Index.arm_mrc, "mrc", "xxxx1110xxx1xxxxxxxxxxxxxxx1xxxx"),
+ // A8.6.101 MRRC, MRRC2
// Encoding A2 / T1 ARMv6*, ARMv7
- // A8.6.101 MRRC, MRRC2
// mrrc2<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
- // 111111000101xxxxxxxxxxxxxxxxxxxx
- // must precede arm_mrrc in the search table
- // must precede arm_ldc__lit in the search table
- // must precede arm_ldc__imm in the search table
+ // must precede arm_mrrc in table
+ // must precede arm_ldc__lit in table
+ // must precede arm_ldc__imm in table
new OpcodeARM(Index.arm_mrrc2, "mrrc2", "111111000101xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 / T1 ARMv5TE*, ARMv6*, ARMv7
// A8.6.101 MRRC, MRRC2
- // mrrc<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
- // xxxx11000101xxxxxxxxxxxxxxxxxxxx
- // must follow arm_mrrc2 in the search table
- // must precede arm_ldc__lit in the search table
- // must precede arm_ldc__imm in the search table
- new OpcodeARM(Index.arm_mrrc, "mrrc", "xxxx11000101xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
- // A8.6.52 LDC, LDC2 (literal)
- // ldc2{l}<c> <coproc>,<CRd>,<label> ldc2{l}<c> <coproc>,<CRd>,[pc,#-0] Special case ldc2{l}<c> <coproc>,<CRd>,[pc],<option>
- // 1111110xxxx11111xxxxxxxxxxxxxxxx
- // must precede arm_ldc__imm in search table
- // must follow arm_mrrc in search table
- // must follow arm_mrrc2 in search table
- new OpcodeARM(Index.arm_ldc2__lit, "ldc2", "1111110xxxx11111xxxxxxxxxxxxxxxx"),
- // NEW - Encoding A1 / T1 (cond) ARMv4*, ARMv5T*, ARMv6*, ARMv7
- // A8.6.52 LDC, LDC2 (literal)
- // ldc{l}<c> <coproc>,<CRd>,<label> ldc{l}<c> <coproc>,<CRd>,[pc,#-0] Special case ldc{l}<c> <coproc>,<CRd>,[pc],<option>
- // xxxx110xxxx11111xxxxxxxxxxxxxxxx
- // must follow arm_ldc2__lit in search table
- // must precede arm_ldc2__imm in search table
- new OpcodeARM(Index.arm_ldc__lit, "ldc", "xxxx110xxxx11111xxxxxxxxxxxxxxxx"),
- // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
- // A8.6.51 LDC, LDC2 (immediate)
- // ldc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> ldc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // 1111110xxxx1xxxxxxxxxxxxxxxxxxxx
- // must precede arm_ldc__lit in search table
- new OpcodeARM(Index.arm_ldc2__imm, "ldc2", "1111110xxxx1xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
- // A8.6.51 LDC, LDC2 (immediate)
- // ldc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> ldc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // xxxx110xxxx1xxxxxxxxxxxxxxxxxxxx
- // must follow arm_ldc2__imm in search table
- // must follow arm_mrrc in search table
- // must follow arm_mrrc2 in search table
- new OpcodeARM(Index.arm_ldc__imm, "ldc", "xxxx110xxxx1xxxxxxxxxxxxxxxxxxxx"),
- // Encoding A2 / T2 ARMv6*, ARMv7
- // A8.6.93 MCRR, MCRR2
- // mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- // 111111000100xxxxxxxxxxxxxxxxxxxx
- // must precede arm_mcrr in search table
- // must precede arm_stc in search table
- // must precede arm_stc2 in search table
- new OpcodeARM(Index.arm_mcrr2, "mcrr2", "111111000100xxxxxxxxxxxxxxxxxxxx"),
// Encoding A1 / T1 ARMv5TE*, ARMv6*, ARMv7
- // A8.6.93 MCRR, MCRR2
- // mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- // xxxx11000100xxxxxxxxxxxxxxxxxxxx
- // must follow arm_mcrr2 in the search table
- // must precede arm_stc in search table
- // must precede arm_stc2 in search table
- new OpcodeARM(Index.arm_mcrr, "mcrr", "xxxx11000100xxxxxxxxxxxxxxxxxxxx"),
+ // mrrc<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
+ // must follow arm_mrrc2 in table
+ // must precede arm_ldc__lit in table
+ // must precede arm_ldc__imm in table
+ new OpcodeARM(Index.arm_mrrc, "mrrc", "xxxx11000101xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.52 LDC, LDC2 (literal)
// Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
- // A8.6.188 STC, STC2
- // stc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> stc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // 1111110xxxx0xxxxxxxxxxxxxxxxxxxx
- // must precede stc in search table
- // must follow arm_ldc2__lit in search table
- // must follow arm_mcrr in search table
- // must follow arm_mcrr2 in search table
- new OpcodeARM(Index.arm_stc2, "stc2", "1111110xxxx0xxxxxxxxxxxxxxxxxxxx"),
+ // ldc2{l}<c> <coproc>,<CRd>,<label> ldc2{l}<c> <coproc>,<CRd>,[pc,#-0]
+ // Special case ldc2{l}<c> <coproc>,<CRd>,[pc],<option>
+ // must precede arm_ldc__imm in table
+ // must follow arm_mrrc in table
+ // must follow arm_mrrc2 in table
+ new OpcodeARM(Index.arm_ldc2__lit, "ldc2", "1111110xxxx11111xxxxxxxxxxxxxxxx"),
+ // A8.6.52 LDC, LDC2 (literal)
// Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // ldc{l}<c> <coproc>,<CRd>,<label> ldc{l}<c> <coproc>,<CRd>,[pc,#-0]
+ // Special case ldc{l}<c> <coproc>,<CRd>,[pc],<option>
+ // must follow arm_ldc2__lit in table
+ // must precede arm_ldc2__imm in table
+ new OpcodeARM(Index.arm_ldc__lit, "ldc", "xxxx110xxxx11111xxxxxxxxxxxxxxxx"),
+ // A8.6.51 LDC, LDC2 (immediate)
+ // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
+ // ldc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // ldc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // must precede arm_ldc__lit in table
+ new OpcodeARM(Index.arm_ldc2__imm, "ldc2", "1111110xxxx1xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.51 LDC, LDC2 (immediate)
+ // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // must follow arm_ldc2__imm in table
+ // must follow arm_mrrc in table
+ // must follow arm_mrrc2 in table
+ new OpcodeARM(Index.arm_ldc__imm, "ldc", "xxxx110xxxx1xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.93 MCRR, MCRR2
+ // Encoding A2 / T2 ARMv6*, ARMv7
+ // mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ // must precede arm_mcrr in table
+ // must precede arm_stc in table
+ // must precede arm_stc2 in table
+ new OpcodeARM(Index.arm_mcrr2, "mcrr2", "111111000100xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.93 MCRR, MCRR2
+ // Encoding A1 / T1 ARMv5TE*, ARMv6*, ARMv7
+ // mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ // must follow arm_mcrr2 in table
+ // must precede arm_stc in table
+ // must precede arm_stc2 in table
+ new OpcodeARM(Index.arm_mcrr, "mcrr", "xxxx11000100xxxxxxxxxxxxxxxxxxxx"),
// A8.6.188 STC, STC2
- // stc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> stc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // xxxx110xxxx0xxxxxxxxxxxxxxxxxxxx
- // must follow arm_ldc2__lit in search table
- // must follow arm_stc2 in search table
- // must follow arm_mcrr in search table
- // must follow arm_mcrr2 in search table
+ // Encoding A2 / T2 ARMv5T*, ARMv6*, ARMv7
+ // stc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // stc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // must precede stc in table
+ // must follow arm_ldc2__lit in table
+ // must follow arm_mcrr in table
+ // must follow arm_mcrr2 in table
+ new OpcodeARM(Index.arm_stc2, "stc2", "1111110xxxx0xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.188 STC, STC2
+ // Encoding A1 / T1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
+ // stc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // stc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // must follow arm_ldc2__lit in table
+ // must follow arm_stc2 in table
+ // must follow arm_mcrr in table
+ // must follow arm_mcrr2 in table
new OpcodeARM(Index.arm_stc, "stc", "xxxx110xxxx0xxxxxxxxxxxxxxxxxxxx"),
new OpcodeARM(Index.arm_undefined, "undefined", "111001111111xxxxxxxxxxxxxxx1xxxx"),
};
+ // Reference manual citations (e.g., "A8.6.97") refer to sections in the ARM Architecture
+ // Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
public static final OpcodeARM thumb_opcode_table[] = {
- new OpcodeARM(Index.thumb_undefined, "undefined", "11011110xxxxxxxx"), // needs to precede 'b' since it overloads 'b' with invalid condition
+ // must precede thumb_b_1 in table
+ new OpcodeARM(Index.thumb_undefined, "undefined", "11011110xxxxxxxx"),
+ // A8.6.97 MOV (register)
// Encoding T1 ARMv6*, ARMv7 if <Rd> and <Rm> both from R0-R7; ARMv4T, ARMv5T*, ARMv6*, ARMv7 otherwise
- // A8.6.97 MOV (register)
// mov<c> <Rd>,<Rm> If <Rd> is the PC, must be outside or last in IT block.
- // 01000110xxxxxxxx
new OpcodeARM(Index.thumb_mov__reg, "mov", "01000110xxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.2 ADC (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// adcs <Rdn>,<Rm> Outside IT block. adc<c> <Rdn>,<Rm> Inside IT block.
- // 0100000101xxxxxx
new OpcodeARM(Index.thumb_adc, "adc", "0100000101xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.4 ADD (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// adds <Rd>,<Rn>,#<imm3> Outside IT block. add<c> <Rd>,<Rn>,#<imm3> Inside IT block.
- // 0001110xxxxxxxxx
new OpcodeARM(Index.thumb_add__reg_imm, "add", "0001110xxxxxxxxx"),
- // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.8 ADD (SP plus immediate)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// add<c> sp,sp,#<imm>
- // 101100000xxxxxxx
new OpcodeARM(Index.thumb_add__imm_to_sp, "add", "101100000xxxxxxx"),
- // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.4 ADD (immediate, Thumb)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// adds <Rdn>,#<imm8> Outside IT block. add<c> <Rdn>,#<imm8> Inside IT block.
- // 00110xxxxxxxxxxx
new OpcodeARM(Index.thumb_add__imm, "add", "00110xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.6 ADD (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// adds <Rd>,<Rn>,<Rm> Outside IT block. add<c> <Rd>,<Rn>,<Rm> Inside IT block.
- // 0001100xxxxxxxxx
new OpcodeARM(Index.thumb_add__reg_reg, "add", "0001100xxxxxxxxx"),
-// // NEW - Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
-// // A8.6.9 ADD (SP plus register)
-// // add<c> <Rdm>, sp, <Rdm>
-// // 01000100x1101xxx
-// SEE thumb_add__reg
-// new OpcodeARM(Index.thumb_add__sp_reg, "add", "01000100x1101xxx"),
-// // NEW - Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
-// // A8.6.9 ADD (SP plus register)
-// // add<c> sp,<Rm>
-// // 010001001xxxx101
-// SEE thumb_add__reg
-// new OpcodeARM(Index.thumb_add__reg_to_sp, "add", "010001001xxxx101"),
- // Encoding T2 ARMv6T2, ARMv7 if <Rdn> and <Rm> are both from R0-R7; ARMv4T, ARMv5T*, ARMv6*, ARMv7 otherwise
// A8.6.6 ADD (register)
+ // Encoding T2 ARMv6T2, ARMv7 if <Rdn> and <Rm> are both from R0-R7; ARMv4T, ARMv5T*, ARMv6*, ARMv7 otherwise
// add<c> <Rdn>,<Rm> If <Rdn> is the PC, must be outside or last in IT block.
- // 01000100xxxxxxxx
+ // A8.6.9 ADD (SP plus register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // add<c> <Rdm>, sp, <Rdm>
+ // A8.6.9 ADD (SP plus register)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // add<c> sp,<Rm>
+ //
new OpcodeARM(Index.thumb_add__reg, "add", "01000100xxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.8 ADD (SP plus immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// add<c> <Rd>,sp,#<imm>
- // 10101xxxxxxxxxxx
new OpcodeARM(Index.thumb_add__sp_imm, "add", "10101xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.10 ADR
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// adr<c> <Rd>,<label> add <Rd>,pc,imm8 Alternative form
- // 10100xxxxxxxxxxx
new OpcodeARM(Index.thumb_adr, "add", "10100xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.12 AND (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// ands <Rdn>,<Rm> Outside IT block. and<c> <Rdn>,<Rm> Inside IT block.
- // 0100000000xxxxxx
new OpcodeARM(Index.thumb_and, "and", "0100000000xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.14 ASR (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// asrs <Rd>,<Rm>,#<imm> Outside IT block. asr<c> <Rd>,<Rm>,#<imm> Inside IT block.
- // 00010xxxxxxxxxxx
new OpcodeARM(Index.thumb_asr__imm, "asr", "00010xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.15 ASR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// asrs <Rdn>,<Rm> Outside IT block. asr<c> <Rdn>,<Rm> Inside IT block.
- // 0100000100xxxxxx
new OpcodeARM(Index.thumb_asr__reg, "asr", "0100000100xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.218 SVC (previously SWI)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// svc<c> #<imm8>
- // 11011111xxxxxxxx
- // must precede thumb_b_1 in search table
+ // must precede thumb_b_1 in table
new OpcodeARM(Index.thumb_svc, "svc", "11011111xxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.16 B
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// b<c> <label> Not permitted in IT block.
- // 1101xxxxxxxxxxxx
- // must follow thumb_b_1 in search table
+ // must follow thumb_b_1 in table
new OpcodeARM(Index.thumb_b_1, "b", "1101xxxxxxxxxxxx"),
- // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.16 B
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// b<c> <label> Outside or last in IT block
- // 11100xxxxxxxxxxx
new OpcodeARM(Index.thumb_b_2, "b", "11100xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.20 BIC (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// bics <Rdn>,<Rm> Outside IT block. bic<c> <Rdn>,<Rm> Inside IT block.
- // 0100001110xxxxxx
new OpcodeARM(Index.thumb_bic, "bic", "0100001110xxxxxx"),
- // Encoding T1 ARMv5T*, ARMv6*, ARMv7
// A8.6.22 BKPT
- // bkpt #<imm8>
- // 10111110xxxxxxxx
- new OpcodeARM(Index.thumb_bkpt, "bkpt", "10111110xxxxxxxx"),
// Encoding T1 ARMv5T*, ARMv6*, ARMv7
+ // bkpt #<imm8>
+ new OpcodeARM(Index.thumb_bkpt, "bkpt", "10111110xxxxxxxx"),
// A8.6.24 BLX (register)
+ // Encoding T1 ARMv5T*, ARMv6*, ARMv7
// blx<c> <Rm> Outside or last in IT block
- // 010001111xxxx(0)(0)(0)
+ // Unpredictable if (0) is 1: 010001111xxxx(0)(0)(0)
new OpcodeARM(Index.thumb_blx, "blx", "010001111xxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.25 BX
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// bx<c> <Rm> Outside or last in IT block
- // 010001110xxxx(0)(0)(0)
+ // Unpredictable if (0) is 1: 010001110xxxx(0)(0)(0)
new OpcodeARM(Index.thumb_bx, "bx", "010001110xxxxxxx"),
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.27 CBNZ, CBZ
+ // Encoding T1 ARMv6T2, ARMv7
// cb{n}z <Rn>,<label> Not permitted in IT block.
- // 1011x0x1xxxxxxxx
new OpcodeARM(Index.thumb_cbnz_cbz, "cb", "1011x0x1xxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.33 CMN (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// cmn<c> <Rn>,<Rm>
- // 0100001011xxxxxx
new OpcodeARM(Index.thumb_cmn, "cmn", "0100001011xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.35 CMP (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// cmp<c> <Rn>,#<imm8>
- // 00101xxxxxxxxxxx
new OpcodeARM(Index.thumb_cmp__imm, "cmp", "00101xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.36 CMP (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// cmp<c> <Rn>,<Rm> <Rn> and <Rm> both from R0-R7
- // 0100001010xxxxxx
new OpcodeARM(Index.thumb_cmp__reg, "cmp", "0100001010xxxxxx"),
- // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.36 CMP (register)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// cmp<c> <Rn>,<Rm> <Rn> and <Rm> not both from R0-R7
- // 01000101xxxxxxxx
new OpcodeARM(Index.thumb_cmp__reg_hi, "cmp", "01000101xxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.45 EOR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// eors <Rdn>,<Rm> Outside IT block. eor<c> <Rdn>,<Rm> Inside IT block.
- // 0100000001xxxxxx
new OpcodeARM(Index.thumb_eor, "eor", "0100000001xxxxxx"),
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.110 NOP
+ // Encoding T1 ARMv6T2, ARMv7
// nop<c>
- // 1011111100000000
- // must precede thumb_it in search table
+ // must precede thumb_it in table
new OpcodeARM(Index.thumb_nop, "nop", "1011111100000000"),
- // NEW - Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.158 SEV
+ // Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// sev<c>
- // 1011111101000000
- // must precede thumb_it in search table
+ // must precede thumb_it in table
new OpcodeARM(Index.thumb_sev, "sev", "1011111101000000"),
- // NEW - Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.411 WFE
+ // Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// wfe<c>
- // 1011111100100000
- // must precede thumb_it in search table
+ // must precede thumb_it in table
new OpcodeARM(Index.thumb_wfe, "wfe", "1011111100100000"),
- // NEW - Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.412 WFI
+ // Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// wfi<c>
- // 1011111100110000
- // must precede thumb_it in search table
+ // must precede thumb_it in table
new OpcodeARM(Index.thumb_wfi, "wfi", "1011111100110000"),
- // NEW - Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.413 YIELD
+ // Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// yield<c>
- // 1011111100010000
- // must precede thumb_it in search table
+ // must precede thumb_it in table
new OpcodeARM(Index.thumb_yield, "yield", "1011111100010000"),
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.50 IT
+ // Encoding T1 ARMv6T2, ARMv7
// it{x{y{z}}} <firstcond> Not permitted in IT block
- // 10111111xxxxxxxx
- // must follow thumb_nop in search table
- // must follow thumb_sev in search table
- // must follow thumb_wfe in search table
- // must follow thumb_wfi in search table
- // must follow thumb_yield in search table
+ // must follow thumb_nop in table
+ // must follow thumb_sev in table
+ // must follow thumb_wfe in table
+ // must follow thumb_wfi in table
+ // must follow thumb_yield in table
new OpcodeARM(Index.thumb_it, "it", "10111111xxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)
// A8.6.53 LDM / LDMIA / LDMFD
- // ldm<c> <Rn>!,<registers> <Rn> not included in <registers> ldm<c> <Rn>,<registers> <Rn> included in <registers>
- // 11001xxxxxxxxxxx
- new OpcodeARM(Index.thumb_ldm, "ldm", "11001xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.57 LDR (immediate, Thumb)
- // ldr<c> <Rt>, [<Rn>{,#<imm>}]
- // 01101xxxxxxxxxxx
- new OpcodeARM(Index.thumb_ldr__imm, "ldr", "01101xxxxxxxxxxx"),
- // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.57 LDR (immediate, Thumb)
- // ldr<c> <Rt>,[sp{,#<imm>}]
- // 10011xxxxxxxxxxx
- new OpcodeARM(Index.thumb_ldr__imm_sp, "ldr", "10011xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.59 LDR (literal)
- // ldr<c> <Rt>,<label>
- // 01001xxxxxxxxxxx
- new OpcodeARM(Index.thumb_ldr__lit, "ldr", "01001xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.60 LDR (register)
- // ldr<c> <Rt>,[<Rn>,<Rm>]
- // 0101100xxxxxxxxx
- new OpcodeARM(Index.thumb_ldr__reg, "ldr", "0101100xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.61 LDRB (immediate, Thumb)
- // ldrb<c> <Rt>,[<Rn>{,#<imm5>}]
- // 01111xxxxxxxxxxx
- new OpcodeARM(Index.thumb_ldrb__imm, "ldrb", "01111xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.64 LDRB (register)
- // ldrb<c> <Rt>,[<Rn>,<Rm>]
- // 0101110xxxxxxxxx
- new OpcodeARM(Index.thumb_ldrb__reg, "ldrb", "0101110xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.73 LDRH (immediate, Thumb)
- // ldrh<c> <Rt>,[<Rn>{,#<imm>}]
- // 10001xxxxxxxxxxx
- new OpcodeARM(Index.thumb_ldrh__imm, "ldrh", "10001xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.76 LDRH (register)
- // ldrh<c> <Rt>,[<Rn>,<Rm>]
- // 0101101xxxxxxxxx
- new OpcodeARM(Index.thumb_ldrh__reg, "ldrh", "0101101xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.80 LDRSB (register)
- // ldrsb<c> <Rt>,[<Rn>,<Rm>]
- // 0101011xxxxxxxxx
- new OpcodeARM(Index.thumb_ldrsb, "ldrsb", "0101011xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.84 LDRSH (register)
- // ldrsh<c> <Rt>,[<Rn>,<Rm>]
- // 0101111xxxxxxxxx
- new OpcodeARM(Index.thumb_ldrsh, "ldrsh", "0101111xxxxxxxxx"),
- // NEW - Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.97 MOV (register)
- // movs <Rd>,<Rm> Not permitted in IT block
- // 0000000000xxxxxx
- // must precede thumb_lsl__imm in search table
- new OpcodeARM(Index.thumb_movs, "movs", "0000000000xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.88 LSL (immediate)
- // lsls <Rd>,<Rm>,#<imm5> Outside IT block. lsl<c> <Rd>,<Rm>,#<imm5> Inside IT block.
- // 00000xxxxxxxxxxx
- // must follow thumb_movs in search table
- new OpcodeARM(Index.thumb_lsl__imm, "lsl", "00000xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.89 LSL (register)
- // lsls <Rdn>,<Rm> Outside IT block. lsl<c> <Rdn>,<Rm> Inside IT block.
- // 0100000010xxxxxx
- new OpcodeARM(Index.thumb_lsl__reg, "lsl", "0100000010xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.90 LSR (immediate)
- // lsrs <Rd>,<Rm>,#<imm> Outside IT block. lsr<c> <Rd>,<Rm>,#<imm> Inside IT block.
- // 00001xxxxxxxxxxx
- new OpcodeARM(Index.thumb_lsr__imm, "lsr", "00001xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.91 LSR (register)
- // lsrs <Rdn>,<Rm> Outside IT block. lsr<c> <Rdn>,<Rm> Inside IT block.
- // 0100000011xxxxxx
- new OpcodeARM(Index.thumb_lsr__reg, "lsr", "0100000011xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.96 MOV (immediate)
- // movs <Rd>,#<imm8> Outside IT block. mov<c> <Rd>,#<imm8> Inside IT block.
- // 00100xxxxxxxxxxx
- new OpcodeARM(Index.thumb_mov__imm, "mov", "00100xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.105 MUL
- // muls <Rdm>,<Rn>,<Rdm> Outside IT block. mul<c> <Rdm>,<Rn>,<Rdm> Inside IT block.
- // 0100001101xxxxxx
- new OpcodeARM(Index.thumb_mul, "mul", "0100001101xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.107 MVN (register)
- // mvns <Rd>,<Rm> Outside IT block. mvn<c> <Rd>,<Rm> Inside IT block.
- // 0100001111xxxxxx
- new OpcodeARM(Index.thumb_mvn, "mvn", "0100001111xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.114 ORR (register)
- // orrs <Rdn>,<Rm> Outside IT block. orr<c> <Rdn>,<Rm> Inside IT block.
- // 0100001100xxxxxx
- new OpcodeARM(Index.thumb_orr, "orr", "0100001100xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.122 POP
- // pop<c> <registers>
- // 1011110xxxxxxxxx
- new OpcodeARM(Index.thumb_pop, "pop", "1011110xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.123 PUSH
- // push<c> <registers>
- // 1011010xxxxxxxxx
- new OpcodeARM(Index.thumb_push, "push", "1011010xxxxxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
- // A8.6.135 REV
- // rev<c> <Rd>,<Rm>
- // 1011101000xxxxxx
- new OpcodeARM(Index.thumb_rev, "rev", "1011101000xxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
- // A8.6.136 REV16
- // rev16<c> <Rd>,<Rm>
- // 1011101001xxxxxx
- new OpcodeARM(Index.thumb_rev16, "rev16", "1011101001xxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
- // A8.6.137 REVSH
- // revsh<c> <Rd>,<Rm>
- // 1011101011xxxxxx
- new OpcodeARM(Index.thumb_revsh, "revsh", "1011101011xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.140 ROR (register)
- // rors <Rdn>,<Rm> Outside IT block. ror<c> <Rdn>,<Rm> Inside IT block.
- // 0100000111xxxxxx
- new OpcodeARM(Index.thumb_ror, "ror", "0100000111xxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.142 RSB (immediate)
- // rsbs <Rd>,<Rn>,#0 Outside IT block. rsb<c> <Rd>,<Rn>,#0 Inside IT block.
- // 0100001001xxxxxx
- new OpcodeARM(Index.thumb_rsb, "rsb", "0100001001xxxxxx"),
- // NEW - Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.152 SBC (register)
- // sbcs <Rdn>,<Rm> Outside IT block. sbc<c> <Rdn>,<Rm> Inside IT block.
- // 0100000110xxxxxx
- new OpcodeARM(Index.thumb_sbc, "sbc", "0100000110xxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
- // A8.6.157 SETEND
- // setend <endian_specifier> Not permitted in IT block
- // 10110110010(1)x(0)(0)(0)
- new OpcodeARM(Index.thumb_setend, "setend", "10110110010xxxxx"),
// Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)
+ // ldm<c> <Rn>!,<registers> <Rn> not included in <registers> ldm<c> <Rn>,<registers> <Rn> included in <registers>
+ new OpcodeARM(Index.thumb_ldm, "ldm", "11001xxxxxxxxxxx"),
+ // A8.6.57 LDR (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldr<c> <Rt>, [<Rn>{,#<imm>}]
+ new OpcodeARM(Index.thumb_ldr__imm, "ldr", "01101xxxxxxxxxxx"),
+ // A8.6.57 LDR (immediate, Thumb)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldr<c> <Rt>,[sp{,#<imm>}]
+ new OpcodeARM(Index.thumb_ldr__imm_sp, "ldr", "10011xxxxxxxxxxx"),
+ // A8.6.59 LDR (literal)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldr<c> <Rt>,<label>
+ new OpcodeARM(Index.thumb_ldr__lit, "ldr", "01001xxxxxxxxxxx"),
+ // A8.6.60 LDR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldr<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_ldr__reg, "ldr", "0101100xxxxxxxxx"),
+ // A8.6.61 LDRB (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldrb<c> <Rt>,[<Rn>{,#<imm5>}]
+ new OpcodeARM(Index.thumb_ldrb__imm, "ldrb", "01111xxxxxxxxxxx"),
+ // A8.6.64 LDRB (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldrb<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_ldrb__reg, "ldrb", "0101110xxxxxxxxx"),
+ // A8.6.73 LDRH (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldrh<c> <Rt>,[<Rn>{,#<imm>}]
+ new OpcodeARM(Index.thumb_ldrh__imm, "ldrh", "10001xxxxxxxxxxx"),
+ // A8.6.76 LDRH (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldrh<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_ldrh__reg, "ldrh", "0101101xxxxxxxxx"),
+ // A8.6.80 LDRSB (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldrsb<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_ldrsb, "ldrsb", "0101011xxxxxxxxx"),
+ // A8.6.84 LDRSH (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // ldrsh<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_ldrsh, "ldrsh", "0101111xxxxxxxxx"),
+ // A8.6.97 MOV (register)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // movs <Rd>,<Rm> Not permitted in IT block
+ // must precede thumb_lsl__imm in table
+ new OpcodeARM(Index.thumb_movs, "movs", "0000000000xxxxxx"),
+ // A8.6.88 LSL (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // lsls <Rd>,<Rm>,#<imm5> Outside IT block. lsl<c> <Rd>,<Rm>,#<imm5> Inside IT block.
+ // must follow thumb_movs in table
+ new OpcodeARM(Index.thumb_lsl__imm, "lsl", "00000xxxxxxxxxxx"),
+ // A8.6.89 LSL (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // lsls <Rdn>,<Rm> Outside IT block. lsl<c> <Rdn>,<Rm> Inside IT block.
+ new OpcodeARM(Index.thumb_lsl__reg, "lsl", "0100000010xxxxxx"),
+ // A8.6.90 LSR (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // lsrs <Rd>,<Rm>,#<imm> Outside IT block. lsr<c> <Rd>,<Rm>,#<imm> Inside IT block.
+ new OpcodeARM(Index.thumb_lsr__imm, "lsr", "00001xxxxxxxxxxx"),
+ // A8.6.91 LSR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // lsrs <Rdn>,<Rm> Outside IT block. lsr<c> <Rdn>,<Rm> Inside IT block.
+ new OpcodeARM(Index.thumb_lsr__reg, "lsr", "0100000011xxxxxx"),
+ // A8.6.96 MOV (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // movs <Rd>,#<imm8> Outside IT block. mov<c> <Rd>,#<imm8> Inside IT block.
+ new OpcodeARM(Index.thumb_mov__imm, "mov", "00100xxxxxxxxxxx"),
+ // A8.6.105 MUL
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // muls <Rdm>,<Rn>,<Rdm> Outside IT block. mul<c> <Rdm>,<Rn>,<Rdm> Inside IT block.
+ new OpcodeARM(Index.thumb_mul, "mul", "0100001101xxxxxx"),
+ // A8.6.107 MVN (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // mvns <Rd>,<Rm> Outside IT block. mvn<c> <Rd>,<Rm> Inside IT block.
+ new OpcodeARM(Index.thumb_mvn, "mvn", "0100001111xxxxxx"),
+ // A8.6.114 ORR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // orrs <Rdn>,<Rm> Outside IT block. orr<c> <Rdn>,<Rm> Inside IT block.
+ new OpcodeARM(Index.thumb_orr, "orr", "0100001100xxxxxx"),
+ // A8.6.122 POP
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // pop<c> <registers>
+ new OpcodeARM(Index.thumb_pop, "pop", "1011110xxxxxxxxx"),
+ // A8.6.123 PUSH
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // push<c> <registers>
+ new OpcodeARM(Index.thumb_push, "push", "1011010xxxxxxxxx"),
+ // A8.6.135 REV
+ // Encoding T1 ARMv6*, ARMv7
+ // rev<c> <Rd>,<Rm>
+ new OpcodeARM(Index.thumb_rev, "rev", "1011101000xxxxxx"),
+ // A8.6.136 REV16
+ // Encoding T1 ARMv6*, ARMv7
+ // rev16<c> <Rd>,<Rm>
+ new OpcodeARM(Index.thumb_rev16, "rev16", "1011101001xxxxxx"),
+ // A8.6.137 REVSH
+ // Encoding T1 ARMv6*, ARMv7
+ // revsh<c> <Rd>,<Rm>
+ new OpcodeARM(Index.thumb_revsh, "revsh", "1011101011xxxxxx"),
+ // A8.6.140 ROR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // rors <Rdn>,<Rm> Outside IT block. ror<c> <Rdn>,<Rm> Inside IT block.
+ new OpcodeARM(Index.thumb_ror, "ror", "0100000111xxxxxx"),
+ // A8.6.142 RSB (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // rsbs <Rd>,<Rn>,#0 Outside IT block. rsb<c> <Rd>,<Rn>,#0 Inside IT block.
+ new OpcodeARM(Index.thumb_rsb, "rsb", "0100001001xxxxxx"),
+ // A8.6.152 SBC (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // sbcs <Rdn>,<Rm> Outside IT block. sbc<c> <Rdn>,<Rm> Inside IT block.
+ new OpcodeARM(Index.thumb_sbc, "sbc", "0100000110xxxxxx"),
+ // A8.6.157 SETEND
+ // Encoding T1 ARMv6*, ARMv7
+ // setend <endian_specifier> Not permitted in IT block
+ // Unpredictable if (1) is 0 or (0) is 1: 10110110010(1)x(0)(0)(0)
+ new OpcodeARM(Index.thumb_setend, "setend", "10110110010xxxxx"),
// A8.6.189 STM / STMIA / STMEA
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)
// stm<c> <Rn>!,<registers>
- // 11000xxxxxxxxxxx
new OpcodeARM(Index.thumb_stm, "stm", "11000xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.193 STR (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// str<c> <Rt>, [<Rn>{,#<imm>}]
- // 01100xxxxxxxxxxx
new OpcodeARM(Index.thumb_str__imm, "str", "01100xxxxxxxxxxx"),
- // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.193 STR (immediate, Thumb)
- // str<c> <Rt>,[sp,#<imm>]
- // 10010xxxxxxxxxxx
- new OpcodeARM(Index.thumb_str__imm_sp, "str", "10010xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.195 STR (register)
- // str<c> <Rt>,[<Rn>,<Rm>]
- // 0101000xxxxxxxxx
- new OpcodeARM(Index.thumb_str__reg, "str", "0101000xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.196 STRB (immediate, Thumb)
- // strb<c> <Rt>,[<Rn>,#<imm5>]
- // 01110xxxxxxxxxxx
- new OpcodeARM(Index.thumb_strb__imm, "strb", "01110xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.198 STRB (register)
- // strb<c> <Rt>,[<Rn>,<Rm>]
- // 0101010xxxxxxxxx
- new OpcodeARM(Index.thumb_strb__reg, "strb", "0101010xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.206 STRH (immediate, Thumb)
- // strh<c> <Rt>,[<Rn>{,#<imm>}]
- // 10000xxxxxxxxxxx
- new OpcodeARM(Index.thumb_strh__imm, "strh", "10000xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.208 STRH (register)
- // strh<c> <Rt>,[<Rn>,<Rm>]
- // 0101001xxxxxxxxx
- new OpcodeARM(Index.thumb_strh__reg, "strh", "0101001xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
- // A8.6.211 SUB (immediate, Thumb)
- // subs <Rd>,<Rn>,#<imm3> Outside IT block. sub<c> <Rd>,<Rn>,#<imm3> Inside IT block.
- // 0001111xxxxxxxxx
- new OpcodeARM(Index.thumb_sub__reg_imm, "sub", "0001111xxxxxxxxx"),
// Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // str<c> <Rt>,[sp,#<imm>]
+ new OpcodeARM(Index.thumb_str__imm_sp, "str", "10010xxxxxxxxxxx"),
+ // A8.6.195 STR (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // str<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_str__reg, "str", "0101000xxxxxxxxx"),
+ // A8.6.196 STRB (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // strb<c> <Rt>,[<Rn>,#<imm5>]
+ new OpcodeARM(Index.thumb_strb__imm, "strb", "01110xxxxxxxxxxx"),
+ // A8.6.198 STRB (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // strb<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_strb__reg, "strb", "0101010xxxxxxxxx"),
+ // A8.6.206 STRH (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // strh<c> <Rt>,[<Rn>{,#<imm>}]
+ new OpcodeARM(Index.thumb_strh__imm, "strh", "10000xxxxxxxxxxx"),
+ // A8.6.208 STRH (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // strh<c> <Rt>,[<Rn>,<Rm>]
+ new OpcodeARM(Index.thumb_strh__reg, "strh", "0101001xxxxxxxxx"),
// A8.6.211 SUB (immediate, Thumb)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // subs <Rd>,<Rn>,#<imm3> Outside IT block. sub<c> <Rd>,<Rn>,#<imm3> Inside IT block.
+ new OpcodeARM(Index.thumb_sub__reg_imm, "sub", "0001111xxxxxxxxx"),
+ // A8.6.211 SUB (immediate, Thumb)
+ // Encoding T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// subs <Rdn>,#<imm8> Outside IT block. sub<c> <Rdn>,#<imm8> Inside IT block.
- // 00111xxxxxxxxxxx
new OpcodeARM(Index.thumb_sub__imm, "sub", "00111xxxxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.213 SUB (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// subs <Rd>,<Rn>,<Rm> Outside IT block. sub<c> <Rd>,<Rn>,<Rm> Inside IT block.
- // 0001101xxxxxxxxx
new OpcodeARM(Index.thumb_sub__reg_reg, "sub", "0001101xxxxxxxxx"),
- // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// A8.6.215 SUB (SP minus immediate)
- // sub<c> sp,sp,#<imm>
- // 101100001xxxxxxx
- new OpcodeARM(Index.thumb_sub__imm_from_sp, "sub", "101100001xxxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
- // A8.6.223 SXTB
- // sxtb<c> <Rd>,<Rm>
- // 1011001001xxxxxx
- new OpcodeARM(Index.thumb_sxtb, "sxtb", "1011001001xxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
- // A8.6.225 SXTH
- // sxth<c> <Rd>,<Rm>
- // 1011001000xxxxxx
- new OpcodeARM(Index.thumb_sxth, "sxth", "1011001000xxxxxx"),
// Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
+ // sub<c> sp,sp,#<imm>
+ new OpcodeARM(Index.thumb_sub__imm_from_sp, "sub", "101100001xxxxxxx"),
+ // A8.6.223 SXTB
+ // Encoding T1 ARMv6*, ARMv7
+ // sxtb<c> <Rd>,<Rm>
+ new OpcodeARM(Index.thumb_sxtb, "sxtb", "1011001001xxxxxx"),
+ // A8.6.225 SXTH
+ // Encoding T1 ARMv6*, ARMv7
+ // sxth<c> <Rd>,<Rm>
+ new OpcodeARM(Index.thumb_sxth, "sxth", "1011001000xxxxxx"),
// A8.6.231 TST (register)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
// tst<c> <Rn>,<Rm>
- // 0100001000xxxxxx
new OpcodeARM(Index.thumb_tst, "tst", "0100001000xxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
// A8.6.263 UXTB
+ // Encoding T1 ARMv6*, ARMv7
// uxtb<c> <Rd>,<Rm>
- // 1011001011xxxxxx
new OpcodeARM(Index.thumb_uxtb, "uxtb", "1011001011xxxxxx"),
- // Encoding T1 ARMv6*, ARMv7
// A8.6.265 UXTH
- // uxth<c> <Rd>,<Rm>
- // 1011001010xxxxxx
- new OpcodeARM(Index.thumb_uxth, "uxth", "1011001010xxxxxx"),
// Encoding T1 ARMv6*, ARMv7
+ // uxth<c> <Rd>,<Rm>
+ new OpcodeARM(Index.thumb_uxth, "uxth", "1011001010xxxxxx"),
// B6.1.1 CPS
+ // Encoding T1 ARMv6*, ARMv7
// cps<effect> <iflags> Not permitted in IT block.
- // 10110110011x(0)xxx
+ // Unpredictable if (0) is 1: 10110110011x(0)xxx
new OpcodeARM(Index.thumb_cps, "cps", "10110110011xxxxx"),
};
+ // Reference manual citations (e.g., "A8.6.1") refer to sections in the ARM Architecture
+ // Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
public static final OpcodeARM thumb2_opcode_table[] = {
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.1 ADC (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// adc{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 0 1 0 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01010xxxxx0xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_adc__imm, "adc", "11110x01010xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.2 ADC (register)
+ // Encoding T2 ARMv6T2, ARMv7
// adc{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 0 1 0 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011010xxxxx(0)xxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 11101011010xxxxx(0)xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_adc__reg, "adc", "11101011010xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.10 ADR
+ // Encoding T3 ARMv6T2, ARMv7
// adr<c>.w <Rd>,<label>
- // 1 1 1 1 0 i_1_10_10 1 0 0 0 0 0 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x10000011110xxxxxxxxxxxxxxx
- // must precede thumb2_addw in search table
+ // must precede thumb2_addw in table
new OpcodeARM(Index.thumb2_adr__add, "add", "11110x10000011110xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.32 CMN (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// cmn<c> <Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 0 0 0 1 Rn_1_3_0 0 imm3_0_14_12 1 1 1 1 imm8_0_7_0
- // 11110x010001xxxx0xxx1111xxxxxxxx
- // must precede thumb2_add__imm in search table
- // must precede thumb2_addw__imm in search table
+ // must precede thumb2_add__imm in table
+ // must precede thumb2_addw__imm in table
new OpcodeARM(Index.thumb2_cmn__imm, "cmn", "11110x010001xxxx0xxx1111xxxxxxxx"),
-
- // NEW - Encoding T4 ARMv6T2, ARMv7
// A8.6.4 ADD (immediate, Thumb)
+ // Encoding T4 ARMv6T2, ARMv7
// addw<c> <Rd>,<Rn>,#<imm12>
- // 1 1 1 1 0 i_1_10_10 1 0 0 0 0 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x100000xxxx0xxxxxxxxxxxxxxx
- // NEW - Encoding T4 ARMv6T2, ARMv7
// A8.6.8 ADD (SP plus immediate)
+ // Encoding T4 ARMv6T2, ARMv7
// addw <Rd>,sp,#<imm12>
- // 1 1 1 1 0 i_1_10_10 1 0 0 0 0 0 1 1 0 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x10000011010xxxxxxxxxxxxxxx
//
- // must follow thumb2_adr__add in search table
- // must follow thumb2_cmn__imm in search table
- // must precede thumb2_add__imm in search table
+ // must follow thumb2_adr__add in table
+ // must follow thumb2_cmn__imm in table
+ // must precede thumb2_add__imm in table
new OpcodeARM(Index.thumb2_addw, "addw", "11110x100000xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.4 ADD (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
// add{s}<c>.w <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 0 0 0 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01000xxxxx0xxxxxxxxxxxxxxx
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.8 ADD (SP plus immediate)
+ // Encoding T3 ARMv6T2, ARMv7
// add{s}.w <Rd>,sp,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 0 0 0 S_1_4_4 1 1 0 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01000x11010xxxxxxxxxxxxxxx
//
- // must follow thumb2_addw__imm in search table
- // must follow thumb2_cmn__imm in search table
+ // must follow thumb2_addw__imm in table
+ // must follow thumb2_cmn__imm in table
new OpcodeARM(Index.thumb2_add__imm, "add", "11110x01000xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.33 CMN (register)
+ // Encoding T2 ARMv6T2, ARMv7
// cmn<c>.w <Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 0 0 0 1 Rn_1_3_0 (0) imm3_0_14_12 1 1 1 1 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 111010110001xxxx(0)xxx1111xxxxxxxx
- // must precede thumb2_add__reg in search table
+ // Unpredictable if (0) is 1: 111010110001xxxx(0)xxx1111xxxxxxxx
+ // must precede thumb2_add__reg in table
new OpcodeARM(Index.thumb2_cmn__reg, "cmn.w", "111010110001xxxxxxxx1111xxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.6 ADD (register)
+ // Encoding T3 ARMv6T2, ARMv7
// add{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 0 0 0 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011000xxxxx(0)xxxxxxxxxxxxxxx
- // NEW - Encoding T3 ARMv6T2, ARMv7
+ // Unpredictable if (0) is 1: 11101011000xxxxx(0)xxxxxxxxxxxxxxx
// A8.6.9 ADD (SP plus register)
+ // Encoding T3 ARMv6T2, ARMv7
// add{s}<c>.w <Rd>,sp,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 0 0 0 S_1_4_4 1 1 0 1 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011000x11010xxxxxxxxxxxxxxx
//
- // must follow thumb2_cmn__reg in search table
+ // must follow thumb2_cmn__reg in table
new OpcodeARM(Index.thumb2_add__reg, "add", "11101011000xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.10 ADR
+ // Encoding T2 ARMv6T2, ARMv7
// adr<c>.w <Rd>,<label> sub <Rd>,pc,#0 Special case for subtraction of zero
- // 1 1 1 1 0 i_1_10_10 1 0 1 0 1 0 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x10101011110xxxxxxxxxxxxxxx
- // must precede thumb2_subw in search table
+ // must precede thumb2_subw in table
new OpcodeARM(Index.thumb2_adr__sub, "sub", "11110x10101011110xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.230 TST (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// tst<c> <Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 0 0 1 Rn_1_3_0 0 imm3_0_14_12 1 1 1 1 imm8_0_7_0
- // 11110x000001xxxx0xxx1111xxxxxxxx
- // must precede thumb2_and__imm in search table
+ // must precede thumb2_and__imm in table
new OpcodeARM(Index.thumb2_tst__imm, "tst", "11110x000001xxxx0xxx1111xxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.11 AND (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// and{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 0 0 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00000xxxxx0xxxxxxxxxxxxxxx
- // must follow thumb2_and__imm in search table
+ // must follow thumb2_and__imm in table
new OpcodeARM(Index.thumb2_and__imm, "and", "11110x00000xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.231 TST (register)
+ // Encoding T2 ARMv6T2, ARMv7
// tst<c>.w <Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 0 0 0 1 Rn_1_3_0 (0) imm3_0_14_12 1 1 1 1 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 111010100001xxxx(0)xxx1111xxxxxxxx
- // must precede thumb2_and__reg in search table
+ // Unpredictable if (0) is 1: 111010100001xxxx(0)xxx1111xxxxxxxx
+ // must precede thumb2_and__reg in table
new OpcodeARM(Index.thumb2_tst__reg, "tst.w", "111010100001xxxxxxxx1111xxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.12 AND (register)
+ // Encoding T2 ARMv6T2, ARMv7
// and{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 0 0 0 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101010000xxxxx(0)xxxxxxxxxxxxxxx
- // must follow thumb2_and__reg in search table
+ // Unpredictable if (0) is 1: 11101010000xxxxx(0)xxxxxxxxxxxxxxx
+ // must follow thumb2_and__reg in table
new OpcodeARM(Index.thumb2_and__reg, "and", "11101010000xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.14 ASR (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
// asr{s}<c>.w <Rd>,<Rm>,#<imm>
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 1 1 1 1 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 1 0 Rm_0_3_0
- // 11101010010x1111(0)xxxxxxxxx10xxxx
+ // Unpredictable if (0) is 1: 11101010010x1111(0)xxxxxxxxx10xxxx
new OpcodeARM(Index.thumb2_asr__imm, "asr", "11101010010x1111xxxxxxxxxx10xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.15 ASR (register)
+ // Encoding T2 ARMv6T2, ARMv7
// asr{s}<c>.w <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 0 1 0 S_1_4_4 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 11111010010xxxxx1111xxxx0000xxxx
new OpcodeARM(Index.thumb2_asr__reg, "asr", "11111010010xxxxx1111xxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.26 BXJ
+ // Encoding T1 ARMv6T2, ARMv7
// bxj<c> <Rm> Outside or last in IT block
- // 1 1 1 1 0 0 1 1 1 1 0 0 Rm_1_3_0 1 0 (0) 0 (1)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)
- // 111100111100xxxx10(0)0(1)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111100xxxx10(0)0(1)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_bxj, "bxj", "111100111100xxxx10x0xxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv7
// A8.6.30 CLREX
+ // Encoding T1 ARMv7
// clrex<c>
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 0 1 0 (1)(1)(1)(1)
- // 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0010(1)(1)(1)(1)
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0010(1)(1)(1)(1)
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_clrex, "clrex", "111100111011xxxx10x0xxxx0010xxxx"),
-
- // NEW - Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.40 DBG
+ // Encoding T1 ARMv7 (executes as NOP in ARMv6T2)
// dbg<c> #<option>
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) 0 0 0 1 1 1 1 option
- // 111100111010(1)(1)(1)(1)10(0)0(0)0001111xxxx
- // must precede thumb2_b__cond in search table
- // must precede thumb2_cps in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)0001111xxxx
+ // must precede thumb2_b__cond in table
+ // must precede thumb2_cps in table
new OpcodeARM(Index.thumb2_dbg, "dbg", "111100111010xxxx10x0x0001111xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.110 NOP
+ // Encoding T2 ARMv6T2, ARMv7
// nop<c>.w
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) 0 0 0 0 0 0 0 0 0 0 0
- // 111100111010(1)(1)(1)(1)10(0)0(0)00000000000
- // must precede thumb2_b__cond in search table
- // must precede thumb2_cps in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)00000000000
+ // must precede thumb2_b__cond in table
+ // must precede thumb2_cps in table
new OpcodeARM(Index.thumb2_nop, "nop.w", "111100111010xxxx10x0x00000000000"),
-
- // NEW - Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.158 SEV
+ // Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// sev<c>.w
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) 0 0 0 0 0 0 0 0 1 0 0
- // 111100111010(1)(1)(1)(1)10(0)0(0)00000000100
- // must precede thumb2_b__cond in search table
- // must precede thumb2_cps in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)00000000100
+ // must precede thumb2_b__cond in table
+ // must precede thumb2_cps in table
new OpcodeARM(Index.thumb2_sev, "sev.w", "111100111010xxxx10x0x00000000100"),
-
- // NEW - Encoding T1 Security Extensions (not in ARMv6K)
// B6.1.9 SMC (previously SMI)
+ // Encoding T1 Security Extensions (not in ARMv6K)
// smc<c> #<imm4>
- // 1 1 1 1 0 1 1 1 1 1 1 1 imm4_1_3_0 1 0 0 0 (0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
- // 111101111111xxxx1000(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 111101111111xxxx1000(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
new OpcodeARM(Index.thumb2_smc, "smc", "111101111111xxxx1000xxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.411 WFE
+ // Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// wfe<c>.w
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) 0 0 0 0 0 0 0 0 0 1 0
- // 111100111010(1)(1)(1)(1)10(0)0(0)00000000010
- // must precede thumbw_b__cond in search table
- // must precede thumb2_cps in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)00000000010
+ // must precede thumbw_b__cond in table
+ // must precede thumb2_cps in table
new OpcodeARM(Index.thumb2_wfe, "wfe.w", "111100111010xxxx10x0x00000000010"),
-
- // NEW - Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.412 WFI
+ // Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// wfi<c>.w
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) 0 0 0 0 0 0 0 0 0 1 1
- // 111100111010(1)(1)(1)(1)10(0)0(0)00000000011
- // must precede thumbw_b__cond in search table
- // must precede thumb2_cps in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)00000000011
+ // must precede thumbw_b__cond in table
+ // must precede thumb2_cps in table
new OpcodeARM(Index.thumb2_wfi, "wfi.w", "111100111010xxxx10x0x00000000011"),
-
- // NEW - Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// A8.6.413 YIELD
+ // Encoding T2 ARMv7 (executes as NOP in ARMv6T2)
// yield<c>.w
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) 0 0 0 0 0 0 0 0 0 0 1
- // 111100111010(1)(1)(1)(1)10(0)0(0)00000000001
- // must precede thumbw_b__cond in search table
- // must precede thumb2_cps in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)00000000001
+ // must precede thumbw_b__cond in table
+ // must precede thumb2_cps in table
new OpcodeARM(Index.thumb2_yield, "yield.w", "111100111010xxxx10x0x00000000001"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// B6.1.1 CPS
+ // Encoding T2 ARMv6T2, ARMv7
// cps<effect>.w <iflags>{,#<mode>} Not permitted in IT block. cps #<mode> Not permitted in IT block.
- // 1 1 1 1 0 0 1 1 1 0 1 0 (1)(1)(1) (1) 1 0 (0) 0 (0) imod_0_10_9 M_0_8_8 A_0_7_7 I_0_6_6 F_0_5_5 mode_0_4_0
- // 111100111010(1)(1)(1)(1)10(0)0(0)xxxxxxxxxxx
- // must follow thumb2_dbg in search table
- // must follow thumb2_nop in search table
- // must follow thumb2_sev in search table
- // must follow thumb2_wfe in search table
- // must follow thumb2_wfi in search table
- // must follow thumb2_yield in search table
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111010(1)(1)(1)(1)10(0)0(0)xxxxxxxxxxx
+ // must follow thumb2_dbg in table
+ // must follow thumb2_nop in table
+ // must follow thumb2_sev in table
+ // must follow thumb2_wfe in table
+ // must follow thumb2_wfi in table
+ // must follow thumb2_yield in table
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_cps, "cps", "111100111010xxxx10x0xxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv7
// A8.6.41 DMB
+ // Encoding T1 ARMv7
// dmb<c> #<option>
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 1 0 1 option_0_3_0
- // 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0101xxxx
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0101xxxx
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_dmb, "dmb", "111100111011xxxx10x0xxxx0101xxxx"),
-
- // NEW - Encoding T1 ARMv7
// A8.6.42 DSB
+ // Encoding T1 ARMv7
// dsb<c> #<option>
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 1 0 0 option_0_3_0
- // 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0100xxxx
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0100xxxx
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_dsb, "dsb", "111100111011xxxx10x0xxxx0100xxxx"),
-
- // NEW - Encoding T1 ARMv7
// A8.6.49 ISB
+ // Encoding T1 ARMv7
// isb<c> #<option>
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 1 1 0 option_0_3_0
- // 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0110xxxx
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)0110xxxx
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_isb, "isb", "111100111011xxxx10x0xxxx0110xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.102 MRS
+ // Encoding T1 ARMv6T2, ARMv7
// mrs<c> <Rd>,<spec_reg>
- // 1 1 1 1 0 0 1 1 1 1 1 0 (1)(1)(1) (1) 1 0 (0) 0 Rd_0_11_8 (0)(0)(0)(0)(0)(0)(0)(0)
- // 111100111110(1)(1)(1)(1)10(0)0xxxx(0)(0)(0)(0)(0)(0)(0)(0)
- // NEW - Encoding T1 ARMv6T2, ARMv7
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111110(1)(1)(1)(1)10(0)0xxxx(0)(0)(0)(0)(0)(0)(0)(0)
// B6.1.5 MRS
+ // Encoding T1 ARMv6T2, ARMv7
// mrs<c> <Rd>,<spec_reg>
- // 1 1 1 1 0 0 1 1 1 1 1 R_1_4_4 (1)(1)(1) (1) 1 0 (0) 0 Rd_0_11_8 (0)(0)(0)(0)(0)(0)(0)(0)
- // 11110011111x(1)(1)(1)(1)10(0)0xxxx(0)(0)(0)(0)(0)(0)(0)(0)
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 11110011111x(1)(1)(1)(1)10(0)0xxxx(0)(0)(0)(0)(0)(0)(0)(0)
+ //
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_mrs, "mrs", "11110011111xxxxx10x0xxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.104 MSR (register)
+ // Encoding T1 ARMv6T2, ARMv7
// msr<c> <spec_reg>,<Rn>
- // 1 1 1 1 0 0 1 1 1 0 0 0 Rn_1_3_0 1 0 (0) 0 mask_0_11_10 0 0 (0)(0)(0)(0)(0)(0)(0)(0)
- // 111100111000xxxx10(0)0xx00(0)(0)(0)(0)(0)(0)(0)(0)
- // must precede thumb2_b__cond in search table
- // NEW - Encoding T1 ARMv6T2, ARMv7
+ // Unpredictable if (0) is 1: 111100111000xxxx10(0)0xx00(0)(0)(0)(0)(0)(0)(0)(0)
+ // must precede thumb2_b__cond in table
// B6.1.7 MSR (register)
+ // Encoding T1 ARMv6T2, ARMv7
// msr<c> <spec_reg>,<Rn>
- // 1 1 1 1 0 0 1 1 1 0 0 R_1_4_4 Rn_1_3_0 1 0 (0) 0 mask_0_11_8 (0)(0)(0)(0)(0)(0)(0)(0)
- // 11110011100xxxxx10(0)0xxxx(0)(0)(0)(0)(0)(0)(0)(0)
- // must precede thumb2_b__cond in search table
+ // Unpredictable if (0) is 1: 11110011100xxxxx10(0)0xxxx(0)(0)(0)(0)(0)(0)(0)(0)
+ //
+ // must precede thumb2_b__cond in table
new OpcodeARM(Index.thumb2_msr, "msr", "11110011100xxxxx10x0xxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.16 B
+ // Encoding T3 ARMv6T2, ARMv7
// b<c>.w <label> Not permitted in IT block.
- // 1 1 1 1 0 S_1_10_10 cond_1_9_6 imm6_1_5_0 1 0 J1_0_13_13 0 J2_0_11_11 imm11_0_10_0
- // 11110xxxxxxxxxxx10x0xxxxxxxxxxxx
- // must follow thumb2_bxj in search table
- // must follow thumb2_clrex in search table
- // must follow thumb2_cps in search table
- // must follow thumb2_dbg in search table
- // must follow thumb2_dmb in search table
- // must follow thumb2_dsb in search table
- // must follow thumb2_isb in search table
- // must follow thumb2_mrs in search table
- // must follow thumb2_msr in search table
- // must follow thumb2_nop in search table
- // must follow thumb2_sev in search table
- // must follow thumb2_wfe in search table
- // must follow thumb2_wfi in search table
- // must follow thumb2_yield in search table
+ // must follow thumb2_bxj in table
+ // must follow thumb2_clrex in table
+ // must follow thumb2_cps in table
+ // must follow thumb2_dbg in table
+ // must follow thumb2_dmb in table
+ // must follow thumb2_dsb in table
+ // must follow thumb2_isb in table
+ // must follow thumb2_mrs in table
+ // must follow thumb2_msr in table
+ // must follow thumb2_nop in table
+ // must follow thumb2_sev in table
+ // must follow thumb2_wfe in table
+ // must follow thumb2_wfi in table
+ // must follow thumb2_yield in table
new OpcodeARM(Index.thumb2_b__cond, "b", "11110xxxxxxxxxxx10x0xxxxxxxxxxxx"),
-
- // NEW - Encoding T4 ARMv6T2, ARMv7
// A8.6.16 B
+ // Encoding T4 ARMv6T2, ARMv7
// b<c>.w <label> Outside or last in IT block
- // 1 1 1 1 0 S_1_10_10 imm10_1_9_0 1 0 J1_0_13_13 1 J2_0_11_11 imm11_0_10_0
- // 11110xxxxxxxxxxx10x1xxxxxxxxxxxx
new OpcodeARM(Index.thumb2_b__uncond, "b.w", "11110xxxxxxxxxxx10x1xxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.17 BFC
+ // Encoding T1 ARMv6T2, ARMv7
// bfc<c> <Rd>,#<lsb>,#<width>
- // 1 1 1 1 0 (0) 1 1 0 1 1 0 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) msb_0_4_0
- // 11110(0)11011011110xxxxxxxxx(0)xxxxx
- // must precede thumb2_bfi in search table
+ // Unpredictable if (0) is 1: 11110(0)11011011110xxxxxxxxx(0)xxxxx
+ // must precede thumb2_bfi in table
new OpcodeARM(Index.thumb2_bfc, "bfc", "11110x11011011110xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.18 BFI
+ // Encoding T1 ARMv6T2, ARMv7
// bfi<c> <Rd>,<Rn>,#<lsb>,#<width>
- // 1 1 1 1 0 (0) 1 1 0 1 1 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) msb_0_4_0
- // 11110(0)110110xxxx0xxxxxxxxx(0)xxxxx
- // must follow thumb2_bfc in search table
+ // Unpredictable if (0) is 1: 11110(0)110110xxxx0xxxxxxxxx(0)xxxxx
+ // must follow thumb2_bfc in table
new OpcodeARM(Index.thumb2_bfi, "bfi", "11110x110110xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.154 SBFX
+ // Encoding T1 ARMv6T2, ARMv7
// sbfx<c> <Rd>,<Rn>,#<lsb>,#<width>
- // 1 1 1 1 0 (0) 1 1 0 1 0 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) widthm1
- // 11110(0)110100xxxx0xxxxxxxxx(0)xxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
+ // Unpredictable if (0) is 1: 11110(0)110100xxxx0xxxxxxxxx(0)xxxxx
// A8.6.236 UBFX
+ // Encoding T1 ARMv6T2, ARMv7
// ubfx<c> <Rd>,<Rn>,#<lsb>,#<width>
- // 1 1 1 1 0 (0) 1 1 1 1 0 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) widthm1
- // 11110(0)111100xxxx0xxxxxxxxx(0)xxxxx
+ // Unpredictable if (0) is 1: 11110(0)111100xxxx0xxxxxxxxx(0)xxxxx
//
new OpcodeARM(Index.thumb2_bfx, "bfx", "11110x11x100xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.19 BIC (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// bic{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 0 1 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00001xxxxx0xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_bic__imm, "bic", "11110x00001xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.20 BIC (register)
+ // Encoding T2 ARMv6T2, ARMv7
// bic{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 0 0 1 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101010001xxxxx(0)xxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 11101010001xxxxx(0)xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_bic__reg, "bic", "11101010001xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1; ARMv6T2, ARMv7 otherwise
// A8.6.23 BL, BLX (immediate)
+ // Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1; ARMv6T2, ARMv7 otherwise
// bl<c> <label> Outside or last in IT block
- // 1 1 1 1 0 S_1_10_10 imm10_1_9_0 1 1 J1_0_13_13 1 J2_0_11_11 imm11_0_10_0
- // 11110xxxxxxxxxxx11x1xxxxxxxxxxxx
new OpcodeARM(Index.thumb2_bl, "bl", "11110xxxxxxxxxxx11x1xxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1; ARMv6T2, ARMv7 otherwise
// A8.6.23 BL, BLX (immediate)
+ // Encoding T2 ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1; ARMv6T2, ARMv7 otherwise
// blx<c> <label> Outside or last in IT block
- // 1 1 1 1 0 S_1_10_10 imm10H_1_9_0 1 1 J1_0_13_13 0 J2_0_11_11 imm10L_0_10_1 0
- // 11110xxxxxxxxxxx11x0xxxxxxxxxxx0
new OpcodeARM(Index.thumb2_blx, "blx", "11110xxxxxxxxxxx11x0xxxxxxxxxxx0"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.31 CLZ
+ // Encoding T1 ARMv6T2, ARMv7
// clz<c> <Rd>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 1 Rm_1_3_0 1 1 1 1 Rd_0_11_8 1 0 0 0 Rm_0_3_0
- // 111110101011xxxx1111xxxx1000xxxx
new OpcodeARM(Index.thumb2_clz, "clz", "111110101011xxxx1111xxxx1000xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.35 CMP (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
// cmp<c>.w <Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 1 0 1 1 Rn_1_3_0 0 imm3_0_14_12 1 1 1 1 imm8_0_7_0
- // 11110x011011xxxx0xxx1111xxxxxxxx
- // must precede thumb2_sub__imm in search table
- // must precede thumb2_subw in search table
+ // must precede thumb2_sub__imm in table
+ // must precede thumb2_subw in table
new OpcodeARM(Index.thumb2_cmp__imm, "cmp.w", "11110x011011xxxx0xxx1111xxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.36 CMP (register)
+ // Encoding T3 ARMv6T2, ARMv7
// cmp<c>.w <Rn>, <Rm> {,<shift>}
- // 1 1 1 0 1 0 1 1 1 0 1 1 Rn_1_3_0 (0) imm3_0_14_12 1 1 1 1 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 111010111011xxxx(0)xxx1111xxxxxxxx
- // must precede thumb2_sub__reg in search table
- // must precede thumb2_subw in search table
+ // Unpredictable if (0) is 1: 111010111011xxxx(0)xxx1111xxxxxxxx
+ // must precede thumb2_sub__reg in table
+ // must precede thumb2_subw in table
new OpcodeARM(Index.thumb2_cmp__reg, "cmp.w", "111010111011xxxxxxxx1111xxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.227 TEQ (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// teq<c> <Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 1 0 0 1 Rn_1_3_0 0 imm3_0_14_12 1 1 1 1 imm8_0_7_0
- // 11110x001001xxxx0xxx1111xxxxxxxx
- // must precede thumb2_eor__imm in search table
+ // must precede thumb2_eor__imm in table
new OpcodeARM(Index.thumb2_teq__imm, "teq", "11110x001001xxxx0xxx1111xxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.44 EOR (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// eor{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 1 0 0 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00100xxxxx0xxxxxxxxxxxxxxx
- // must follow thumb2_teq__imm in search table
+ // must follow thumb2_teq__imm in table
new OpcodeARM(Index.thumb2_eor__imm, "eor", "11110x00100xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.228 TEQ (register)
+ // Encoding T1 ARMv6T2, ARMv7
// teq<c> <Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 1 0 0 1 Rn_1_3_0 (0) imm3_0_14_12 1 1 1 1 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 111010101001xxxx(0)xxx1111xxxxxxxx
- // must precede thumb2_eor__reg in search table
+ // Unpredictable if (0) is 1: 111010101001xxxx(0)xxx1111xxxxxxxx
+ // must precede thumb2_eor__reg in table
new OpcodeARM(Index.thumb2_teq__reg, "teq", "111010101001xxxxxxxx1111xxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.45 EOR (register)
+ // Encoding T2 ARMv6T2, ARMv7
// eor{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 1 0 0 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101010100xxxxx(0)xxxxxxxxxxxxxxx
- // must follow thumb2_teq__reg in search table
+ // Unpredictable if (0) is 1: 11101010100xxxxx(0)xxxxxxxxxxxxxxx
+ // must follow thumb2_teq__reg in table
new OpcodeARM(Index.thumb2_eor__reg, "eor", "11101010100xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.122 POP
+ // Encoding T2 ARMv6T2, ARMv7
// pop<c>.w <registers> <registers> contains more than one register
- // 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P_0_15_15 M_0_14_14 (0) register_list_0_12_0
- // 1110100010111101xx(0)xxxxxxxxxxxxx
- // must precede thumb2_ldm in search table
+ // Unpredictable if (0) is 1: 1110100010111101xx(0)xxxxxxxxxxxxx
+ // must precede thumb2_ldm in table
new OpcodeARM(Index.thumb2_pop__regs, "pop.w", "1110100010111101xxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.53 LDM / LDMIA / LDMFD
+ // Encoding T2 ARMv6T2, ARMv7
// ldm<c>.w <Rn>{!},<registers>
- // 1 1 1 0 1 0 0 0 1 0 W_1_5_5 1 Rn_1_3_0 P_0_15_15 M_0_14_14 (0) register_list_0_12_0
- // 1110100010x1xxxxxx(0)xxxxxxxxxxxxx
- // must follow thumb2_pop__regs in search table
+ // Unpredictable if (0) is 1: 1110100010x1xxxxxx(0)xxxxxxxxxxxxx
+ // must follow thumb2_pop__regs in table
new OpcodeARM(Index.thumb2_ldm, "ldm.w", "1110100010x1xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7; if ony 1 register, instead assemble to LDR<c><q> <Rt>,[<Rn>,#-4]{!} instruction
// A8.6.55 LDMDB / LDMEA
+ // Encoding T1 ARMv6T2, ARMv7; if ony 1 register, instead assemble to LDR<c><q> <Rt>,[<Rn>,#-4]{!} instruction
// ldmdb<c> <Rn>{!},<registers>
- // 1 1 1 0 1 0 0 1 0 0 W_1_5_5 1 Rn_1_3_0 P_0_15_15 M_0_14_14 (0) register_list_0_12_0
- // 1110100100x1xxxxxx(0)xxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 1110100100x1xxxxxx(0)xxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_ldmdb, "ldmdb", "1110100100x1xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// A8.6.117 PLD, PLDW (immediate)
+ // Encoding T1 ARMv6T2, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// pld{w}<c> [<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 0 1 0 W_1_5_5 1 Rn_1_3_0 1 1 1 1 imm12_0_11_0
- // 1111100010x1xxxx1111xxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// A8.6.117 PLD, PLDW (immediate)
+ // Encoding T2 ARMv6T2, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// pld{w}<c> [<Rn>,#-<imm8>]
- // 1 1 1 1 1 0 0 0 0 0 W_1_5_5 1 Rn_1_3_0 1 1 1 1 1 1 0 0 imm8_0_7_0
- // 1111100000x1xxxx11111100xxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.118 PLD (literal)
+ // Encoding T1 ARMv6T2, ARMv7
// pld<c> <label> pld<c> [pc,#-0] Special case
- // 1 1 1 1 1 0 0 0 U_1_7_7 0 (0) 1 1 1 1 1 1 1 1 1 imm12_0_11_0
- // 11111000x0(0)111111111xxxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
+ // Unpredictable if (0) is 1: 11111000x0(0)111111111xxxxxxxxxxxx
// A8.6.119 PLD, PLDW (register)
+ // Encoding T1 ARMv6T2, ARMv7 for PLD; ARMv7 with MP Extensions for PLDW
// pld{w}<c> [<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 0 W_1_5_5 1 Rn_1_3_0 1 1 1 1 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 1111100000x1xxxx1111000000xxxxxx
//
- // must precede thumb2_ldr in search table
- new OpcodeARM(Index.thumb2_pld, "pld", "11111000x0x1xxxx1111xxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv7
+ // must precede thumb2_ldr in table
+ new OpcodeARM(Index.thumb2_pld, "pld", "11111000x0x1xxxx1111xxxxxxxxxxxx"),
// A8.6.120 PLI (immediate, literal)
+ // Encoding T1 ARMv7
// pli<c> [<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 1 1 0 0 1 Rn_1_3_0 1 1 1 1 imm12_0_11_0
- // 111110011001xxxx1111xxxxxxxxxxxx
- // NEW - Encoding T2 ARMv7
// A8.6.120 PLI (immediate, literal)
+ // Encoding T2 ARMv7
// pli<c> [<Rn>,#-<imm8>]
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 1 1 1 1 1 1 0 0 imm8_0_7_0
- // 111110010001xxxx11111100xxxxxxxx
- // NEW - Encoding T3 ARMv7
// A8.6.120 PLI (immediate, literal)
+ // Encoding T3 ARMv7
// pli<c> <label> pli<c> [pc,#-0] Special case
- // 1 1 1 1 1 0 0 1 U_1_7_7 0 0 1 1 1 1 1 1 1 1 1 imm12_0_11_0
- // 11111001x00111111111xxxxxxxxxxxx
- // must precede thumb2_ldr__imm in search table
- // NEW - Encoding T1 ARMv7
+ // must precede thumb2_ldr__imm in table
// A8.6.121 PLI (register)
+ // Encoding T1 ARMv7
// pli<c> [<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 1 1 1 1 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110010001xxxx1111000000xxxxxx
- // must precede thumb2_ldr in search table
- new OpcodeARM(Index.thumb2_pli, "pli", "11111001x001xxxx1111xxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
- // A8.6.122 POP
- // pop<c>.w <registers> <registers> contains one register, <Rt>
- // 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt_0_15_12 1 0 1 1 0 0 0 0 0 1 0 0
- // 1111100001011101xxxx101100000100
- // must precede thumb2_ldr in search table
- new OpcodeARM(Index.thumb2_pop__reg, "pop.w", "1111100001011101xxxx101100000100"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
- // A8.6.57 LDR (immediate, Thumb)
- // ldr<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // 1 1 1 1 1 0 0 0 1 1 0 1 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110001101xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T4 ARMv6T2, ARMv7
- // A8.6.57 LDR (immediate, Thumb)
- // ldr<c> <Rt>,[<Rn>,#-<imm8>] ldr<c> <Rt>,[<Rn>],#+/-<imm8> ldr<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 0 0 1 0 1 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110000101xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.59 LDR (literal)
- // ldr<c>.w <Rt>,<label> ldr<c>.w <Rt>,[pc,#-0] Special case
- // 1 1 1 1 1 0 0 0 U_1_7_7 1 0 1 1 1 1 1 Rt_0_15_12 imm12_0_11_0
- // 11111000x1011111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.60 LDR (register)
- // ldr<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 1 0 1 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110000101xxxxxxxx000000xxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.61 LDRB (immediate, Thumb)
- // ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // 1 1 1 1 1 0 0 0 1 0 0 1 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110001001xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T3 ARMv6T2, ARMv7
- // A8.6.61 LDRB (immediate, Thumb)
- // ldrb<c> <Rt>,[<Rn>,#-<imm8>] ldrb<c> <Rt>,[<Rn>],#+/-<imm8> ldrb<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 0 0 0 0 1 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110000001xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.63 LDRB (literal)
- // ldrb<c> <Rt>,<label> ldrb<c> <Rt>,[pc,#-0] Special case
- // 1 1 1 1 1 0 0 0 U_1_7_7 0 0 1 1 1 1 1 Rt_0_15_12 imm12_0_11_0
- // 11111000x0011111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.64 LDRB (register)
- // ldrb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 0 0 1 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110000001xxxxxxxx000000xxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.65 LDRBT
- // ldrbt<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 0 0 0 0 1 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110000001xxxxxxxx1110xxxxxxxx
- // A8.6.73 LDRH (immediate, Thumb)
- // ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // 1 1 1 1 1 0 0 0 1 0 1 1 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110001011xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T3 ARMv6T2, ARMv7
- // A8.6.73 LDRH (immediate, Thumb)
- // ldrh<c> <Rt>,[<Rn>,#-<imm8>] ldrh<c> <Rt>,[<Rn>],#+/-<imm8> ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 0 0 0 1 1 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110000011xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.75 LDRH (literal)
- // ldrh<c> <Rt>,<label> ldrh<c> <Rt>,[pc,#-0] Special case
- // 1 1 1 1 1 0 0 0 U_1_7_7 0 1 1 1 1 1 1 Rt_0_15_12 imm12_0_11_0
- // 11111000x0111111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.76 LDRH (register)
- // ldrh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 0 1 1 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110000011xxxxxxxx000000xxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.77 LDRHT
- // ldrht<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 0 0 0 1 1 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110000011xxxxxxxx1110xxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.78 LDRSB (immediate)
- // ldrsb<c> <Rt>,[<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 1 1 0 0 1 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110011001xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.78 LDRSB (immediate)
- // ldrsb<c> <Rt>,[<Rn>,#-<imm8>] ldrsb<c> <Rt>,[<Rn>],#+/-<imm8> ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110010001xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.79 LDRSB (literal)
- // ldrsb<c> <Rt>,<label> ldrsb<c> <Rt>,[pc,#-0] Special case
- // 1 1 1 1 1 0 0 1 U_1_7_7 0 0 1 1 1 1 1 Rt_0_15_12 imm12_0_11_0
- // 11111001x0011111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.80 LDRSB (register)
- // ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110010001xxxxxxxx000000xxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.81 LDRSBT
- // ldrsbt<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 1 0 0 0 1 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110010001xxxxxxxx1110xxxxxxxx
- // A8.6.82 LDRSH (immediate)
- // ldrsh<c> <Rt>,[<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 1 1 0 1 1 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110011011xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.82 LDRSH (immediate)
- // ldrsh<c> <Rt>,[<Rn>,#-<imm8>] ldrsh<c> <Rt>,[<Rn>],#+/-<imm8> ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 1 0 0 1 1 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110010011xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.83 LDRSH (literal)
- // ldrsh<c> <Rt>,<label> ldrsh<c> <Rt>,[pc,#-0] Special case
- // 1 1 1 1 1 0 0 1 U_1_7_7 0 1 1 1 1 1 1 Rt_0_15_12 imm12_0_11_0
- // 11111001x0111111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.84 LDRSH (register)
- // ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 1 0 0 1 1 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110010011xxxxxxxx000000xxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.85 LDRSHT
- // ldrsht<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 1 0 0 1 1 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110010011xxxxxxxx1110xxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.86 LDRT
- // ldrt<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 0 0 1 0 1 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110000101xxxxxxxx1110xxxxxxxx
+ // must precede thumb2_ldr in table
//
- // must follow thumb2_pld in search table
- // must follow thumb2_pli in search table
- // must follow thumb2_pop_reg in search table
+ new OpcodeARM(Index.thumb2_pli, "pli", "11111001x001xxxx1111xxxxxxxxxxxx"),
+ // A8.6.122 POP
+ // Encoding T3 ARMv6T2, ARMv7
+ // pop<c>.w <registers> <registers> contains one register, <Rt>
+ // must precede thumb2_ldr in table
+ new OpcodeARM(Index.thumb2_pop__reg, "pop.w", "1111100001011101xxxx101100000100"),
+ // A8.6.57 LDR (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
+ // ldr<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // A8.6.57 LDR (immediate, Thumb)
+ // Encoding T4 ARMv6T2, ARMv7
+ // ldr<c> <Rt>,[<Rn>,#-<imm8>] ldr<c> <Rt>,[<Rn>],#+/-<imm8> ldr<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.59 LDR (literal)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldr<c>.w <Rt>,<label> ldr<c>.w <Rt>,[pc,#-0] Special case
+ // A8.6.60 LDR (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldr<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.61 LDRB (immediate, Thumb)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // A8.6.61 LDRB (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
+ // ldrb<c> <Rt>,[<Rn>,#-<imm8>] ldrb<c> <Rt>,[<Rn>],#+/-<imm8> ldrb<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.63 LDRB (literal)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrb<c> <Rt>,<label> ldrb<c> <Rt>,[pc,#-0] Special case
+ // A8.6.64 LDRB (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.65 LDRBT
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrbt<c> <Rt>,[<Rn>,#<imm8>]
+ // A8.6.73 LDRH (immediate, Thumb)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]
+ // A8.6.73 LDRH (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
+ // ldrh<c> <Rt>,[<Rn>,#-<imm8>] ldrh<c> <Rt>,[<Rn>],#+/-<imm8> ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.75 LDRH (literal)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrh<c> <Rt>,<label> ldrh<c> <Rt>,[pc,#-0] Special case
+ // A8.6.76 LDRH (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.77 LDRHT
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrht<c> <Rt>,[<Rn>,#<imm8>]
+ // A8.6.78 LDRSB (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrsb<c> <Rt>,[<Rn>,#<imm12>]
+ // A8.6.78 LDRSB (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrsb<c> <Rt>,[<Rn>,#-<imm8>] ldrsb<c> <Rt>,[<Rn>],#+/-<imm8> ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.79 LDRSB (literal)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrsb<c> <Rt>,<label> ldrsb<c> <Rt>,[pc,#-0] Special case
+ // A8.6.80 LDRSB (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.81 LDRSBT
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrsbt<c> <Rt>,[<Rn>,#<imm8>]
+ // A8.6.82 LDRSH (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrsh<c> <Rt>,[<Rn>,#<imm12>]
+ // A8.6.82 LDRSH (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrsh<c> <Rt>,[<Rn>,#-<imm8>] ldrsh<c> <Rt>,[<Rn>],#+/-<imm8> ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]!
+ // A8.6.83 LDRSH (literal)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrsh<c> <Rt>,<label> ldrsh<c> <Rt>,[pc,#-0] Special case
+ // A8.6.84 LDRSH (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
+ // A8.6.85 LDRSHT
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrsht<c> <Rt>,[<Rn>,#<imm8>]
+ // A8.6.86 LDRT
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrt<c> <Rt>,[<Rn>,#<imm8>]
+ //
+ // must follow thumb2_pld in table
+ // must follow thumb2_pli in table
+ // must follow thumb2_pop_reg in table
// 1 1 1 1 1 0 0 s_1_8_8 u_1_7_7 op_1_6_6 bh_1_5_5 1 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
new OpcodeARM(Index.thumb2_ldr, "ldr", "1111100xxxx1xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.67 LDRD (literal)
+ // Encoding T1 ARMv6T2, ARMv7
// ldrd<c> <Rt>,<Rt2>,<label> ldrd<c> <Rt>,<Rt2>,[pc,#-0] Special case
- // 1 1 1 0 1 0 0 P_1_8_8 U_1_7_7 1 (0) 1 1 1 1 1 Rt_0_15_12 Rt2_0_11_8 imm8_0_7_0
- // 1110100xx1(0)11111xxxxxxxxxxxxxxxx
- // must precede thumb2_ldrex in search table
- // must precede thumb2_ldrd__imm in search table
+ // Unpredictable if (0) is 1: 1110100xx1(0)11111xxxxxxxxxxxxxxxx
+ // must precede thumb2_ldrex in table
+ // must precede thumb2_ldrd__imm in table
new OpcodeARM(Index.thumb2_ldrd__lit, "ldrd", "1110100xx1x11111xxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.69 LDREX
+ // Encoding T1 ARMv6T2, ARMv7
// ldrex<c> <Rt>,[<Rn>{,#<imm>}]
- // 1 1 1 0 1 0 0 0 0 1 0 1 Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) imm8_0_7_0
- // 111010000101xxxxxxxx(1)(1)(1)(1)xxxxxxxx
- // must follow thumb2_ldrd__lit in search table
- // must encode (1)(1)(1)(1) and precede thumb2_ldrd__imm in search table
+ // Unpredictable if (1) is 0: 111010000101xxxxxxxx(1)(1)(1)(1)xxxxxxxx
+ // must follow thumb2_ldrd__lit in table
+ // must precede thumb2_ldrd__imm in table and must encode (1)(1)(1)(1)
new OpcodeARM(Index.thumb2_ldrex, "ldrex", "111010000101xxxxxxxx1111xxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.226 TBB, TBH
+ // Encoding T1 ARMv6T2, ARMv7
// tbb<c> [<Rn>,<Rm>] Outside or last in IT block tbh<c> [<Rn>,<Rm>,LSL #1] Outside or last in IT block
- // 1 1 1 0 1 0 0 0 1 1 0 1 Rn_1_3_0 (1) (1)(1)(1)(0)(0)(0)(0) 0 0 0 H_0_4_4 Rm_0_3_0
- // 111010001101xxxx(1)(1)(1)(1)(0)(0)(0)(0)000xxxxx
- // must precede thumb2_ldrexx in search table
+ // Unpredictable if (1) is 0 or (0) is 1: 111010001101xxxx(1)(1)(1)(1)(0)(0)(0)(0)000xxxxx
+ // must precede thumb2_ldrexx in table
new OpcodeARM(Index.thumb2_tb, "tb", "111010001101xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv7
// A8.6.70 LDREXB
+ // Encoding T1 ARMv7
// ldrexb<c> <Rt>, [<Rn>]
- // 1 1 1 0 1 0 0 0 1 1 0 1 Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) 0 1 0 0 (1)(1)(1)(1)
- // 111010001101xxxxxxxx(1)(1)(1)(1)0100(1)(1)(1)(1)
- // NEW - Encoding T1 ARMv7
+ // Unpredictable if (1) is 0: 111010001101xxxxxxxx(1)(1)(1)(1)0100(1)(1)(1)(1)
// A8.6.71 LDREXD
+ // Encoding T1 ARMv7
// ldrexd<c> <Rt>,<Rt2>,[<Rn>]
- // 1 1 1 0 1 0 0 0 1 1 0 1 Rn_1_3_0 Rt_0_15_12 Rt2_0_11_8 0 1 1 1 (1)(1)(1)(1)
- // 111010001101xxxxxxxxxxxx0111(1)(1)(1)(1)
- // NEW - Encoding T1 ARMv7
+ // Unpredictable if (1) is 0: 111010001101xxxxxxxxxxxx0111(1)(1)(1)(1)
// A8.6.72 LDREXH
+ // Encoding T1 ARMv7
// ldrexh<c> <Rt>, [<Rn>]
- // 1 1 1 0 1 0 0 0 1 1 0 1 Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) 0 1 0 1 (1)(1)(1)(1)
- // 111010001101xxxxxxxx(1)(1)(1)(1)0101(1)(1)(1)(1)
- // must follow thumb2_ldrd__lit in search table
- // must follow thumb2_tb in search table
- // must encode Rt2/(1)(1)(1)(1) and precede thumb2_ldrd__imm in search table
- new OpcodeARM(Index.thumb2_ldrexx, "ldrex", "111010001101xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.66 LDRD (immediate)
- // ldrd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}] ldrd<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm> ldrd<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
- // 1 1 1 0 1 0 0 P_1_8_8 U_1_7_7 1 W_1_5_5 1 Rn_1_3_0 Rt_0_15_12 Rt2_0_11_8 imm8_0_7_0
- // 1110100xx1x1xxxxxxxxxxxxxxxxxxxx
- // must follow thumb2_ldrd__lit in search table
- // must follow thumb2_ldrex in search table
- new OpcodeARM(Index.thumb2_ldrd__imm, "ldrd", "1110100xx1x1xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
- // A8.6.97 MOV (register)
- // mov{s}<c>.w <Rd>,<Rm>
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 1 1 1 1 (0) 0 0 0 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 11101010010x1111(0)000xxxx0000xxxx
- // must precede thumb2_lsl__imm in search table
- // must precede thumb2_orr__reg in search table
- new OpcodeARM(Index.thumb2_mov__reg, "mov", "11101010010x1111x000xxxx0000xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.88 LSL (immediate)
- // lsl{s}<c>.w <Rd>,<Rm>,#<imm5>
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 1 1 1 1 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 0 0 Rm_0_3_0
- // 11101010010x1111(0)xxxxxxxxx00xxxx
- // must follow thumb2_mov_reg in search table
- new OpcodeARM(Index.thumb2_lsl__imm, "lsl", "11101010010x1111xxxxxxxxxx00xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.89 LSL (register)
- // lsl{s}<c>.w <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 0 0 0 S_1_4_4 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 11111010000xxxxx1111xxxx0000xxxx
- new OpcodeARM(Index.thumb2_lsl__reg, "lsl", "11111010000xxxxx1111xxxx0000xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.90 LSR (immediate)
- // lsr{s}<c>.w <Rd>,<Rm>,#<imm>
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 1 1 1 1 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 0 1 Rm_0_3_0
- // 11101010010x1111(0)xxxxxxxxx01xxxx
- new OpcodeARM(Index.thumb2_lsr__imm, "lsr", "11101010010x1111xxxxxxxxxx01xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.91 LSR (register)
- // lsr{s}<c>.w <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 0 0 1 S_1_4_4 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 11111010001xxxxx1111xxxx0000xxxx
- new OpcodeARM(Index.thumb2_lsr__reg, "lsr", "11111010001xxxxx1111xxxx0000xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.105 MUL
- // mul<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110110000xxxx1111xxxx0000xxxx
- // must precede thumb2_ml in search table
- new OpcodeARM(Index.thumb2_mul, "mul", "111110110000xxxx1111xxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.94 MLA
- // mla<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 0 0 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110110000xxxxxxxxxxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.95 MLS
- // mls<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 0 0 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110110000xxxxxxxxxxxx0001xxxx
+ // Unpredictable if (1) is 0: 111010001101xxxxxxxx(1)(1)(1)(1)0101(1)(1)(1)(1)
//
- // must follow thumb2_mul in search table
+ // must follow thumb2_ldrd__lit in table
+ // must follow thumb2_tb in table
+ // must precede thumb2_ldrd__imm in table and encode Rt2/(1)(1)(1)(1)
+ new OpcodeARM(Index.thumb2_ldrexx, "ldrex", "111010001101xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.66 LDRD (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
+ // ldrd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}] ldrd<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm> ldrd<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
+ // must follow thumb2_ldrd__lit in table
+ // must follow thumb2_ldrex in table
+ new OpcodeARM(Index.thumb2_ldrd__imm, "ldrd", "1110100xx1x1xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.97 MOV (register)
+ // Encoding T3 ARMv6T2, ARMv7
+ // mov{s}<c>.w <Rd>,<Rm>
+ // Unpredictable if (0) is 1: 11101010010x1111(0)000xxxx0000xxxx
+ // must precede thumb2_lsl__imm in table
+ // must precede thumb2_orr__reg in table
+ new OpcodeARM(Index.thumb2_mov__reg, "mov", "11101010010x1111x000xxxx0000xxxx"),
+ // A8.6.88 LSL (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
+ // lsl{s}<c>.w <Rd>,<Rm>,#<imm5>
+ // Unpredictable if (0) is 1: 11101010010x1111(0)xxxxxxxxx00xxxx
+ // must follow thumb2_mov_reg in table
+ new OpcodeARM(Index.thumb2_lsl__imm, "lsl", "11101010010x1111xxxxxxxxxx00xxxx"),
+ // A8.6.89 LSL (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // lsl{s}<c>.w <Rd>,<Rn>,<Rm>
+ new OpcodeARM(Index.thumb2_lsl__reg, "lsl", "11111010000xxxxx1111xxxx0000xxxx"),
+ // A8.6.90 LSR (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
+ // lsr{s}<c>.w <Rd>,<Rm>,#<imm>
+ // Unpredictable if (0) is 1: 11101010010x1111(0)xxxxxxxxx01xxxx
+ new OpcodeARM(Index.thumb2_lsr__imm, "lsr", "11101010010x1111xxxxxxxxxx01xxxx"),
+ // A8.6.91 LSR (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // lsr{s}<c>.w <Rd>,<Rn>,<Rm>
+ new OpcodeARM(Index.thumb2_lsr__reg, "lsr", "11111010001xxxxx1111xxxx0000xxxx"),
+ // A8.6.105 MUL
+ // Encoding T2 ARMv6T2, ARMv7
+ // mul<c> <Rd>,<Rn>,<Rm>
+ // must precede thumb2_ml in table
+ new OpcodeARM(Index.thumb2_mul, "mul", "111110110000xxxx1111xxxx0000xxxx"),
+ // A8.6.94 MLA
+ // Encoding T1 ARMv6T2, ARMv7
+ // mla<c> <Rd>,<Rn>,<Rm>,<Ra>
+ // A8.6.95 MLS
+ // Encoding T1 ARMv6T2, ARMv7
+ // mls<c> <Rd>,<Rn>,<Rm>,<Ra>
+ //
+ // must follow thumb2_mul in table
new OpcodeARM(Index.thumb2_ml, "ml", "111110110000xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.96 MOV (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
// mov{s}<c>.w <Rd>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 1 0 S_1_4_4 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00010x11110xxxxxxxxxxxxxxx
- // must precede thumb2_orr__imm in search table
+ // must precede thumb2_orr__imm in table
new OpcodeARM(Index.thumb2_mov__imm, "mov", "11110x00010x11110xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.96 MOV (immediate)
+ // Encoding T3 ARMv6T2, ARMv7
// movw<c> <Rd>,#<imm16>
- // 1 1 1 1 0 i_1_10_10 1 0 0 1 0 0 imm4_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x100100xxxx0xxxxxxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.99 MOVT
+ // Encoding T1 ARMv6T2, ARMv7
// movt<c> <Rd>,#<imm16>
- // 1 1 1 1 0 i_1_10_10 1 0 1 1 0 0 imm4_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x101100xxxx0xxxxxxxxxxxxxxx
+ //
new OpcodeARM(Index.thumb2_movx, "mov", "11110x10x100xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.106 MVN (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// mvn{s}<c> <Rd>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 1 1 S_1_4_4 1 1 1 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00011x11110xxxxxxxxxxxxxxx
- // must precede thumb2_orn__imm in search table
+ // must precede thumb2_orn__imm in table
new OpcodeARM(Index.thumb2_mvn__imm, "mvn", "11110x00011x11110xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.107 MVN (register)
+ // Encoding T2 ARMv6T2, ARMv7
// mvn{s}<c>.w <Rd>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 0 1 1 S_1_4_4 1 1 1 1 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101010011x1111(0)xxxxxxxxxxxxxxx
- // must precede thumb2_orn__reg in search table
+ // Unpredictable if (0) is 1: 11101010011x1111(0)xxxxxxxxxxxxxxx
+ // must precede thumb2_orn__reg in table
new OpcodeARM(Index.thumb2_mvn__reg, "mvn", "11101010011x1111xxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.111 ORN (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// orn{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 1 1 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00011xxxxx0xxxxxxxxxxxxxxx
- // must follow thumb2_mvn__imm in search table
+ // must follow thumb2_mvn__imm in table
new OpcodeARM(Index.thumb2_orn__imm, "orn", "11110x00011xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.112 ORN (register)
+ // Encoding T1 ARMv6T2, ARMv7
// orn{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 0 1 1 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101010011xxxxx(0)xxxxxxxxxxxxxxx
- // must follow thumb2_mvn__reg in search table
+ // Unpredictable if (0) is 1: 11101010011xxxxx(0)xxxxxxxxxxxxxxx
+ // must follow thumb2_mvn__reg in table
new OpcodeARM(Index.thumb2_orn__reg, "orn", "11101010011xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.113 ORR (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// orr{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 0 0 1 0 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x00010xxxxx0xxxxxxxxxxxxxxx
- // must follow thumb2_mov__imm in search table
+ // must follow thumb2_mov__imm in table
new OpcodeARM(Index.thumb2_orr__imm, "orr", "11110x00010xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.141 RRX
+ // Encoding T1 ARMv6T2, ARMv7
// rrx{s}<c> <Rd>,<Rm>
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 1 1 1 1 (0) 0 0 0 Rd_0_11_8 0 0 1 1 Rm_0_3_0
- // 11101010010x1111(0)000xxxx0011xxxx
- // must precede thumb2_ror__imm in search table
- // must precede thumb2_orr__reg in search table
+ // Unpredictable if (0) is 1: 11101010010x1111(0)000xxxx0011xxxx
+ // must precede thumb2_ror__imm in table
+ // must precede thumb2_orr__reg in table
new OpcodeARM(Index.thumb2_rrx, "rrx", "11101010010x1111x000xxxx0011xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.139 ROR (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// ror{s}<c> <Rd>,<Rm>,#<imm>
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 1 1 1 1 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 1 1 Rm_0_3_0
- // 11101010010x1111(0)xxxxxxxxx11xxxx
- // must precede thumb2_orr__reg in search table
- // must follow thumb2_rrx in search table
+ // Unpredictable if (0) is 1: 11101010010x1111(0)xxxxxxxxx11xxxx
+ // must precede thumb2_orr__reg in table
+ // must follow thumb2_rrx in table
new OpcodeARM(Index.thumb2_ror__imm, "ror", "11101010010x1111xxxxxxxxxx11xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.114 ORR (register)
+ // Encoding T2 ARMv6T2, ARMv7
// orr{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 0 0 1 0 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101010010xxxxx(0)xxxxxxxxxxxxxxx
- // must follow thumb2_mov__reg in search table
- // must follow thumb2_ror__imm in search table
- // must follow thumb2_rrx in search table
+ // Unpredictable if (0) is 1: 11101010010xxxxx(0)xxxxxxxxxxxxxxx
+ // must follow thumb2_mov__reg in table
+ // must follow thumb2_ror__imm in table
+ // must follow thumb2_rrx in table
new OpcodeARM(Index.thumb2_orr__reg, "orr", "11101010010xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.116 PKH
+ // Encoding T1 ARMv6T2, ARMv7
// pkhbt<c> <Rd>,<Rn>,<Rm>{,lsl #<imm>} pkhtb<c> <Rd>,<Rn>,<Rm>{,asr #<imm>}
- // 1 1 1 0 1 0 1 0 1 1 0 0 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 tb_0_5_5 0 Rm_0_3_0
- // 111010101100xxxx(0)xxxxxxxxxx0xxxx
+ // Unpredictable if (0) is 1: 111010101100xxxx(0)xxxxxxxxxx0xxxx
new OpcodeARM(Index.thumb2_pkh, "pkh", "111010101100xxxxxxxxxxxxxxx0xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.123 PUSH
+ // Encoding T2 ARMv6T2, ARMv7
// push<c>.w <registers> <registers> contains more than one register
- // 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 (0) M_0_14_14 (0) register_list_0_12_0
- // 1110100010101101(0)x(0)xxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 1110100010101101(0)x(0)xxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_push__regs, "push.w", "1110100010101101xxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.123 PUSH
+ // Encoding T3 ARMv6T2, ARMv7
// push<c>.w <registers> <registers> contains one register, <Rt>
- // 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt_0_15_12 1 1 0 1 0 0 0 0 0 1 0 0
- // 1111100001001101xxxx110100000100
- // must precede thumb2_str in search table
+ // must precede thumb2_str in table
new OpcodeARM(Index.thumb2_push__reg, "push.w", "1111100001001101xxxx110100000100"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.124 QADD
+ // Encoding T1 ARMv6T2, ARMv7
// qadd<c> <Rd>,<Rm>,<Rn>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 0 0 0 Rm_0_3_0
- // 111110101000xxxx1111xxxx1000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.128 QDADD
+ // Encoding T1 ARMv6T2, ARMv7
// qdadd<c> <Rd>,<Rm>,<Rn>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 0 0 1 Rm_0_3_0
- // 111110101000xxxx1111xxxx1001xxxx
//
new OpcodeARM(Index.thumb2_qadd, "add", "111110101000xxxx1111xxxx100xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.129 QDSUB
+ // Encoding T1 ARMv6T2, ARMv7
// qdsub<c> <Rd>,<Rm>,<Rn>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 0 1 1 Rm_0_3_0
- // 111110101000xxxx1111xxxx1011xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.131 QSUB
+ // Encoding T1 ARMv6T2, ARMv7
// qsub<c> <Rd>,<Rm>,<Rn>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 0 1 0 Rm_0_3_0
- // 111110101000xxxx1111xxxx1010xxxx
//
new OpcodeARM(Index.thumb2_qsub, "sub", "111110101000xxxx1111xxxx101xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.125 QADD16
+ // Encoding T1 ARMv6T2, ARMv7
// qadd16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110101001xxxx1111xxxx0001xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.126 QADD8
+ // Encoding T1 ARMv6T2, ARMv7
// qadd8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110101000xxxx1111xxxx0001xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.127 QASX
+ // Encoding T1 ARMv6T2, ARMv7
// qasx<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110101010xxxx1111xxxx0001xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.130 QSAX
+ // Encoding T1 ARMv6T2, ARMv7
// qsax<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110101110xxxx1111xxxx0001xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.132 QSUB16
+ // Encoding T1 ARMv6T2, ARMv7
// qsub16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110101101xxxx1111xxxx0001xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.133 QSUB8
+ // Encoding T1 ARMv6T2, ARMv7
// qsub8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 1 Rm_0_3_0
- // 111110101100xxxx1111xxxx0001xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.148 SADD16
+ // Encoding T1 ARMv6T2, ARMv7
// sadd16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110101001xxxx1111xxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.149 SADD8
+ // Encoding T1 ARMv6T2, ARMv7
// sadd8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110101000xxxx1111xxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.150 SASX
+ // Encoding T1 ARMv6T2, ARMv7
// sasx<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110101010xxxx1111xxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.159 SHADD16
+ // Encoding T1 ARMv6T2, ARMv7
// shadd16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 1 0 Rm_0_3_0
- // 111110101001xxxx1111xxxx0010xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.160 SHADD8
+ // Encoding T1 ARMv6T2, ARMv7
// shadd8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 1 0 Rm_0_3_0
- // 111110101000xxxx1111xxxx0010xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.161 SHASX
+ // Encoding T1 ARMv6T2, ARMv7
// shasx<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 1 0 Rm_0_3_0
- // 111110101010xxxx1111xxxx0010xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.162 SHSAX
+ // Encoding T1 ARMv6T2, ARMv7
// shsax<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 1 0 Rm_0_3_0
- // 111110101110xxxx1111xxxx0010xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.163 SHSUB16
+ // Encoding T1 ARMv6T2, ARMv7
// shsub16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 1 0 Rm_0_3_0
- // 111110101101xxxx1111xxxx0010xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.164 SHSUB8
+ // Encoding T1 ARMv6T2, ARMv7
// shsub8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 1 0 Rm_0_3_0
- // 111110101100xxxx1111xxxx0010xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.185 SSAX
+ // Encoding T1 ARMv6T2, ARMv7
// ssax<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110101110xxxx1111xxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.186 SSUB16
+ // Encoding T1 ARMv6T2, ARMv7
// ssub16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110101101xxxx1111xxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.187 SSUB8
+ // Encoding T1 ARMv6T2, ARMv7
// ssub8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110101100xxxx1111xxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.233 UADD16
+ // Encoding T1 ARMv6T2, ARMv7
// uadd16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 0 Rm_0_3_0
- // 111110101001xxxx1111xxxx0100xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.234 UADD8
+ // Encoding T1 ARMv6T2, ARMv7
// uadd8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 0 Rm_0_3_0
- // 111110101000xxxx1111xxxx0100xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.235 UASX
+ // Encoding T1 ARMv6T2, ARMv7
// uasx<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 0 Rm_0_3_0
- // 111110101010xxxx1111xxxx0100xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.238 UHADD16
+ // Encoding T1 ARMv6T2, ARMv7
// uhadd16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110101001xxxx1111xxxx0110xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.239 UHADD8
+ // Encoding T1 ARMv6T2, ARMv7
// uhadd8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110101000xxxx1111xxxx0110xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.240 UHASX
+ // Encoding T1 ARMv6T2, ARMv7
// uhasx<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110101010xxxx1111xxxx0110xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.241 UHSAX
+ // Encoding T1 ARMv6T2, ARMv7
// uhsax<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110101110xxxx1111xxxx0110xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.242 UHSUB16
+ // Encoding T1 ARMv6T2, ARMv7
// uhsub16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110101101xxxx1111xxxx0110xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.243 UHSUB8
+ // Encoding T1 ARMv6T2, ARMv7
// uhsub8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110101100xxxx1111xxxx0110xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.247 UQADD16
+ // Encoding T1 ARMv6T2, ARMv7
// uqadd16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 1 Rm_0_3_0
- // 111110101001xxxx1111xxxx0101xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.248 UQADD8
+ // Encoding T1 ARMv6T2, ARMv7
// uqadd8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 1 Rm_0_3_0
- // 111110101000xxxx1111xxxx0101xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.249 UQASX
+ // Encoding T1 ARMv6T2, ARMv7
// uqasx<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 1 Rm_0_3_0
- // 111110101010xxxx1111xxxx0101xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.250 UQSAX
+ // Encoding T1 ARMv6T2, ARMv7
// uqsax<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 1 Rm_0_3_0
- // 111110101110xxxx1111xxxx0101xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.251 UQSUB16
+ // Encoding T1 ARMv6T2, ARMv7
// uqsub16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 1 Rm_0_3_0
- // 111110101101xxxx1111xxxx0101xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.252 UQSUB8
+ // Encoding T1 ARMv6T2, ARMv7
// uqsub8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 1 Rm_0_3_0
- // 111110101100xxxx1111xxxx0101xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.257 USAX
+ // Encoding T1 ARMv6T2, ARMv7
// usax<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 0 Rm_0_3_0
- // 111110101110xxxx1111xxxx0100xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.258 USUB16
+ // Encoding T1 ARMv6T2, ARMv7
// usub16<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 0 Rm_0_3_0
- // 111110101101xxxx1111xxxx0100xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.259 USUB8
+ // Encoding T1 ARMv6T2, ARMv7
// usub8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 1 0 0 Rm_0_3_0
- // 111110101100xxxx1111xxxx0100xxxx
//
// {s|u|}{h|q|}{asx|sax|{add|sub}{8|16}<c> <Rd>,<Rn>,<Rm>
// 1 1 1 1 1 0 1 0 1 op_1_6_4 Rn_1_3_0 1 1 1 1 Rd_0_11_8 u_0_6_0 h_0_5_0 q_0_4_0 Rm_0_3_0
new OpcodeARM(Index.thumb2__r_dnm_math, null, "111110101xxxxxxx1111xxxx0xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.134 RBIT
+ // Encoding T1 ARMv6T2, ARMv7
// rbit<c> <Rd>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rm_1_3_0 1 1 1 1 Rd_0_11_8 1 0 1 0 Rm_0_3_0
- // 111110101001xxxx1111xxxx1010xxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.135 REV
+ // Encoding T2 ARMv6T2, ARMv7
// rev<c>.w <Rd>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rm_1_3_0 1 1 1 1 Rd_0_11_8 1 0 0 0 Rm_0_3_0
- // 111110101001xxxx1111xxxx1000xxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.136 REV16
+ // Encoding T2 ARMv6T2, ARMv7
// rev16<c>.w <Rd>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rm_1_3_0 1 1 1 1 Rd_0_11_8 1 0 0 1 Rm_0_3_0
- // 111110101001xxxx1111xxxx1001xxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.137 REVSH
+ // Encoding T2 ARMv6T2, ARMv7
// revsh<c>.w <Rd>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 0 1 Rm_1_3_0 1 1 1 1 Rd_0_11_8 1 0 1 1 Rm_0_3_0
- // 111110101001xxxx1111xxxx1011xxxx
//
new OpcodeARM(Index.thumb2_reverse, "r", "111110101001xxxx1111xxxx10xxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.140 ROR (register)
+ // Encoding T2 ARMv6T2, ARMv7
// ror{s}<c>.w <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 0 1 1 S_1_4_4 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 11111010011xxxxx1111xxxx0000xxxx
new OpcodeARM(Index.thumb2_ror__reg, "ror", "11111010011xxxxx1111xxxx0000xxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.142 RSB (immediate)
+ // Encoding T2 ARMv6T2, ARMv7
// rsb{s}<c>.w <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 1 1 0 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01110xxxxx0xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_rsb__imm, "rsb", "11110x01110xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.143 RSB (register)
+ // Encoding T1 ARMv6T2, ARMv7
// rsb{s}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 1 1 0 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011110xxxxx(0)xxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 11101011110xxxxx(0)xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_rsb__reg, "rsb", "11101011110xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.151 SBC (immediate)
+ // Encoding T1 ARMv6T2, ARMv7
// sbc{s}<c> <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 0 1 1 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01011xxxxx0xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_sbc__imm, "sbc", "11110x01011xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.152 SBC (register)
+ // Encoding T2 ARMv6T2, ARMv7
// sbc{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 0 1 1 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011011xxxxx(0)xxxxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 11101011011xxxxx(0)xxxxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_sbc__reg, "sbc", "11101011011xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv7-R
// A8.6.155 SDIV
+ // Encoding T1 ARMv7-R
// sdiv<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 0 0 1 Rn_1_3_0 (1) (1)(1)(1) Rd_0_11_8 1 1 1 1 Rm_0_3_0
- // 111110111001xxxx(1)(1)(1)(1)xxxx1111xxxx
+ // Unpredictable if (1) is 0: 111110111001xxxx(1)(1)(1)(1)xxxx1111xxxx
new OpcodeARM(Index.thumb2_sdiv, "sdiv", "111110111001xxxxxxxxxxxx1111xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.156 SEL
+ // Encoding T1 ARMv6T2, ARMv7
// sel<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 0 1 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 0 0 0 Rm_0_3_0
- // 111110101010xxxx1111xxxx1000xxxx
new OpcodeARM(Index.thumb2_sel, "sel", "111110101010xxxx1111xxxx1000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.178 SMULBB, SMULBT, SMULTB, SMULTT
+ // Encoding T1 ARMv6T2, ARMv7
// smul<x><y><c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 N_0_5_5 M_0_4_4 Rm_0_3_0
- // 111110110001xxxx1111xxxx00xxxxxx
- // must preced thumb2_smla in search table
+ // must precede thumb2_smla in table
new OpcodeARM(Index.thumb2_smul, "smul", "111110110001xxxx1111xxxx00xxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.166 SMLABB, SMLABT, SMLATB, SMLATT
+ // Encoding T1 ARMv6T2, ARMv7
// smla<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 0 1 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 N_0_5_5 M_0_4_4 Rm_0_3_0
- // 111110110001xxxxxxxxxxxx00xxxxxx
- // must follow thumb2_smul in search table
+ // must follow thumb2_smul in table
new OpcodeARM(Index.thumb2_smla, "smla", "111110110001xxxxxxxxxxxx00xxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.177 SMUAD
+ // Encoding T1 ARMv6T2, ARMv7
// smuad{x}<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
- // 111110110010xxxx1111xxxx000xxxxx
- // must preced thumb2_smlad in search table
+ // must precede thumb2_smlad in table
new OpcodeARM(Index.thumb2_smuad, "smuad", "111110110010xxxx1111xxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.167 SMLAD
+ // Encoding T1 ARMv6T2, ARMv7
// smlad{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 1 0 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
- // 111110110010xxxxxxxxxxxx000xxxxx
- // must follow thumb2_smuad in search table
+ // must follow thumb2_smuad in table
new OpcodeARM(Index.thumb2_smlad, "smlad", "111110110010xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.168 SMLAL
+ // Encoding T1 ARMv6T2, ARMv7
// smlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 0 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110111100xxxxxxxxxxxx0000xxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.169 SMLALBB, SMLALBT, SMLALTB, SMLALTT
+ // Encoding T1 ARMv6T2, ARMv7
// smlal<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 0 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 1 0 N_0_5_5 M_0_4_4 Rm_0_3_0
- // 111110111100xxxxxxxxxxxx10xxxxxx
//
new OpcodeARM(Index.thumb2_smlal, "smlal", "111110111100xxxxxxxxxxxxx0xxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.170 SMLALD
+ // Encoding T1 ARMv6T2, ARMv7
// smlald{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 0 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 1 1 0 M_0_4_4 Rm_0_3_0
- // 111110111100xxxxxxxxxxxx110xxxxx
new OpcodeARM(Index.thumb2_smlald, "smlald", "111110111100xxxxxxxxxxxx110xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.180 SMULWB, SMULWT
+ // Encoding T1 ARMv6T2, ARMv7
// smulw<y><c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 0 1 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
- // 111110110011xxxx1111xxxx000xxxxx
- // must precede thumb2_smlaw in search table
+ // must precede thumb2_smlaw in table
new OpcodeARM(Index.thumb2_smulw, "smulw", "111110110011xxxx1111xxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.171 SMLAWB, SMLAWT
+ // Encoding T1 ARMv6T2, ARMv7
// smlaw<y><c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 0 1 1 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
- // 111110110011xxxxxxxxxxxx000xxxxx
- // must follow thumb2_smulw in search table
+ // must follow thumb2_smulw in table
new OpcodeARM(Index.thumb2_smlaw, "smlaw", "111110110011xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.181 SMUSD
+ // Encoding T1 ARMv6T2, ARMv7
// smusd{x}<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
- // 111110110100xxxx1111xxxx000xxxxx
new OpcodeARM(Index.thumb2_smusd, "smusd", "111110110100xxxx1111xxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.172 SMLSD
+ // Encoding T1 ARMv6T2, ARMv7
// smlsd{x}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 1 0 0 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 M_0_4_4 Rm_0_3_0
- // 111110110100xxxxxxxxxxxx000xxxxx
- // must follow thumb2_smusd in search table
+ // must follow thumb2_smusd in table
new OpcodeARM(Index.thumb2_smlsd, "smlsd", "111110110100xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.173 SMLSLD
+ // Encoding T1 ARMv6T2, ARMv7
// smlsld{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 0 1 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 1 1 0 M_0_4_4 Rm_0_3_0
- // 111110111101xxxxxxxxxxxx110xxxxx
new OpcodeARM(Index.thumb2_smlsld, "smlsld", "111110111101xxxxxxxxxxxx110xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.176 SMMUL
+ // Encoding T1 ARMv6T2, ARMv7
// smmul{r}<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 R_0_4_4 Rm_0_3_0
- // 111110110101xxxx1111xxxx000xxxxx
- // must precede thumb2_smmla in search table
+ // must precede thumb2_smmla in table
new OpcodeARM(Index.thumb2_smmul, "smmul", "111110110101xxxx1111xxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.174 SMMLA
+ // Encoding T1 ARMv6T2, ARMv7
// smmla{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 1 0 1 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 R_0_4_4 Rm_0_3_0
- // 111110110101xxxxxxxxxxxx000xxxxx
- // must follow thumb2_smmul in search table
+ // must follow thumb2_smmul in table
new OpcodeARM(Index.thumb2_smmla, "smmla", "111110110101xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.175 SMMLS
+ // Encoding T1 ARMv6T2, ARMv7
// smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 1 1 0 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 R_0_4_4 Rm_0_3_0
- // 111110110110xxxxxxxxxxxx000xxxxx
new OpcodeARM(Index.thumb2_smmls, "smmls", "111110110110xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.179 SMULL
+ // Encoding T1 ARMv6T2, ARMv7
// smull<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 0 0 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110111000xxxxxxxxxxxx0000xxxx
new OpcodeARM(Index.thumb2_smull, "smull", "111110111000xxxxxxxxxxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.184 SSAT16
+ // Encoding T1 ARMv6T2, ARMv7
// ssat16<c> <Rd>,#<imm>,<Rn>
- // 1 1 1 1 0 (0) 1 1 0 0 1 0 Rn_1_3_0 0 0 0 0 Rd_0_11_8 0 0 (0)(0) sat_imm_0_3_0
- // 11110(0)110010xxxx0000xxxx00(0)(0)xxxx
- // must precede thumb2_ssat in search table
+ // Unpredictable if (0) is 1: 11110(0)110010xxxx0000xxxx00(0)(0)xxxx
+ // must precede thumb2_ssat in table
new OpcodeARM(Index.thumb2_ssat16, "ssat16", "11110x110010xxxx0000xxxx00xxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.183 SSAT
+ // Encoding T1 ARMv6T2, ARMv7
// ssat<c> <Rd>,#<imm>,<Rn>{,<shift>}
- // 1 1 1 1 0 (0) 1 1 0 0 sh_1_5_5 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) sat_imm_0_4_0
- // 11110(0)1100x0xxxx0xxxxxxxxx(0)xxxxx
- // must follow thumb2_ssat16 in search table
- new OpcodeARM(Index.thumb2_ssat, "ssat", "11110x1100x0xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
+ // Unpredictable if (0) is 1: 11110(0)1100x0xxxx0xxxxxxxxx(0)xxxxx
+ // must follow thumb2_ssat16 in table
+ new OpcodeARM(Index.thumb2_ssat, "ssat", "11110x1100x0xxxx0xxxxxxxxxxxxxxx"),
// A8.6.189 STM / STMIA / STMEA
+ // Encoding T2 ARMv6T2, ARMv7
// stm<c>.w <Rn>{!},<registers>
- // 1 1 1 0 1 0 0 0 1 0 W_1_5_5 0 Rn_1_3_0 (0) M_0_14_14 (0) register_list_0_12_0
- // 1110100010x0xxxx(0)x(0)xxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 1110100010x0xxxx(0)x(0)xxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_stm, "stm.w", "1110100010x0xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.191 STMDB / STMFD
+ // Encoding T1 ARMv6T2, ARMv7
// stmdb<c> <Rn>{!},<registers>
- // 1 1 1 0 1 0 0 1 0 0 W_1_5_5 0 Rn_1_3_0 (0) M_0_14_14 (0) register_list_0_12_0
- // 1110100100x0xxxx(0)x(0)xxxxxxxxxxxxx
+ // Unpredictable if (0) is 1: 1110100100x0xxxx(0)x(0)xxxxxxxxxxxxx
new OpcodeARM(Index.thumb2_stmdb, "stmdb", "1110100100x0xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.307 VLD1 (multiple single elements)
+ // Encoding T1 / A1 Advanced SIMD
// vld1<c>.<size> <list>, [<Rn>{@<align>}]{!} vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.310 VLD2 (multiple 2-element structures)
+ // Encoding T1 / A1 Advanced SIMD
// vld2<c>.<size> <list>, [<Rn>{@<align>}]{!} vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.313 VLD3 (multiple 3-element structures)
+ // Encoding T1 / A1 Advanced SIMD
// vld3<c>.<size> <list>, [<Rn>{@<align>}]{!} vld3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.316 VLD4 (multiple 4-element structures)
+ // Encoding T1 / A1 Advanced SIMD
// vld4<c>.<size> <list>, [<Rn>{@<align>}]{!} vld4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 0 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
- // 111110010x10xxxxxxxxxxxxxxxxxxxx
//
- // must precede thumb2_str
+ // must precede thumb2_str in table
new OpcodeARM(Index.thumb2_vld__multi, "vld", "111110010x10xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.309 VLD1 (single element to all lanes)
+ // Encoding T1 / A1 Advanced SIMD
// vld1<c>.<size> <list>, [<Rn>{@<align>}]{!} vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 1 1 0 0 size_0_7_6 T_0_5_5 a_0_4_4 Rm_0_3_0
- // 111110011x10xxxxxxxx1100xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.308 VLD1 (single element to one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vld1<c>.<size> <list>, [<Rn>{@<align>}]{!} vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 0 0 index_align_0_7_4 Rm_0_3_0
- // 111110011x10xxxxxxxxxx00xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.312 VLD2 (single 2-element structure to all lanes)
+ // Encoding T1 / A1 Advanced SIMD
// vld2<c>.<size> <list>, [<Rn>{@<align>}]{!} vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 1 1 0 1 size_0_7_6 T_0_5_5 a_0_4_4 Rm_0_3_0
- // 111110011x10xxxxxxxx1101xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.311 VLD2 (single 2-element structure to one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vld2<c>.<size> <list>, [<Rn>{@<align>}]{!} vld2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 0 1 index_align_0_7_4 Rm_0_3_0
- // 111110011x10xxxxxxxxxx01xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.315 VLD3 (single 3-element structure to all lanes)
+ // Encoding T1 / A1 Advanced SIMD
// vld3<c>.<size> <list>, [<Rn>]{!} vld3<c>.<size> <list>, [<Rn>], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 1 1 1 0 size_0_7_6 T_0_5_5 a_0_4_4 Rm_0_3_0
- // 111110011x10xxxxxxxx1110xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.314 VLD3 (single 3-element structure to one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vld3<c>.<size> <list>, [<Rn>]{!} vld3<c>.<size> <list>, [<Rn>], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 1 0 index_align_0_7_4 Rm_0_3_0
- // 111110011x10xxxxxxxxxx10xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.318 VLD4 (single 4-element structure to all lanes)
+ // Encoding T1 / A1 Advanced SIMD
// vld4<c>.<size> <list>, [<Rn>{ @<align>}]{!} vld4<c>.<size> <list>, [<Rn>{ @<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 1 1 1 1 size_0_7_6 T_0_5_5 a_0_4_4 Rm_0_3_0
- // 111110011x10xxxxxxxx1111xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.317 VLD4 (single 4-element structure to one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vld4<c>.<size> <list>, [<Rn>{@<align>}]{!} vld4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 1 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 1 1 index_align_0_7_4 Rm_0_3_0
- // 111110011x10xxxxxxxxxx11xxxxxxxx
- //
- // must precede thumb2_str
+ //
+ // must precede thumb2_str in table
new OpcodeARM(Index.thumb2_vld__xlane, "vld", "111110011x10xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.391 VST1 (multiple single elements)
+ // Encoding T1 / A1 Advanced SIMD
// vst1<c>.<size> <list>, [<Rn>{@<align>}]{!} vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.393 VST2 (multiple 2-element structures)
+ // Encoding T1 / A1 Advanced SIMD
// vst2<c>.<size> <list>, [<Rn>{@<align>}]{!} vst2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.395 VST3 (multiple 3-element structures)
+ // Encoding T1 / A1 Advanced SIMD
// vst3<c>.<size> <list>, [<Rn>{@<align>}]{!} vst3<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.397 VST4 (multiple 4-element structures)
+ // Encoding T1 / A1 Advanced SIMD
// vst4<c>.<size> <list>, [<Rn>{@<align>}]{!} vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 0 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 type_0_11_8 size_0_7_6 align_0_5_4 Rm_0_3_0
- // 111110010x00xxxxxxxxxxxxxxxxxxxx
//
- // must precede thumb2_str
+ // must precede thumb2_str in table
new OpcodeARM(Index.thumb2_vst__multi, "vst", "111110010x00xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.392 VST1 (single element from one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vst1<c>.<size> <list>, [<Rn>{@<align>}]{!} vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 0 0 index_align_0_7_4 Rm_0_3_0
- // 111110011x00xxxxxxxxxx00xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.394 VST2 (single 2-element structure from one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vst2<c>.<size> <list>, [<Rn>{@<align>}]{!} vst2<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 0 1 index_align_0_7_4 Rm_0_3_0
- // 111110011x00xxxxxxxxxx01xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.396 VST3 (single 3-element structure from one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vst3<c>.<size> <list>, [<Rn>]{!} vst3<c>.<size> <list>, [<Rn>], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 1 0 index_align_0_7_4 Rm_0_3_0
- // 111110011x00xxxxxxxxxx10xxxxxxxx
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.398 VST4 (single 4-element structure from one lane)
+ // Encoding T1 / A1 Advanced SIMD
// vst4<c>.<size> <list>, [<Rn>{@<align>}]{!} vst4<c>.<size> <list>, [<Rn>{@<align>}], <Rm>
- // 1 1 1 1 1 0 0 1 1 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 size_0_11_10 1 1 index_align_0_7_4 Rm_0_3_0
- // 111110011x00xxxxxxxxxx11xxxxxxxx
- //
- // must precede thumb2_str in search table
+ //
+ // must precede thumb2_str in table
new OpcodeARM(Index.thumb2_vst__xlane, "vst", "111110011x00xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.193 STR (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
// str<c>.w <Rt>,[<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 0 1 1 0 0 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110001100xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T4 ARMv6T2, ARMv7
// A8.6.193 STR (immediate, Thumb)
+ // Encoding T4 ARMv6T2, ARMv7
// str<c> <Rt>,[<Rn>,#-<imm8>] str<c> <Rt>,[<Rn>],#+/-<imm8> str<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 0 0 1 0 0 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110000100xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.195 STR (register)
+ // Encoding T2 ARMv6T2, ARMv7
// str<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 1 0 0 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110000100xxxxxxxx000000xxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.196 STRB (immediate, Thumb)
+ // Encoding T2 ARMv6T2, ARMv7
// strb<c>.w <Rt>,[<Rn>,#<imm12>]
- // 1 1 1 1 1 0 0 0 1 0 0 0 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110001000xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.196 STRB (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
// strb<c> <Rt>,[<Rn>,#-<imm8>] strb<c> <Rt>,[<Rn>],#+/-<imm8> strb<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 0 0 0 0 0 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110000000xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.198 STRB (register)
+ // Encoding T2 ARMv6T2, ARMv7
// strb<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 0 0 0 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110000000xxxxxxxx000000xxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.199 STRBT
+ // Encoding T1 ARMv6T2, ARMv7
// strbt<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 0 0 0 0 0 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110000000xxxxxxxx1110xxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.206 STRH (immediate, Thumb)
+ // Encoding T2 ARMv6T2, ARMv7
// strh<c>.w <Rt>,[<Rn>{,#<imm12>}]
- // 1 1 1 1 1 0 0 0 1 0 1 0 Rn_1_3_0 Rt_0_15_12 imm12_0_11_0
- // 111110001010xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.206 STRH (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
// strh<c> <Rt>,[<Rn>,#-<imm8>] strh<c> <Rt>,[<Rn>],#+/-<imm8> strh<c> <Rt>,[<Rn>,#+/-<imm8>]!
- // 1 1 1 1 1 0 0 0 0 0 1 0 Rn_1_3_0 Rt_0_15_12 1 P_0_10_10 U_0_9_9 W_0_8_8 imm8_0_7_0
- // 111110000010xxxxxxxx1xxxxxxxxxxx
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.208 STRH (register)
+ // Encoding T2 ARMv6T2, ARMv7
// strh<c>.w <Rt>,[<Rn>,<Rm>{,lsl #<imm2>}]
- // 1 1 1 1 1 0 0 0 0 0 1 0 Rn_1_3_0 Rt_0_15_12 0 0 0 0 0 0 imm2_0_5_4 Rm_0_3_0
- // 111110000010xxxxxxxx000000xxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.209 STRHT
+ // Encoding T1 ARMv6T2, ARMv7
// strht<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 0 0 0 1 0 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110000010xxxxxxxx1110xxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.210 STRT
+ // Encoding T1 ARMv6T2, ARMv7
// strt<c> <Rt>,[<Rn>,#<imm8>]
- // 1 1 1 1 1 0 0 0 0 1 0 0 Rn_1_3_0 Rt_0_15_12 1 1 1 0 imm8_0_7_0
- // 111110000100xxxxxxxx1110xxxxxxxx
//
- // must follow thumb2_push__reg in search table
- // must follow thumb2_vld__multi in search table
- // must follow thumb2_vld__xlane in search table
- // must follow thumb2_vst__multi in search table
- // must follow thumb2_vst__xlane in search table
- new OpcodeARM(Index.thumb2_str, "str", "1111100xxxx0xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
+ // must follow thumb2_push__reg in table
+ // must follow thumb2_vld__multi in table
+ // must follow thumb2_vld__xlane in table
+ // must follow thumb2_vst__multi in table
+ // must follow thumb2_vst__xlane in table
+ new OpcodeARM(Index.thumb2_str, "str", "1111100xxxx0xxxxxxxxxxxxxxxxxxxx"),
// A8.6.202 STREX
+ // Encoding T1 ARMv6T2, ARMv7
// strex<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
- // 1 1 1 0 1 0 0 0 0 1 0 0 Rn_1_3_0 Rt_0_15_12 Rd_0_11_8 imm8_0_7_0
- // 111010000100xxxxxxxxxxxxxxxxxxxx
- // must precede thumb2_strd in search table
- new OpcodeARM(Index.thumb2_strex, "strex", "111010000100xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv7
+ // must precede thumb2_strd in table
+ new OpcodeARM(Index.thumb2_strex, "strex", "111010000100xxxxxxxxxxxxxxxxxxxx"),
// A8.6.203 STREXB
+ // Encoding T1 ARMv7
// strexb<c> <Rd>,<Rt>,[<Rn>]
- // 1 1 1 0 1 0 0 0 1 1 0 0 Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) 0 1 0 0 Rd
- // 111010001100xxxxxxxx(1)(1)(1)(1)0100xxxx
- // must precede thumb2_strd in search table
- // NEW - Encoding T1 ARMv7
+ // Unpredictable if (1) is 0: 111010001100xxxxxxxx(1)(1)(1)(1)0100xxxx
+ // must precede thumb2_strd in table
// A8.6.204 STREXD
+ // Encoding T1 ARMv7
// strexd<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
- // 1 1 1 0 1 0 0 0 1 1 0 0 Rn_1_3_0 Rt_0_15_12 Rt2_0_11_8 0 1 1 1 Rd_0_3_0
- // 111010001100xxxxxxxxxxxx0111xxxx
- // NEW - Encoding T1 ARMv7
// A8.6.205 STREXH
+ // Encoding T1 ARMv7
// strexh<c> <Rd>,<Rt>,[<Rn>]
- // 1 1 1 0 1 0 0 0 1 1 0 0 Rn_1_3_0 Rt_0_15_12 (1)(1)(1)(1) 0 1 0 1 Rd
- // 111010001100xxxxxxxx(1)(1)(1)(1)0101xxxx
+ // Unpredictable if (1) is 0: 111010001100xxxxxxxx(1)(1)(1)(1)0101xxxx
//
- // must precede thumb2_strd in search table
+ // must precede thumb2_strd in table
new OpcodeARM(Index.thumb2_strexx, "strex", "111010001100xxxxxxxxxxxx01xxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.200 STRD (immediate)
- // strd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}] strd<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm> strd<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
- // 1 1 1 0 1 0 0 P_1_8_8 U_1_7_7 1 W_1_5_5 0 Rn_1_3_0 Rt_0_15_12 Rt2_0_11_8 imm8_0_7_0
- // 1110100xx1x0xxxxxxxxxxxxxxxxxxxx
- // must follow thumb2_strex in search table
- // must follow thumb2_strexx in search table
- new OpcodeARM(Index.thumb2_strd, "strd", "1110100xx1x0xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T4 ARMv6T2, ARMv7
+ // Encoding T1 ARMv6T2, ARMv7
+ // strd<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}] strd<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm>
+ // strd<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
+ // must follow thumb2_strex in table
+ // must follow thumb2_strexx in table
+ new OpcodeARM(Index.thumb2_strd, "strd", "1110100xx1x0xxxxxxxxxxxxxxxxxxxx"),
// A8.6.211 SUB (immediate, Thumb)
+ // Encoding T4 ARMv6T2, ARMv7
// subw<c> <Rd>,<Rn>,#<imm12>
- // 1 1 1 1 0 i_1_10_10 1 0 1 0 1 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x101010xxxx0xxxxxxxxxxxxxxx
- // must follow thumb2_adr__sub in search table
- // must follow thumb2_cmp__imm in search table
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.215 SUB (SP minus immediate)
+ // Encoding T3 ARMv6T2, ARMv7
// subw <Rd>,sp,#<imm12>
- // 1 1 1 1 0 i_1_10_10 1 0 1 0 1 0 1 1 0 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x10101011010xxxxxxxxxxxxxxx
//
+ // must follow thumb2_adr__sub in table
+ // must follow thumb2_cmp__imm in table
new OpcodeARM(Index.thumb2_subw, "subw", "11110x101010xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T3 ARMv6T2, ARMv7
// A8.6.211 SUB (immediate, Thumb)
+ // Encoding T3 ARMv6T2, ARMv7
// sub{s}<c>.w <Rd>,<Rn>,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 1 0 1 S_1_4_4 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01101xxxxx0xxxxxxxxxxxxxxx
- // must follow thumb2_cmp__imm in search table
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.215 SUB (SP minus immediate)
+ // Encoding T2 ARMv6T2, ARMv7
// sub{s}.w <Rd>,sp,#<const>
- // 1 1 1 1 0 i_1_10_10 0 1 1 0 1 S_1_4_4 1 1 0 1 0 imm3_0_14_12 Rd_0_11_8 imm8_0_7_0
- // 11110x01101x11010xxxxxxxxxxxxxxx
- //
- new OpcodeARM(Index.thumb2_sub__imm, "sub", "11110x01101xxxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
- // A8.6.213 SUB (register)
- // sub{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 1 0 1 S_1_4_4 Rn_1_3_0 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011101xxxxx(0)xxxxxxxxxxxxxxx
- // NEW - Encoding T1 ARMv6T2, ARMv7
- // A8.6.216 SUB (SP minus register)
- // sub{s} <Rd>,sp,<Rm>{,<shift>}
- // 1 1 1 0 1 0 1 1 1 0 1 S_1_4_4 1 1 0 1 (0) imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 type_0_5_4 Rm_0_3_0
- // 11101011101x1101(0)xxxxxxxxxxxxxxx
//
- // must follow thumb2_cmp__reg in search table
+ // must follow thumb2_cmp__imm in table
+ new OpcodeARM(Index.thumb2_sub__imm, "sub", "11110x01101xxxxx0xxxxxxxxxxxxxxx"),
+ // A8.6.213 SUB (register)
+ // Encoding T2 ARMv6T2, ARMv7
+ // sub{s}<c>.w <Rd>,<Rn>,<Rm>{,<shift>}
+ // Unpredictable if (0) is 1: 11101011101xxxxx(0)xxxxxxxxxxxxxxx
+ // A8.6.216 SUB (SP minus register)
+ // Encoding T1 ARMv6T2, ARMv7
+ // sub{s} <Rd>,sp,<Rm>{,<shift>}
+ // Unpredictable if (0) is 1: 11101011101x1101(0)xxxxxxxxxxxxxxx
+ //
+ // must follow thumb2_cmp__reg in table
new OpcodeARM(Index.thumb2_sub__reg, "sub", "11101011101xxxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.223 SXTB
+ // Encoding T2 ARMv6T2, ARMv7
// sxtb<c>.w <Rd>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 11111010010011111111xxxx1(0)xxxxxx
- // must precede thumb2_sxtab in search table
+ // Unpredictable if (0) is 1: 11111010010011111111xxxx1(0)xxxxxx
+ // must precede thumb2_sxtab in table
new OpcodeARM(Index.thumb2_sxtb, "sxtb.w", "11111010010011111111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.220 SXTAB
+ // Encoding T1 ARMv6T2, ARMv7
// sxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 1 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 111110100100xxxx1111xxxx1(0)xxxxxx
- // must follow thumb2_sxtb in search table
+ // Unpredictable if (0) is 1: 111110100100xxxx1111xxxx1(0)xxxxxx
+ // must follow thumb2_sxtb in table
new OpcodeARM(Index.thumb2_sxtab, "sxtab", "111110100100xxxx1111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.224 SXTB16
+ // Encoding T1 ARMv6T2, ARMv7
// sxtb16<c> <Rd>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 11111010001011111111xxxx1(0)xxxxxx
- // must precede thumb2_sxtab16 in search table
+ // Unpredictable if (0) is 1: 11111010001011111111xxxx1(0)xxxxxx
+ // must precede thumb2_sxtab16 in table
new OpcodeARM(Index.thumb2_sxtb16, "sxtb16", "11111010001011111111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.221 SXTAB16
+ // Encoding T1 ARMv6T2, ARMv7
// sxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 1 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 111110100010xxxx1111xxxx1(0)xxxxxx
- // must follow thumb2_sxtb16 in search table
+ // Unpredictable if (0) is 1: 111110100010xxxx1111xxxx1(0)xxxxxx
+ // must follow thumb2_sxtb16 in table
new OpcodeARM(Index.thumb2_sxtab16, "sxtab16", "111110100010xxxx1111xxxx1xxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.225 SXTH
+ // Encoding T2 ARMv6T2, ARMv7
// sxth<c>.w <Rd>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 11111010000011111111xxxx1(0)xxxxxx
- // must precede thumb2_sxtah in search table
+ // Unpredictable if (0) is 1: 11111010000011111111xxxx1(0)xxxxxx
+ // must precede thumb2_sxtah in table
new OpcodeARM(Index.thumb2_sxth, "sxth.w", "11111010000011111111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.222 SXTAH
+ // Encoding T1 ARMv6T2, ARMv7
// sxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 0 0 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 111110100000xxxx1111xxxx1(0)xxxxxx
- // must follow thumb2_sxth in search table
+ // Unpredictable if (0) is 1: 111110100000xxxx1111xxxx1(0)xxxxxx
+ // must follow thumb2_sxth in table
new OpcodeARM(Index.thumb2_sxtah, "sxtah", "111110100000xxxx1111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.226 TBB, TBH
+ // Encoding T1 ARMv6T2, ARMv7
// tbb<c> [<Rn>,<Rm>] Outside or last in IT block tbh<c> [<Rn>,<Rm>,LSL #1] Outside or last in IT block
- // 1 1 1 0 1 0 0 0 1 1 0 1 Rn_1_3_0 (1) (1)(1)(1)(0)(0)(0)(0) 0 0 0 H_0_4_4 Rm_0_3_0
- // 111010001101xxxx(1)(1)(1)(1)(0)(0)(0)(0)000xxxxx
+ // Unpredictable if (1) is 0 or (0) is 1: 111010001101xxxx(1)(1)(1)(1)(0)(0)(0)(0)000xxxxx
new OpcodeARM(Index.thumb2_tb, "tb", "111010001101xxxxxxxxxxxx000xxxxx"),
-
- // NEW - Encoding T1 ARMv7-R
// A8.6.237 UDIV
+ // Encoding T1 ARMv7-R
// udiv<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 0 1 1 Rn_1_3_0 (1) (1)(1)(1) Rd_0_11_8 1 1 1 1 Rm_0_3_0
- // 111110111011xxxx(1)(1)(1)(1)xxxx1111xxxx
+ // Unpredictable if (1) is 0: 111110111011xxxx(1)(1)(1)(1)xxxx1111xxxx
new OpcodeARM(Index.thumb2_udiv, "udiv", "111110111011xxxxxxxxxxxx1111xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.244 UMAAL
+ // Encoding T1 ARMv6T2, ARMv7
// umaal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 1 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 0 1 1 0 Rm_0_3_0
- // 111110111110xxxxxxxxxxxx0110xxxx
new OpcodeARM(Index.thumb2_umaal, "umaal", "111110111110xxxxxxxxxxxx0110xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.245 UMLAL
+ // Encoding T1 ARMv6T2, ARMv7
// umlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 1 1 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110111110xxxxxxxxxxxx0000xxxx
new OpcodeARM(Index.thumb2_umlal, "umlal", "111110111110xxxxxxxxxxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.246 UMULL
+ // Encoding T1 ARMv6T2, ARMv7
// umull<c> <RdLo>,<RdHi>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 1 0 1 0 Rn_1_3_0 RdLo_0_15_12 RdHi_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110111010xxxxxxxxxxxx0000xxxx
new OpcodeARM(Index.thumb2_umull, "umull", "111110111010xxxxxxxxxxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.253 USAD8
+ // Encoding T1 ARMv6T2, ARMv7
// usad8<c> <Rd>,<Rn>,<Rm>
- // 1 1 1 1 1 0 1 1 0 1 1 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110110111xxxx1111xxxx0000xxxx
new OpcodeARM(Index.thumb2_usad8, "usad8", "111110110111xxxx1111xxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.254 USADA8
+ // Encoding T1 ARMv6T2, ARMv7
// usada8<c> <Rd>,<Rn>,<Rm>,<Ra>
- // 1 1 1 1 1 0 1 1 0 1 1 1 Rn_1_3_0 Ra_0_15_12 Rd_0_11_8 0 0 0 0 Rm_0_3_0
- // 111110110111xxxxxxxxxxxx0000xxxx
new OpcodeARM(Index.thumb2_usada8, "usada8", "111110110111xxxxxxxxxxxx0000xxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.256 USAT16
+ // Encoding T1 ARMv6T2, ARMv7
// usat16<c> <Rd>,#<imm4>,<Rn>
- // 1 1 1 1 0 (0) 1 1 1 0 1 0 Rn_1_3_0 0 0 0 0 Rd_0_11_8 0 0 (0)(0) sat_imm_0_3_0
- // 11110(0)111010xxxx0000xxxx00(0)(0)xxxx
- // must precede thumb2_usat in search table
+ // Unpredictable if (0) is 1: 11110(0)111010xxxx0000xxxx00(0)(0)xxxx
+ // must precede thumb2_usat in table
new OpcodeARM(Index.thumb2_usat16, "usat16", "11110x111010xxxx0000xxxx00xxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.255 USAT
+ // Encoding T1 ARMv6T2, ARMv7
// usat<c> <Rd>,#<imm5>,<Rn>{,<shift>}
- // 1 1 1 1 0 (0) 1 1 1 0 sh_1_5_5 0 Rn_1_3_0 0 imm3_0_14_12 Rd_0_11_8 imm2_0_7_6 (0) sat_imm_0_4_0
- // 11110(0)1110x0xxxx0xxxxxxxxx(0)xxxxx
- // must follow thumb2_usat16 in search table
+ // Unpredictable if (0) is 1: 11110(0)1110x0xxxx0xxxxxxxxx(0)xxxxx
+ // must follow thumb2_usat16 in table
new OpcodeARM(Index.thumb2_usat, "usat", "11110x1110x0xxxx0xxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.263 UXTB
+ // Encoding T2 ARMv6T2, ARMv7
// uxtb<c>.w <Rd>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 11111010010111111111xxxx1(0)xxxxxx
- // must precede thumb2_uxtab in search table
+ // Unpredictable if (0) is 1: 11111010010111111111xxxx1(0)xxxxxx
+ // must precede thumb2_uxtab in table
new OpcodeARM(Index.thumb2_uxtb, "uxtb.w", "11111010010111111111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.260 UXTAB
+ // Encoding T1 ARMv6T2, ARMv7
// uxtab<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 1 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 111110100101xxxx1111xxxx1(0)xxxxxx
- // must follow thumb2_uxtb in search table
+ // Unpredictable if (0) is 1: 111110100101xxxx1111xxxx1(0)xxxxxx
+ // must follow thumb2_uxtb in table
new OpcodeARM(Index.thumb2_uxtab, "uxtab", "111110100101xxxx1111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.264 UXTB16
+ // Encoding T1 ARMv6T2, ARMv7
// uxtb16<c> <Rd>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 11111010001111111111xxxx1(0)xxxxxx
- // must precede thumb2_uxtab16 in search table
+ // Unpredictable if (0) is 1: 11111010001111111111xxxx1(0)xxxxxx
+ // must precede thumb2_uxtab16 in table
new OpcodeARM(Index.thumb2_uxtb16, "uxtb16", "11111010001111111111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.261 UXTAB16
+ // Encoding T1 ARMv6T2, ARMv7
// uxtab16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 1 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 111110100011xxxx1111xxxx1(0)xxxxxx
- // must follow thumb2_uxtb16 in search table
+ // Unpredictable if (0) is 1: 111110100011xxxx1111xxxx1(0)xxxxxx
+ // must follow thumb2_uxtb16 in table
new OpcodeARM(Index.thumb2_uxtab16, "uxtab16", "111110100011xxxx1111xxxx1xxxxxxx"),
-
- // NEW - Encoding T2 ARMv6T2, ARMv7
// A8.6.265 UXTH
+ // Encoding T2 ARMv6T2, ARMv7
// uxth<c>.w <Rd>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 11111010000111111111xxxx1(0)xxxxxx
- // must precede thumb2_uxtabh in search table
+ // Unpredictable if (0) is 1: 11111010000111111111xxxx1(0)xxxxxx
+ // must precede thumb2_uxtabh in table
new OpcodeARM(Index.thumb2_uxth, "uxth.w", "11111010000111111111xxxx1xxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
// A8.6.262 UXTAH
+ // Encoding T1 ARMv6T2, ARMv7
// uxtah<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- // 1 1 1 1 1 0 1 0 0 0 0 1 Rn_1_3_0 1 1 1 1 Rd_0_11_8 1 (0) rotate_0_5_4 Rm_0_3_0
- // 111110100001xxxx1111xxxx1(0)xxxxxx
- // must follow thumb2_uxth in search table
+ // Unpredictable if (0) is 1: 111110100001xxxx1111xxxx1(0)xxxxxx
+ // must follow thumb2_uxth in table
new OpcodeARM(Index.thumb2_uxtah, "uxtah", "111110100001xxxx1111xxxx1xxxxxxx"),
-
-
// VFP and Advanced SIMD instructions
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.266 VABA, VABAL
+ // Encoding T1 / A1 Advanced SIMD
// vaba<c>.<dt> <Qd>, <Qn>, <Qm> vaba<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0111xxx1xxxx
new OpcodeARM(Index.thumb2_vaba, "vaba", "111x11110xxxxxxxxxxx0111xxx1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.267 VABD, VABDL (integer)
+ // Encoding T1 / A1 Advanced SIMD
// vabd<c>.<dt> <Qd>, <Qn>, <Qm> vabd<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0111xxx0xxxx
new OpcodeARM(Index.thumb2_vabd__int, "vabd", "111x11110xxxxxxxxxxx0111xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.268 VABD (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vabd<c>.f32 <Qd>, <Qn>, <Qm> vabd<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 1 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110x1xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.thumb2_vabd__f32, "vabd", "111111110x1xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variant)
// A8.6.269 VABS
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variant)
// vabs<c>.<dt> <Qd>, <Qm> vabs<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 1 1 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x110xx0xxxx
- // must precede thumb2_vabdl
+ // must precede thumb2_vabdl in table
new OpcodeARM(Index.thumb2_vabs, "vabs", "111111111x11xx01xxxx0x110xx0xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.269 VABS
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vabs<c>.f64 <Dd>, <Dm> vabs<c>.f32 <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 0 0 0 Vd_0_15_12 1 0 1 sz_0_8_8 1 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x110000xxxx101x11x0xxxx
new OpcodeARM(Index.thumb2_vabs__f, "vabs", "111011101x110000xxxx101x11x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.270 VACGE, VACGT, VACLE, VACLT
- // vacge<c>.f32 <Qd>, <Qn>, <Qm> vacge<c>.f32 <Dd>, <Dn>, <Dm> vacgt<c>.f32 <Qd>, <Qn>, <Qm> vacgt<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 op_1_5_5 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111111110xxxxxxxxxxx1110xxx1xxxx
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
+ // vacge<c>.f32 <Qd>, <Qn>, <Qm> vacge<c>.f32 <Dd>, <Dn>, <Dm>
+ // vacgt<c>.f32 <Qd>, <Qn>, <Qm> vacgt<c>.f32 <Dd>, <Dn>, <Dm>
new OpcodeARM(Index.thumb2_vacge_vacgt, "vac", "111111110xxxxxxxxxxx1110xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.271 VADD (integer)
+ // Encoding T1 / A1 Advanced SIMD
// vadd<c>.<dt> <Qd>, <Qn>, <Qm> vadd<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011110xxxxxxxxxxx1000xxx0xxxx
new OpcodeARM(Index.thumb2_vadd__int, "vadd", "111011110xxxxxxxxxxx1000xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variants)
// A8.6.272 VADD (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variants)
// vadd<c>.f32 <Qd>, <Qn>, <Qm> vadd<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 0 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011110x0xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.thumb2_vadd__f32, "vadd", "111011110x0xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.272 VADD (floating-point)
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vadd<c>.f64 <Dd>, <Dn>, <Dm> vadd<c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 1 1 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011100x11xxxxxxxx101xx0x0xxxx
new OpcodeARM(Index.thumb2_vadd__fp_f, "vadd", "111011100x11xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.273 VADDHN
+ // Encoding T1 / A1 Advanced SIMD
// vaddhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011111xxxxxxxxxxx0100x0x0xxxx
new OpcodeARM(Index.thumb2_vaddhn, "vaddhn", "111011111xxxxxxxxxxx0100x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.276 VAND (register)
+ // Encoding T1 / A1 Advanced SIMD
// vand<c> <Qd>, <Qn>, <Qm> vand<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 0 0 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x00xxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.thumb2_vand, "vand", "111011110x00xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.278 VBIC (register)
+ // Encoding T1 / A1 Advanced SIMD
// vbic<c> <Qd>, <Qn>, <Qm> vbic<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 0 1 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x01xxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.thumb2_vbic__reg, "vbic", "111011110x01xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.304 VEOR - MUST PRECEDE VBIF/VBIT/VBSL
+ // Encoding T1 / A1 Advanced SIMD
// veor<c> <Qd>, <Qn>, <Qm> veor<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 0 0 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
-// see thumb2_vbif_vbit_vbsl_veor
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.279 VBIF, VBIT, VBSL
- // vbif<c> <Qd>, <Qn>, <Qm> vbif<c> <Dd>, <Dn>, <Dm> vbit<c> <Qd>, <Qn>, <Qm> vbit<c> <Dd>, <Dn>, <Dm> vbsl<c> <Qd>, <Qn>, <Qm> vbsl<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 op_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
+ // Encoding T1 / A1 Advanced SIMD
+ // vbif<c> <Qd>, <Qn>, <Qm> vbif<c> <Dd>, <Dn>, <Dm> vbit<c> <Qd>, <Qn>, <Qm
+ // vbit<c> <Dd>, <Dn>, <Dm> vbsl<c> <Qd>, <Qn>, <Qm> vbsl<c> <Dd>, <Dn>, <Dm>
//
- // 111111110x00xxxxxxxx0001xxx1xxxx
- // 111111110xxxxxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.thumb2_vbif_vbit_vbsl_veor, "v", "111111110xxxxxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.280 VCEQ (register)
+ // Encoding T1 / A1 Advanced SIMD
// vceq<c>.<dt> <Qd>, <Qn>, <Qm> vceq<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111111110xxxxxxxxxxx1000xxx1xxxx
new OpcodeARM(Index.thumb2_vceq__reg_int, "vceq", "111111110xxxxxxxxxxx1000xxx1xxxx"),
- // NEW - Encoding T2 / A2 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.280 VCEQ (register)
+ // Encoding T2 / A2 Advanced SIMD (UNDEFINED in integer-only variant)
// vceq<c>.f32 <Qd>, <Qn>, <Qm> vceq<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 0 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011110x0xxxxxxxxx1110xxx0xxxx
new OpcodeARM(Index.thumb2_vceq__reg_f32, "vceq", "111011110x0xxxxxxxxx1110xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.281 VCEQ (immediate #0)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vceq<c>.<dt> <Qd>, <Qm>, #0 vceq<c>.<dt> <Dd>, <Dm>, #0
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 0 1 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x010xx0xxxx
- // must precede thumb2_vaddl_vaddw
- // must precede thumb2_vabal
+ // must precede thumb2_vaddl_vaddw in table
+ // must precede thumb2_vabal in table
new OpcodeARM(Index.thumb2_vceq__imm0, "vceq", "111111111x11xx01xxxx0x010xx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.282 VCGE (register)
+ // Encoding T1 / A1 Advanced SIMD
// vcge<c>.<dt> <Qd>, <Qn>, <Qm> vcge<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0011xxx1xxxx
new OpcodeARM(Index.thumb2_vcge__reg_int, "vcge", "111x11110xxxxxxxxxxx0011xxx1xxxx"),
- // NEW - Encoding T2 / A2 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.282 VCGE (register)
+ // Encoding T2 / A2 Advanced SIMD (UNDEFINED in integer-only variant)
// vcge<c>.f32 <Qd>, <Qn>, <Qm> vcge<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 0 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110x0xxxxxxxxx1110xxx0xxxx
new OpcodeARM(Index.thumb2_vcge__reg_f32, "vcge", "111111110x0xxxxxxxxx1110xxx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.284 VCGT (register)
+ // Encoding T1 / A1 Advanced SIMD
// vcgt<c>.<dt> <Qd>, <Qn>, <Qm> vcgt<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0011xxx0xxxx
new OpcodeARM(Index.thumb2_vcgt__reg_int, "vcgt", "111x11110xxxxxxxxxxx0011xxx0xxxx"),
- // NEW - Encoding T2 / A2 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.284 VCGT (register)
+ // Encoding T2 / A2 Advanced SIMD (UNDEFINED in integer-only variant)
// vcgt<c>.f32 <Qd>, <Qn>, <Qm> vcgt<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 1 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110x1xxxxxxxxx1110xxx0xxxx
new OpcodeARM(Index.thumb2_vcgt__reg_f32, "vcgt", "111111110x1xxxxxxxxx1110xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.283 VCGE (immediate #0)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vcge<c>.<dt> <Qd>, <Qm>, #0 vcge<c>.<dt> <Dd>, <Dm>, #0
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 0 0 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x001xx0xxxx
- // must precede thumb2_vaddl_vaddw
+ // must precede thumb2_vaddl_vaddw in table
new OpcodeARM(Index.thumb2_vcge__imm0, "vcge", "111111111x11xx01xxxx0x001xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.285 VCGT (immediate #0)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vcgt<c>.<dt> <Qd>, <Qm>, #0 vcgt<c>.<dt> <Dd>, <Dm>, #0
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 0 0 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x000xx0xxxx
- // must precede thumb2_vaddl_vaddw
+ // must precede thumb2_vaddl_vaddw in table
new OpcodeARM(Index.thumb2_vcgt__imm0, "vcgt", "111111111x11xx01xxxx0x000xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.287 VCLE (immediate #0)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vcle<c>.<dt> <Qd>, <Qm>, #0 vcle<c>.<dt> <Dd>, <Dm>, #0
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 0 1 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x011xx0xxxx
- // must precede thumb2_vaddl_vaddw
+ // must precede thumb2_vaddl_vaddw in table
new OpcodeARM(Index.thumb2_vcle, "vcle", "111111111x11xx01xxxx0x011xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.288 VCLS
+ // Encoding T1 / A1 Advanced SIMD
// vcls<c>.<dt> <Qd>, <Qm> vcls<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 0 0 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx01000xx0xxxx
new OpcodeARM(Index.thumb2_vcls, "vcls", "111111111x11xx00xxxx01000xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.290 VCLT (immediate #0)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vclt<c>.<dt> <Qd>, <Qm>, #0 vclt<c>.<dt> <Dd>, <Dm>, #0
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 1 0 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x100xx0xxxx
new OpcodeARM(Index.thumb2_vclt, "vclt", "111111111x11xx01xxxx0x100xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.291 VCLZ
+ // Encoding T1 / A1 Advanced SIMD
// vclz<c>.<dt> <Qd>, <Qm> vclz<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 0 0 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx01001xx0xxxx
new OpcodeARM(Index.thumb2_vclz, "vclz", "111111111x11xx00xxxx01001xx0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.292 VCMP, VCMPE
+ // Encoding T1 / A1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vcmp{e}<c>.f64 <Dd>, <Dm> vcmp{e}<c>.f32 <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 1 0 0 Vd_0_15_12 1 0 1 sz_0_8_8 E_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x110100xxxx101xx1x0xxxx
new OpcodeARM(Index.thumb2_vcmp__reg, "vcmp", "111011101x110100xxxx101xx1x0xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.292 VCMP, VCMPE
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vcmp{e}<c>.f64 <Dd>, #0.0 vcmp{e}<c>.f32 <Sd>, #0.0
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 1 0 1 Vd_0_15_12 1 0 1 sz_0_8_8 E_0_7_7 1 (0) 0 (0)(0)(0)(0)
- // 111011101x110101xxxx101xx1(0)0(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 111011101x110101xxxx101xx1(0)0(0)(0)(0)(0)
new OpcodeARM(Index.thumb2_vcmp__to_0, "vcmp", "111011101x110101xxxx101xx1x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.293 VCNT
+ // Encoding T1 / A1 Advanced SIMD
// vcnt<c>.8 <Qd>, <Qm> vcnt<c>.8 <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 0 1 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx01010xx0xxxx
new OpcodeARM(Index.thumb2_vcnt, "vcnt", "111111111x11xx00xxxx01010xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.294 VCVT (between floating-point and integer, Advanced SIMD)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vcvt<c>.<Td>.<Tm> <Qd>, <Qm> vcvt<c>.<Td>.<Tm> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 1 Vd_0_15_12 0 1 1 op_0_8_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx11xxxx011xxxx0xxxx
new OpcodeARM(Index.thumb2_vcvt__fp_i_vec, "vcvt", "111111111x11xx11xxxx011xxxx0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv3 (sf = 1 UNDEFINED in single-precision only variants)
// A8.6.297 VCVT (between floating-point and fixed-point, VFP)
- // vcvt<c>.<Td>.f64 <Dd>, <Dd>, #<fbits> vcvt<c>.<Td>.f32 <Sd>, <Sd>, #<fbits> vcvt<c>.f64.<Td> <Dd>, <Dd>, #<fbits> vcvt<c>.f32.<Td> <Sd>, <Sd>, #<fbits>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 1 op_1_2_2 1 U_1_0_0 Vd_0_15_12 1 0 1 sf_0_8_8 sx_0_7_7 1 i_0_5_5 0 imm4_0_3_0
- // 111011101x111x1xxxxx101xx1x0xxxx
- // must precede thumb2_vcvt__fp_i_reg
+ // Encoding T1 / A1 VFPv3 (sf = 1 UNDEFINED in single-precision only variants)
+ // vcvt<c>.<Td>.f64 <Dd>, <Dd>, #<fbits> vcvt<c>.<Td>.f32 <Sd>, <Sd>, #<fbits>
+ // vcvt<c>.f64.<Td> <Dd>, <Dd>, #<fbits> vcvt<c>.f32.<Td> <Sd>, <Sd>, #<fbits>
+ // must precede thumb2_vcvt__fp_i_reg in table
new OpcodeARM(Index.thumb2_vcvt__fp_fix_reg, "vcvt", "111011101x111x1xxxxx101xx1x0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.295 VCVT, VCVTR (between floating-point and integer, VFP)
- // vcvt{r}<c>.s32.f64 <Sd>, <Dm> vcvt{r}<c>.s32.f32 <Sd>, <Sm> vcvt{r}<c>.u32.f64 <Sd>, <Dm> vcvt{r}<c>.u32.f32 <Sd>, <Sm> vcvt<c>.f64.<Tm> <Dd>, <Sm> vcvt<c>.f32.<Tm> <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 1 opc2_1_2_0 Vd_0_15_12 1 0 1 sz_0_8_8 op_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x111xxxxxxx101xx1x0xxxx
- // must follow thumb2_vcvt__fp_fix_reg
+ // Encoding T1 / A1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
+ // vcvt{r}<c>.s32.f64 <Sd>, <Dm> vcvt{r}<c>.s32.f32 <Sd>, <Sm> vcvt{r}<c>.u32.f64 <Sd>, <Dm>
+ // vcvt{r}<c>.u32.f32 <Sd>, <Sm> vcvt<c>.f64.<Tm> <Dd>, <Sm> vcvt<c>.f32.<Tm> <Sd>, <Sm>
+ // must follow thumb2_vcvt__fp_fix_reg in table
new OpcodeARM(Index.thumb2_vcvt__fp_i_reg, "vcvt", "111011101x111xxxxxxx101xx1x0xxxx"),
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
- // A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 1 0 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0x10x1x0xxxx
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.277 VBIC (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vbic<c>.<dt> <Qd>, #<imm> vbic<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 1 1 imm4_0_3_0
-// see thumb2_vmov_vbitwise
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.346 VORR (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vorr<c>.<dt> <Qd>, #<imm> vorr<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 0 1 imm4_0_3_0
-// see thumb2_vmov_vbitwise
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.340 VMVN (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vmvn<c>.<dt> <Qd>, #<imm> vmvn<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 1 1 imm4_0_3_0
-// see thumb2_vmov_vbitwise
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.326 VMOV (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vmov<c>.<dt> <Qd>, #<imm> vmov<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 op_0_5_5 1 imm4_0_3_0
//
- // 111x11111x000xxxxxxxxxxx0x11xxxx
- // 111x11111x000xxxxxxxxxxx0x01xxxx
- // 111x11111x000xxxxxxxxxxx0x11xxxx
- // 111x11111x000xxxxxxxxxxx0xx1xxxx
- // must precede thumb2_vcvt__fp_fix_vec
+ // must precede thumb2_vcvt__fp_fix_vec in table
new OpcodeARM(Index.thumb2_vmov_vbitwise, "_", "111x11111x000xxxxxxxxxxx0xx1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vcvt<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> vcvt<c>.<Td>.<Tm> <Dd>, <Dm>, #<fbits>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 1 1 1 op_0_8_8 0 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx111x0xx1xxxx
- // must follow thumb2_vmov_vbitwise
+ // must follow thumb2_vmov_vbitwise in table
new OpcodeARM(Index.thumb2_vcvt__fp_fix_vec, "vcvt", "111x11111xxxxxxxxxxx111x0xx1xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3 (UNDEFINED in single-precision only variants)
// A8.6.298 VCVT (between double-precision and single-precision)
+ // Encoding T1 / A1 VFPv2, VFPv3 (UNDEFINED in single-precision only variants)
// vcvt<c>.f64.f32 <Dd>, <Sm> vcvt<c>.f32.f64 <Sd>, <Dm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 1 1 1 Vd_0_15_12 1 0 1 sz_0_8_8 1 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x110111xxxx101x11x0xxxx
new OpcodeARM(Index.thumb2_vcvt__dp_sp, "vcvt", "111011101x110111xxxx101x11x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD with half-precision extensions (UNDEFINED in integer-only variant)
// A8.6.299 VCVT (between half-precision and single-precision, Advanced SIMD)
+ // Encoding T1 / A1 Advanced SIMD with half-precision extensions (UNDEFINED in integer-only variant)
// vcvt<c>.f32.f16 <Qd>, <Dm> vcvt<c>.f16.f32 <Dd>, <Qm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 1 1 op_0_8_8 0 0 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx011x00x0xxxx
new OpcodeARM(Index.thumb2_vcvt__hp_sp_vec, "vcvt", "111111111x11xx10xxxx011x00x0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv3 half-precision extensions
// A8.6.300 VCVTB, VCVTT (between half-precision and single-precision, VFP)
+ // Encoding T1 / A1 VFPv3 half-precision extensions
// vcvt<y><c>.f32.f16 <Sd>, <Sm> vcvt<y><c>.f16.f32 <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 0 1 op_1_0_0 Vd_0_15_12 1 0 1 (0) T_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x11001xxxxx1010x1x0xxxx
new OpcodeARM(Index.thumb2_vcvt__hp_sp_reg, "vcvt", "111011101x11001xxxxx1010x1x0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.301 VDIV
+ // Encoding T1 / A1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vdiv<c>.f64 <Dd>, <Dn>, <Dm> vdiv<c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 0 0 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011101x00xxxxxxxx101xx0x0xxxx
new OpcodeARM(Index.thumb2_vdiv, "vdiv", "111011101x00xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.302 VDUP (scalar)
+ // Encoding T1 / A1 Advanced SIMD
// vdup<c>.<size> <Qd>, <Dm[x]> vdup<c>.<size> <Dd>, <Dm[x]>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 imm4_1_3_0 Vd_0_15_12 1 1 0 0 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xxxxxxxx11000xx0xxxx
new OpcodeARM(Index.thumb2_vdup__scalar, "vdup", "111111111x11xxxxxxxx11000xx0xxxx"),
- // NEW - Encoding T1 / A1 (cond) Advanced SIMD
// A8.6.303 VDUP (ARM core register)
+ // Encoding T1 / A1 Advanced SIMD
// vdup<c>.<size> <Qd>, <Rt> vdup<c>.<size> <Dd>, <Rt>
- // 1 1 1 0 1 1 1 0 1 b_1_6_6 Q_1_5_5 0 Vd_1_3_0 Rt_0_15_12 1 0 1 1 D_1_6_6 0 e_0_5_5 1 (0)(0)(0)(0)
- // 111011101xx0xxxxxxxx1011x0x1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 111011101xx0xxxxxxxx1011x0x1(0)(0)(0)(0)
new OpcodeARM(Index.thumb2_vdup__reg, "vdup", "111011101xx0xxxxxxxx1011x0x1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.305 VEXT
+ // Encoding T1 / A1 Advanced SIMD
// vext<c>.8 <Qd>, <Qn>, <Qm>, #<imm> vext<c>.8 <Dd>, <Dn>, <Dm>, #<imm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 1 1 Vn_1_3_0 Vd_0_15_12 imm4_0_11_8 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011111x11xxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.thumb2_vext, "vext.8", "111011111x11xxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.306 VHADD, VHSUB
+ // Encoding T1 / A1 Advanced SIMD
// vh<op><c> <Qd>, <Qn>, <Qm> vh<op><c> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 op_0_9_9 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx00x0xxx0xxxx
new OpcodeARM(Index.thumb2_vhadd_vhsub, "vh", "111x11110xxxxxxxxxxx00x0xxx0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.320 VLDR
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vldr<c> <Dd>, [<Rn>{, #+/-<imm>}] vldr<c> <Dd>, <label> vldr<c> <Dd>, [pc,#-0] Special case
- // 1 1 1 0 1 1 0 1 U_1_7_7 D_1_6_6 0 1 Rn_1_3_0 Vd_0_15_12 1 0 1 1 imm8_0_7_0
- // 11101101xx01xxxxxxxx1011xxxxxxxx
- // must precede thumb2_vldm__64 in search table
+ // must precede thumb2_vldm__64 in table
new OpcodeARM(Index.thumb2_vldr__64, "vldr", "11101101xx01xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.354 VPOP
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vpop <list> <list> is consecutive 64-bit registers
- // 1 1 1 0 1 1 0 0 1 D_1_6_6 1 1 1 1 0 1 Vd_0_15_12 1 0 1 1 imm8_0_7_0
- // 111011001x111101xxxx1011xxxxxxxx
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3
// A8.6.354 VPOP
+ // Encoding T2 / A2 VFPv2, VFPv3
// vpop <list> <list> is consecutive 32-bit registers
- // 1 1 1 0 1 1 0 0 1 D_1_6_6 1 1 1 1 0 1 Vd_0_15_12 1 0 1 0 imm8_0_7_0
- // 111011001x111101xxxx1010xxxxxxxx
- // must precede thumb2_vldm__32 in search table
- // must precede thumb2_vldm__64 in search table
-// new OpcodeARM(Index.thumb2_vpop_1, "vpop", "111011001x111101xxxx1011xxxxxxxx"),
-// new OpcodeARM(Index.thumb2_vpop_2, "vpop", "111011001x111101xxxx1010xxxxxxxx"),
- new OpcodeARM(Index.thumb2_vpop, "vpop", "111011001x111101xxxx101xxxxxxxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
+ // must precede thumb2_vldm__32 in table
+ // must precede thumb2_vldm__64 in table
+ new OpcodeARM(Index.thumb2_vpop, "vpop", "111011001x111101xxxx101xxxxxxxxx"),
// A8.6.332 VMOV (between two ARM core registers and a doubleword extension register)
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vmov<c> <Dm>, <Rt>, <Rt2> vmov<c> <Rt>, <Rt2>, <Dm>
- // 1 1 1 0 1 1 0 0 0 1 0 op_1_4_4 Rt2_1_3_0 Rt_0_15_12 1 0 1 1 0 0 M_0_5_5 1 Vm_0_3_0
- // 11101100010xxxxxxxxx101100x1xxxx
- // must precede thumb2_vldm_32 in search table
- // must precede thumb2_vldm_64 in search table
+ // must precede thumb2_vldm_32 in table
+ // must precede thumb2_vldm_64 in table
new OpcodeARM(Index.thumb2_vmov_9, "vmov", "11101100010xxxxxxxxx101100x1xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.319 VLDM
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vldm{mode}<c> <Rn>{!}, <list> <list> is consecutive 64-bit registers
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 1 Rn_1_3_0 Vd_0_15_12 1 0 1 1 imm8_0_7_0
- // 1110110xxxx1xxxxxxxx1011xxxxxxxx
- // must follow thumb2_vldr_1 in search table
- // must follow thumb2_vpop in search table
- // must follow thumb2_vmov_9
+ // must follow thumb2_vldr_1 in table
+ // must follow thumb2_vpop in table
+ // must follow thumb2_vmov_9 in table
new OpcodeARM(Index.thumb2_vldm__64, "vldm", "1110110xxxx1xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3
// A8.6.320 VLDR
+ // Encoding T2 / A2 VFPv2, VFPv3
// vldr<c> <Sd>, [<Rn>{, #+/-<imm>}] vldr<c> <Sd>, <label> vldr<c> <Sd>, [pc,#-0] Special case
- // 1 1 1 0 1 1 0 1 U_1_7_7 D_1_6_6 0 1 Rn_1_3_0 Vd_0_15_12 1 0 1 0 imm8_0_7_0
- // 11101101xx01xxxxxxxx1010xxxxxxxx
- // must precede thumb2_vldm__32 in search table
+ // must precede thumb2_vldm__32 in table
new OpcodeARM(Index.thumb2_vldr__32, "vldr", "11101101xx01xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3
// A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
+ // Encoding T1 / A1 VFPv2, VFPv3
// vmov<c> <Sm>, <Sm1>, <Rt>, <Rt2> vmov<c> <Rt>, <Rt2>, <Sm>, <Sm1>
- // 1 1 1 0 1 1 0 0 0 1 0 op_1_4_4 Rt2_1_3_0 Rt_0_15_12 1 0 1 0 0 0 M_0_5_5 1 Vm_0_3_0
- // 11101100010xxxxxxxxx101000x1xxxx
- // must precede thumb2_vldm__32 in search table
+ // must precede thumb2_vldm__32 in table
new OpcodeARM(Index.thumb2_vmov_8, "vmov", "11101100010xxxxxxxxx101000x1xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3
// A8.6.319 VLDM
+ // Encoding T2 / A2 VFPv2, VFPv3
// vldm{mode}<c> <Rn>{!}, <list> <list> is consecutive 32-bit registers
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 1 Rn_1_3_0 Vd_0_15_12 1 0 1 0 imm8_0_7_0
- // 1110110xxxx1xxxxxxxx1010xxxxxxxx
- // must follow thumb2_vldr__32 in search table
- // must follow thumb2_vpop in search table
- // must follow thumb2_vmov_8
+ // must follow thumb2_vldr__32 in table
+ // must follow thumb2_vpop in table
+ // must follow thumb2_vmov_8 in table
new OpcodeARM(Index.thumb2_vldm__32, "vldm", "1110110xxxx1xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.321 VMAX, VMIN (integer)
- // vmax<c>.<dt> <Qd>, <Qn>, <Qm> vmax<c>.<dt> <Dd>, <Dn>, <Dm> vmin<c>.<dt> <Qd>, <Qn>, <Qm> vmin<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 op_0_4_4 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0110xxxxxxxx
+ // Encoding T1 / A1 Advanced SIMD
+ // vmax<c>.<dt> <Qd>, <Qn>, <Qm> vmax<c>.<dt> <Dd>, <Dn>, <Dm>
+ // vmin<c>.<dt> <Qd>, <Qn>, <Qm> vmin<c>.<dt> <Dd>, <Dn>, <Dm>
new OpcodeARM(Index.thumb2_vmax_vmin__int, "v", "111x11110xxxxxxxxxxx0110xxxxxxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.322 VMAX, VMIN (floating-point)
- // vmax<c>.f32 <Qd>, <Qn>, <Qm> vmax<c>.f32 <Dd>, <Dn>, <Dm> vmin<c>.f32 <Qd>, <Qn>, <Qm> vmin<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 op_1_5_5 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011110xxxxxxxxxxx1111xxx0xxxx
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
+ // vmax<c>.f32 <Qd>, <Qn>, <Qm> vmax<c>.f32 <Dd>, <Dn>, <Dm>
+ // vmin<c>.f32 <Qd>, <Qn>, <Qm> vmin<c>.f32 <Dd>, <Dn>, <Dm>
new OpcodeARM(Index.thumb2_vmax_vmin__fp, "v", "111011110xxxxxxxxxxx1111xxx0xxxx"),
- // NEW - Encoding T1 / A1 (op) Advanced SIMD
// A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
+ // Encoding T1 / A1 Advanced SIMD
// v<op><c>.<dt> <Qd>, <Qn>, <Qm> v<op><c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 op_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx1001xxx0xxxx
new OpcodeARM(Index.thumb2_vml__int, "vml", "111x11110xxxxxxxxxxx1001xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.406 VTBL, VTBX
+ // Encoding T1 / A1 Advanced SIMD
// v<op><c>.8 <Dd>, <list>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 Vn_1_3_0 Vd_0_15_12 1 0 len_0_9_8 N_0_7_7 op_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xxxxxxxx10xxxxx0xxxx
- // must precede thumb2_vml__int_long
+ // must precede thumb2_vml__int_long in table
new OpcodeARM(Index.thumb2_vtb, "vtb", "111111111x11xxxxxxxx10xxxxx0xxxx"),
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
// A8.6.323 VMLA, VMLAL, VMLS, VMLSL (integer)
+ // Encoding T2 / A2 Advanced SIMD
// v<op>l<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 op_0_9_9 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx10x0x0x0xxxx
- // must follow thumb2_vtb
+ // must follow thumb2_vtb in table
new OpcodeARM(Index.thumb2_vml__int_long, "vml", "111x11111xxxxxxxxxxx10x0x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.324 VMLA, VMLS (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// v<op><c>.f32 <Qd>, <Qn>, <Qm> v<op><c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 op_1_5_5 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110xxxxxxxxxxx1101xxx1xxxx
new OpcodeARM(Index.thumb2_vml__f32, "vml", "111011110xxxxxxxxxxx1101xxx1xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.324 VMLA, VMLS (floating-point)
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// v<op><c>.f64 <Dd>, <Dn>, <Dm> v<op><c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 0 0 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 op_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011100x00xxxxxxxx101xxxx0xxxx
new OpcodeARM(Index.thumb2_vml__fp, "vml", "111011100x00xxxxxxxx101xxxx0xxxx"),
-
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
- // A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 1 0 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0x10x1x0xxxx
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.277 VBIC (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vbic<c>.<dt> <Qd>, #<imm> vbic<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 1 1 imm4_0_3_0
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.326 VMOV (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vmov<c>.<dt> <Qd>, #<imm> vmov<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 op_0_5_5 1 imm4_0_3_0
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.346 VORR (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vorr<c>.<dt> <Qd>, #<imm> vorr<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 0 1 imm4_0_3_0
- // NEW - Encoding T1 / A1 (i) Advanced SIMD
// A8.6.340 VMVN (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vmvn<c>.<dt> <Qd>, #<imm> vmvn<c>.<dt> <Dd>, #<imm>
- // 1 1 1 i_1_12_12 1 1 1 1 1 D_1_6_6 0 0 0 imm3_1_2_0 Vd_0_15_12 cmode_0_11_8 0 Q_0_6_6 1 1 imm4_0_3_0
//
- // 111x11111x000xxxxxxxxxxx0x11xxxx
- // 111x11111x000xxxxxxxxxxx0x01xxxx
- // 111x11111x000xxxxxxxxxxx0x11xxxx
- // 111x11111x000xxxxxxxxxxx0xx1xxxx
- // must follow thumb2_vorr__imm in search table
+ // must follow thumb2_vorr__imm in table
new OpcodeARM(Index.thumb2_vmov_vbitwise, null, "111x11111x000xxxxxxxxxxx0xx1xxxx"),
-
- // NEW - Encoding T2 / A2 (cond) VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.326 VMOV (immediate)
+ // Encoding T2 / A2 VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vmov<c>.f64 <Dd>, #<imm> vmov<c>.f32 <Sd>, #<imm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 imm4H_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 (0) 0 (0) 0 imm4L_0_3_0
- // 111011101x11xxxxxxxx101x(0)0(0)0xxxx
+ // Unpredictable if (0) is 1: 111011101x11xxxxxxxx101x(0)0(0)0xxxx
new OpcodeARM(Index.thumb2_vmov__imm, "vmov", "111011101x11xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
- // A8.6.347 VORR (register)
- // vorr<c> <Qd>, <Qn>, <Qm> vorr<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 1 0 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x10xxxxxxxx0001xxx1xxxx
- // must precede thumb2_vmov__reg
- new OpcodeARM(Index.thumb2_vorr__reg, "vorr", "111011110x10xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.327 VMOV (register)
+ // Encoding T1 / A1 Advanced SIMD
// vmov<c> <Qd>, <Qm> vmov<c> <Dd>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 1 0 Vm_1_3_0 Vd_0_15_12 0 0 0 1 M_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x10xxxxxxxx0001xxx1xxxx
- // must follow thumb2_vorr__reg
- new OpcodeARM(Index.thumb2_vmov__reg, "vmov", "111011110x10xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
+ // A8.6.347 VORR (register)
+ // Encoding T1 / A1 Advanced SIMD
+ // vorr<c> <Qd>, <Qn>, <Qm> vorr<c> <Dd>, <Dn>, <Dm>
+ //
+ new OpcodeARM(Index.thumb2_vmov_vorr, "vmov", "111011110x10xxxxxxxx0001xxx1xxxx"),
// A8.6.327 VMOV (register)
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vmov<c>.f64 <Dd>, <Dm> vmov<c>.f32 <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 0 0 0 Vd_0_15_12 1 0 1 sz_0_8_8 0 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x110000xxxx101x01x0xxxx
new OpcodeARM(Index.thumb2_vmov__reg_f, "vmov", "111011101x110000xxxx101x01x0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD if opc1 == ’0x’ && opc2 == '00'; Advanced SIMD otherwise
// A8.6.328 VMOV (ARM core register to scalar)
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD for word version (opc1:opc2 == '0x00')'; Advanced SIMD otherwise
// vmov<c>.<size> <Dd[x]>, <Rt>
- // 1 1 1 0 1 1 1 0 0 opc1_1_6_5 0 Vd_1_3_0 Rt_0_15_12 1 0 1 1 D_0_7_7 opc2_0_6_5 1 (0)(0)(0)(0)
- // 111011100xx0xxxxxxxx1011xxx1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 111011100xx0xxxxxxxx1011xxx1(0)(0)(0)(0)
new OpcodeARM(Index.thumb2_vmov_5, "vmov", "111011100xx0xxxxxxxx1011xxx1xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD if opc1 == '0x' && opc2 == '00';Advanced SIMD otherwise
// A8.6.329 VMOV (scalar to ARM core register)
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD for word version (U:opc1:opc2 == '00x00'); Advanced SIMD otherwise
// vmov<c>.<dt> <Rt>, <Dn[x]>
- // 1 1 1 0 1 1 1 0 U_1_7_7 opc1_1_6_5 1 Vn_1_3_0 Rt_0_15_12 1 0 1 1 N_0_7_7 opc2_0_6_5 1 (0)(0)(0)(0)
- // 11101110xxx1xxxxxxxx1011xxx1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 11101110xxx1xxxxxxxx1011xxx1(0)(0)(0)(0)
new OpcodeARM(Index.thumb2_vmov_6, "vmov", "11101110xxx1xxxxxxxx1011xxx1xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3
// A8.6.330 VMOV (between ARM core register and single-precision register)
+ // Encoding T1 / A1 VFPv2, VFPv3
// vmov<c> <Sn>, <Rt> vmov<c> <Rt>, <Sn>
- // 1 1 1 0 1 1 1 0 0 0 0 op_1_4_4 Vn_1_3_0 Rt_0_15_12 1 0 1 0 N_0_7_7 (0)(0) 1 (0)(0)(0)(0)
- // 11101110000xxxxxxxxx1010x(0)(0)1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 11101110000xxxxxxxxx1010x(0)(0)1(0)(0)(0)(0)
new OpcodeARM(Index.thumb2_vmov_7, "vmov", "11101110000xxxxxxxxx1010xxx1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.333 VMOVL
+ // Encoding T1 / A1 Advanced SIMD
// vmovl<c>.<dt> <Qd>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm3_5_3 0 0 0 Vd_0_15_12 1 0 1 0 0 0 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxx000xxxx101000x1xxxx
- // must precede thumb2_vshll__various in search table
+ // must precede thumb2_vshll__various in table
new OpcodeARM(Index.thumb2_vmovl, "vmovl", "111x11111xxxx000xxxx101000x1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.384 VSHLL
+ // Encoding T1 / A1 Advanced SIMD
// vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (0 < <imm> < <size>)
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 1 0 1 0 0 0 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx101000x1xxxx
- // must follow thumb2_vmovl in search table
+ // must follow thumb2_vmovl in table
new OpcodeARM(Index.thumb2_vshll__various, "vshll", "111x11111xxxxxxxxxxx101000x1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.334 VMOVN
+ // Encoding T1 / A1 Advanced SIMD
// vmovn<c>.<dt> <Dd>, <Qm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 1 0 0 0 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx001000x0xxxx
- // must precede thumb2_vqmov in search table
+ // must precede thumb2_vqmov in table
new OpcodeARM(Index.thumb2_vmovn, "vmovn", "111111111x11xx10xxxx001000x0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.335 VMRS
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vmrs<c> <Rt>, fpscr
- // 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 Rt_0_15_12 1 0 1 0 0 (0)(0) 1 (0)(0)(0)(0)
- // 1110111011110001xxxx10100(0)(0)1(0)(0)(0)(0)
- // NEW - Encoding T1 /A1 (cond) VFPv2, VFPv3, Advanced SIMD
+ // Unpredictable if (0) is 1: 1110111011110001xxxx10100(0)(0)1(0)(0)(0)(0)
// B6.1.14 VMRS
+ // Encoding T1 /A1 (cond) VFPv2, VFPv3, Advanced SIMD
// vmrs<c> <Rt>,<spec_reg>
- // 1 1 1 0 1 1 1 0 1 1 1 1 reg_1_3_0 Rt_0_15_12 1 0 1 0 (0)(0)(0) 1 (0)(0)(0)(0)
- // 111011101111xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 111011101111xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ //
new OpcodeARM(Index.thumb2_vmrs, "vmrs", "111011101111xxxxxxxx10100xx1xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.336 VMSR
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vmsr<c> fpscr, <Rt>
- // 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 Rt_0_15_12 1 0 1 0 0 (0)(0) 1 (0)(0)(0)(0)
- // 1110111011100001xxxx10100(0)(0)1(0)(0)(0)(0)
- // NEW - Encoding T1 /A1 (cond) VFPv2, VFPv3, Advanced SIMD
+ // Unpredictable if (0) is 1: 1110111011100001xxxx10100(0)(0)1(0)(0)(0)(0)
// B6.1.15 VMSR
+ // Encoding T1 /A1 (cond) VFPv2, VFPv3, Advanced SIMD
// vmsr<c> <spec_reg>,<Rt>
- // 1 1 1 0 1 1 1 0 1 1 1 0 reg_1_3_0 Rt_0_15_12 1 0 1 0 (0)(0)(0) 1 (0)(0)(0)(0)
- // 111011101110xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ // Unpredictable if (0) is 1: 111011101110xxxxxxxx1010(0)(0)(0)1(0)(0)(0)(0)
+ //
new OpcodeARM(Index.thumb2_vmsr, "vmsr", "111011101110xxxxxxxx10100xx1xxxx"),
- // NEW - Encoding T1 / A1 (op) Advanced SIMD
// A8.6.337 VMUL, VMULL (integer and polynomial)
+ // Encoding T1 / A1 Advanced SIMD
// vmul<c>.<dt> <Qd>, <Qn>, <Qm> vmul<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 op_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx1001xxx1xxxx
new OpcodeARM(Index.thumb2_vmul_1, "vmul", "111x11110xxxxxxxxxxx1001xxx1xxxx"),
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
// A8.6.337 VMUL, VMULL (integer and polynomial)
+ // Encoding T2 / A2 Advanced SIMD
// vmull<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 1 op_0_9_9 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx11x0x0x0xxxx
new OpcodeARM(Index.thumb2_vmull, "vmull", "111x11111xxxxxxxxxxx11x0x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.338 VMUL (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vmul<c>.f32 <Qd>, <Qn>, <Qm> vmul<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 0 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111111110x0xxxxxxxxx1101xxx1xxxx
new OpcodeARM(Index.thumb2_vmul__f32, "vmul", "111111110x0xxxxxxxxx1101xxx1xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.338 VMUL (floating-point)
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vmul<c>.f64 <Dd>, <Dn>, <Dm> vmul<c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 1 0 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011100x10xxxxxxxx101xx0x0xxxx
new OpcodeARM(Index.thumb2_vmul__fp_2, "vmul", "111011100x10xxxxxxxx101xx0x0xxxx"),
- // NEW - Encoding T2 / A2 Advanced SIMD
// A8.6.360 VQDMULL
+ // Encoding T2 / A2 Advanced SIMD
// vqdmull<c>.<dt> <Qd>,<Dn>,<Dm[x]>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 1 1 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011111xxxxxxxxxxx1011x1x0xxxx
- // must precede thumb2_vmul__scalar
+ // must precede thumb2_vmul__scalar in table
new OpcodeARM(Index.thumb2_vqdmull__scalar, "vqdmul", "111011111xxxxxxxxxxx1011x1x0xxxx"),
- // NEW - Encoding T1 / A1 (Q) Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.339 VMUL, VMULL (by scalar)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vmul<c>.<dt> <Qd>, <Qn>, <Dm[x]> vmul<c>.<dt> <Dd>, <Dn>, <Dm[x]>
- // 1 1 1 Q_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 F_0_8_8 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx100xx1x0xxxx
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
// A8.6.339 VMUL, VMULL (by scalar)
+ // Encoding T2 / A2 Advanced SIMD
// vmull<c>.<dt> <Qd>, <Dn>, <Dm[x]>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 1 0 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx1010x1x0xxxx
- // must follow thumb2_vqdmull__scalar
- new OpcodeARM(Index.thumb2_vmul__scalar, "vmul", "111x11111xxxxxxxxxxx10xxx1x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
+ // must follow thumb2_vqdmull__scalar in table
+ //
+ new OpcodeARM(Index.thumb2_vmul__scalar, "vmul", "111x11111xxxxxxxxxxx10xxx1x0xxxx"),
// A8.6.341 VMVN (register)
+ // Encoding T1 / A1 Advanced SIMD
// vmvn<c> <Qd>, <Qm> vmvn<c> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 0 1 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx01011xx0xxxx
new OpcodeARM(Index.thumb2_vmvn, "vmvn", "111111111x11xx00xxxx01011xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.342 VNEG
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vneg<c>.<dt> <Qd>, <Qm> vneg<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 1 Vd_0_15_12 0 F_0_10_10 1 1 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx01xxxx0x111xx0xxxx
new OpcodeARM(Index.thumb2_vneg, "vneg", "111111111x11xx01xxxx0x111xx0xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.342 VNEG
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vneg<c>.f64 <Dd>, <Dm> vneg<c>.f32 <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 0 0 1 Vd_0_15_12 1 0 1 sz_0_8_8 0 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x110001xxxx101x01x0xxxx
new OpcodeARM(Index.thumb2_vneg__f, "vneg", "111011101x110001xxxx101x01x0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.343 VNMLA, VNMLS, VNMUL
- // vnmla<c>.f64 <Dd>, <Dn>, <Dm> vnmla<c>.f32 <Sd>, <Sn>, <Sm> vnmls<c>.f64 <Dd>, <Dn>, <Dm> vnmls<c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 0 1 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 op_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011100x01xxxxxxxx101xxxx0xxxx
+ // Encoding T1 / A1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
+ // vnmla<c>.f64 <Dd>, <Dn>, <Dm> vnmla<c>.f32 <Sd>, <Sn>, <Sm>
+ // vnmls<c>.f64 <Dd>, <Dn>, <Dm> vnmls<c>.f32 <Sd>, <Sn>, <Sm>
new OpcodeARM(Index.thumb2_vnml, "vnml", "111011100x01xxxxxxxx101xxxx0xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.343 VNMLA, VNMLS, VNMUL
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vnmul<c>.f64 <Dd>, <Dn>, <Dm> vnmul<c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 1 0 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011100x10xxxxxxxx101xx1x0xxxx
new OpcodeARM(Index.thumb2_vnmul, "vnmul", "111011100x10xxxxxxxx101xx1x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.345 VORN (register)
+ // Encoding T1 / A1 Advanced SIMD
// vorn<c> <Qd>, <Qn>, <Qm> vorn<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 1 1 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x11xxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.thumb2_vorn, "vorn", "111011110x11xxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.348 VPADAL
+ // Encoding T1 / A1 Advanced SIMD
// vpadal<c>.<dt> <Qd>, <Qm> vpadal<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 1 0 op_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx0110xxx0xxxx
new OpcodeARM(Index.thumb2_vpadal, "vpadal", "111111111x11xx00xxxx0110xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.349 VPADD (integer)
+ // Encoding T1 / A1 Advanced SIMD
// vpadd<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110xxxxxxxxxxx1011xxx1xxxx
new OpcodeARM(Index.thumb2_vpadd__int, "vpadd", "111011110xxxxxxxxxxx1011xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.350 VPADD (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vpadd<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 0 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110x0xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.thumb2_vpadd__f32, "vpadd", "111111110x0xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.351 VPADDL
+ // Encoding T1 / A1 Advanced SIMD
// vpaddl<c>.<dt> <Qd>, <Qm> vpaddl<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 0 1 0 op_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx0010xxx0xxxx
new OpcodeARM(Index.thumb2_vpaddl, "vpaddl", "111111111x11xx00xxxx0010xxx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.352 VPMAX, VPMIN (integer)
+ // Encoding T1 / A1 Advanced SIMD
// vp<op><c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 op_0_4_4 Vm_0_3_0
- // 111x11110xxxxxxxxxxx1010xxxxxxxx
new OpcodeARM(Index.thumb2_vpmax_vpmin__int, "vp", "111x11110xxxxxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.353 VPMAX, VPMIN (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vp<op><c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 op_1_5_5 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110xxxxxxxxxxx1111xxx0xxxx
new OpcodeARM(Index.thumb2_vpmax_vpmin__fp, "vp", "111111110xxxxxxxxxxx1111xxx0xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.355 VPUSH
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vpush<c> <list> <list> is consecutive 64-bit registers
- // 1 1 1 0 1 1 0 1 0 D_1_6_6 1 0 1 1 0 1 Vd_0_15_12 1 0 1 1 imm8_0_7_0
- // 111011010x101101xxxx1011xxxxxxxx
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3
// A8.6.355 VPUSH
+ // Encoding T2 / A2 VFPv2, VFPv3
// vpush<c> <list> <list> is consecutive 32-bit registers
- // 1 1 1 0 1 1 0 1 0 D_1_6_6 1 0 1 1 0 1 Vd_0_15_12 1 0 1 0 imm8_0_7_0
- // 111011010x101101xxxx1010xxxxxxxx
- // must precede thumb2_vstm_1 in search table
-// new OpcodeARM(Index.thumb2_vpush_1, "vpush", "111011010x101101xxxx1011xxxxxxxx"),
-// new OpcodeARM(Index.thumb2_vpush_2, "vpush", "111011010x101101xxxx1010xxxxxxxx"),
- new OpcodeARM(Index.thumb2_vpush, "vpush", "111011010x101101xxxx101xxxxxxxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
+ // must precede thumb2_vstm_1 in table
+ new OpcodeARM(Index.thumb2_vpush, "vpush", "111011010x101101xxxx101xxxxxxxxx"),
// A8.6.356 VQABS
+ // Encoding T1 / A1 Advanced SIMD
// vqabs<c>.<dt> <Qd>,<Qm> vqabs<c>.<dt> <Dd>,<Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 1 1 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx01110xx0xxxx
- // must precede thumb2_vstm_2 in search table
- // must precede thumb2_vabdl
+ // must precede thumb2_vstm_2 in table
+ // must precede thumb2_vabdl in table
new OpcodeARM(Index.thumb2_vqabs, "vqabs", "111111111x11xx00xxxx01110xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.362 VQNEG
+ // Encoding T1 / A1 Advanced SIMD
// vqneg<c>.<dt> <Qd>,<Qm> vqneg<c>.<dt> <Dd>,<Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 1 1 1 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx01111xx0xxxx
- // must precede thumb2_vabdl
+ // must precede thumb2_vabdl in table
new OpcodeARM(Index.thumb2_vqneg, "vqneg", "111111111x11xx00xxxx01111xx0xxxx"),
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
// A8.6.267 VABD, VABDL (integer)
+ // Encoding T2 / A2 Advanced SIMD
// vabdl<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 1 1 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0111x0x0xxxx
- // must follow thumb2_vabs
- // must follow thumb2_vqabs
- // must follow thumb2_vqneg
+ // must follow thumb2_vabs in table
+ // must follow thumb2_vqabs in table
+ // must follow thumb2_vqneg in table
new OpcodeARM(Index.thumb2_vabdl, "vabdl", "111x11111xxxxxxxxxxx0111x0x0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.357 VQADD
+ // Encoding T1 / A1 Advanced SIMD
// vqadd<c>.<dt> <Qd>,<Qn>,<Qm> vqadd<c>.<dt> <Dd>,<Dn>,<Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0000xxx1xxxx
new OpcodeARM(Index.thumb2_vqadd, "vqadd", "111x11110xxxxxxxxxxx0000xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.358 VQDMLAL, VQDMLSL
+ // Encoding T1 / A1 Advanced SIMD
// vqd<op><c>.<dt> <Qd>,<Dn>,<Dm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 op_0_9_9 1 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011111xxxxxxxxxxx10x1x0x0xxxx
new OpcodeARM(Index.thumb2_vqdml__vec, "vqdml", "111011111xxxxxxxxxxx10x1x0x0xxxx"),
- // NEW - Encoding T2 / A2 Advanced SIMD
// A8.6.358 VQDMLAL, VQDMLSL
+ // Encoding T2 / A2 Advanced SIMD
// vqd<op><c>.<dt> <Qd>,<Dn>,<Dm[x]>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 1 1 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011111xxxxxxxxxxx0x11x1x0xxxx
new OpcodeARM(Index.thumb2_vqdml__scalar, "vqdml", "111011111xxxxxxxxxxx0x11x1x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.359 VQDMULH
+ // Encoding T1 / A1 Advanced SIMD
// vqdmulh<c>.<dt> <Qd>,<Qn>,<Qm> vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011110xxxxxxxxxxx1011xxx0xxxx
new OpcodeARM(Index.thumb2_vqdmulh__vec, "vqdmulh", "111011110xxxxxxxxxxx1011xxx0xxxx"),
- // NEW - Encoding T2 / A2 (Q) Advanced SIMD
// A8.6.359 VQDMULH
+ // Encoding T2 / A2 Advanced SIMD
// vqdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]> vqdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
- // 1 1 1 Q_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 1 0 0 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx1100x1x0xxxx
new OpcodeARM(Index.thumb2_vqdmulh__scalar, "vqdmulh", "111x11111xxxxxxxxxxx1100x1x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.360 VQDMULL
+ // Encoding T1 / A1 Advanced SIMD
// vqdmull<c>.<dt> <Qd>,<Dn>,<Dm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011111xxxxxxxxxxx1101x0x0xxxx
new OpcodeARM(Index.thumb2_vqdmull__vec, "vqdmull", "111011111xxxxxxxxxxx1101x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.361 VQMOVN, VQMOVUN
+ // Encoding T1 / A1 Advanced SIMD
// vqmov{u}n<c>.<type><size> <Dd>, <Qm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 1 0 op_0_7_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx0010xxx0xxxx
- // must follow thumb2_vmovn in search table
+ // must follow thumb2_vmovn in table
new OpcodeARM(Index.thumb2_vqmov, "vqmov", "111111111x11xx10xxxx0010xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.363 VQRDMULH
+ // Encoding T1 / A1 Advanced SIMD
// vqrdmulh<c>.<dt> <Qd>,<Qn>,<Qm> vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110xxxxxxxxxxx1011xxx0xxxx
new OpcodeARM(Index.thumb2_vqrdmulh__vec, "vqrdmulh", "111111110xxxxxxxxxxx1011xxx0xxxx"),
- // NEW - Encoding T2 / A2 (Q) Advanced SIMD
// A8.6.363 VQRDMULH
+ // Encoding T2 / A2 Advanced SIMD
// vqrdmulh<c>.<dt> <Qd>,<Qn>,<Dm[x]> vqrdmulh<c>.<dt> <Dd>,<Dn>,<Dm[x]>
- // 1 1 1 Q_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx1101x1x0xxxx
new OpcodeARM(Index.thumb2_vqrdmulh__scalar, "vqrdmulh", "111x11111xxxxxxxxxxx1101x1x0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.364 VQRSHL
+ // Encoding T1 / A1 Advanced SIMD
// vqrshl<c>.<type><size> <Qd>,<Qm>,<Qn> vqrshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0101xxx1xxxx
new OpcodeARM(Index.thumb2_vqrshl, "vqrshl", "111x11110xxxxxxxxxxx0101xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.377 VRSHRN
+ // Encoding T1 / A1 Advanced SIMD
// vrshrn<c>.i<size> <Dd>, <Qm>, #<imm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 1 0 0 0 0 1 M_0_5_5 1 Vm_0_3_0
- // 111011111xxxxxxxxxxx100001x1xxxx
- // must precede thumb2_vqrshr in search table
+ // must precede thumb2_vqrshr in table
new OpcodeARM(Index.thumb2_vrshrn, "vrshrn", "111011111xxxxxxxxxxx100001x1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.365 VQRSHRN, VQRSHRUN
+ // Encoding T1 / A1 Advanced SIMD
// vqrshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 1 0 0 op_0_8_8 0 1 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx100x01x1xxxx
- // must follow thumb2_vrshrn in search table
+ // must follow thumb2_vrshrn in table
new OpcodeARM(Index.thumb2_vqrshr, "vqrshr", "111x11111xxxxxxxxxxx100x01x1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.366 VQSHL (register)
+ // Encoding T1 / A1 Advanced SIMD
// vqshl<c>.<type><size> <Qd>,<Qm>,<Qn> vqshl<c>.<type><size> <Dd>,<Dm>,<Dn>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0100xxx1xxxx
new OpcodeARM(Index.thumb2_vqshl__reg, "vqshl", "111x11110xxxxxxxxxxx0100xxx1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.367 VQSHL, VQSHLU (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vqshl{u}<c>.<type><size> <Qd>,<Qm>,#<imm> vqshl{u}<c>.<type><size> <Dd>,<Dm>,#<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 1 1 op_0_8_8 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx011xxxx1xxxx
new OpcodeARM(Index.thumb2_vqshl__imm, "vqshl", "111x11111xxxxxxxxxxx011xxxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.386 VSHRN
+ // Encoding T1 / A1 Advanced SIMD
// vshrn<c>.i<size> <Dd>, <Qm>, #<imm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 1 0 0 0 0 0 M_0_5_5 1 Vm_0_3_0
- // 111011111xxxxxxxxxxx100000x1xxxx
- // must precede thumb2_vqshr in search table
+ // must precede thumb2_vqshr in table
new OpcodeARM(Index.thumb2_vshrn, "vshrn", "111011111xxxxxxxxxxx100000x1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.368 VQSHRN, VQSHRUN
+ // Encoding T1 / A1 Advanced SIMD
// vqshr{u}n<c>.<type><size> <Dd>,<Qm>,#<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 1 0 0 op_0_8_8 0 0 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx100x00x1xxxx
- // must follow thumb2_vshrn in search table
+ // must follow thumb2_vshrn in table
new OpcodeARM(Index.thumb2_vqshr, "vqshr", "111x11111xxxxxxxxxxx100x00x1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.369 VQSUB
+ // Encoding T1 / A1 Advanced SIMD
// vqsub<c>.<type><size> <Qd>, <Qn>, <Qm> vqsub<c>.<type><size> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 1 0 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0010xxx1xxxx
new OpcodeARM(Index.thumb2_vqsub, "vqsub", "111x11110xxxxxxxxxxx0010xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.371 VRECPE
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vrecpe<c>.<dt> <Qd>, <Qm> vrecpe<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 1 Vd_0_15_12 0 1 0 F_0_8_8 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx11xxxx010x0xx0xxxx
- // must precede thumb2_vraddhn
+ // must precede thumb2_vraddhn in table
new OpcodeARM(Index.thumb2_vrecpe, "vrecpe", "111111111x11xx11xxxx010x0xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.378 VRSQRTE
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// vrsqrte<c>.<dt> <Qd>, <Qm> vrsqrte<c>.<dt> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 1 Vd_0_15_12 0 1 0 F_0_8_8 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx11xxxx010x1xx0xxxx
- // must precede thumb2_vabal
- // must precede thumb2_vraddhn
+ // must precede thumb2_vabal in table
+ // must precede thumb2_vraddhn in table
new OpcodeARM(Index.thumb2_vrsqrte, "vrsqrte", "111111111x11xx11xxxx010x1xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.370 VRADDHN
+ // Encoding T1 / A1 Advanced SIMD
// vraddhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111111111xxxxxxxxxxx0100x0x0xxxx
- // must follow thumb2_vrecpe
- // must follow thumb2_vrsqrte
+ // must follow thumb2_vrecpe in table
+ // must follow thumb2_vrsqrte in table
new OpcodeARM(Index.thumb2_vraddhn, "vraddhn", "111111111xxxxxxxxxxx0100x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.372 VRECPS
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vrecps<c>.f32 <Qd>, <Qn>, <Qm> vrecps<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 0 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x0xxxxxxxxx1111xxx1xxxx
new OpcodeARM(Index.thumb2_vrecps, "vrecps", "111011110x0xxxxxxxxx1111xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.373 VREV16, VREV32, VREV64
+ // Encoding T1 / A1 Advanced SIMD
// vrev<n><c>.<size> <Qd>, <Qm> vrev<n><c>.<size> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 0 0 Vd_0_15_12 0 0 0 op_0_8_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx00xxxx000xxxx0xxxx
new OpcodeARM(Index.thumb2_vrev, "vrev", "111111111x11xx00xxxx000xxxx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.374 VRHADD
+ // Encoding T1 / A1 Advanced SIMD
// vrhadd<c> <Qd>, <Qn>, <Qm> vrhadd<c> <Dd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0001xxx0xxxx
new OpcodeARM(Index.thumb2_vrhadd, "vrhadd", "111x11110xxxxxxxxxxx0001xxx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.375 VRSHL
+ // Encoding T1 / A1 Advanced SIMD
// vrshl<c>.<type><size> <Qd>, <Qm>, <Qn> vrshl<c>.<type><size> <Dd>, <Dm>, <Dn>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0101xxx0xxxx
new OpcodeARM(Index.thumb2_vrshl, "vrshl", "111x11110xxxxxxxxxxx0101xxx0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.376 VRSHR
+ // Encoding T1 / A1 Advanced SIMD
// vrshr<c>.<type><size> <Qd>, <Qm>, #<imm> vrshr<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 0 1 0 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0010xxx1xxxx
new OpcodeARM(Index.thumb2_vrshr, "vrshr", "111x11111xxxxxxxxxxx0010xxx1xxxx"),
- // NEW - Encoding T2 / A2 (U) Advanced SIMD
// A8.6.266 VABA, VABAL
+ // Encoding T2 / A2 Advanced SIMD
// vabal<c>.<dt> <Qd>, <Dn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 1 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0101x0x0xxxx
- // must follow thumb2_vceq__imm0
- // must follow thumb2_vrsqrte
+ // must follow thumb2_vceq__imm0 in table
+ // must follow thumb2_vrsqrte in table
new OpcodeARM(Index.thumb2_vabal, "vabal", "111x11111xxxxxxxxxxx0101x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.379 VRSQRTS
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vrsqrts<c>.f32 <Qd>, <Qn>, <Qm> vrsqrts<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 1 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 1 1 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110x1xxxxxxxxx1111xxx1xxxx
new OpcodeARM(Index.thumb2_vrsqrts, "vrsqrts", "111011110x1xxxxxxxxx1111xxx1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.380 VRSRA
+ // Encoding T1 / A1 Advanced SIMD
// vrsra<c>.<type><size> <Qd>, <Qm>, #<imm> vrsra<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 0 1 1 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0011xxx1xxxx
new OpcodeARM(Index.thumb2_vrsra, "vrsra", "111x11111xxxxxxxxxxx0011xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.381 VRSUBHN
+ // Encoding T1 / A1 Advanced SIMD
// vrsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 1 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111111111xxxxxxxxxxx0110x0x0xxxx
new OpcodeARM(Index.thumb2_vrsubhn, "vrsubhn", "111111111xxxxxxxxxxx0110x0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.382 VSHL (immediate)
+ // Encoding T1 / A1 Advanced SIMD
// vshl<c>.i<size> <Qd>, <Qm>, #<imm> vshl<c>.i<size> <Dd>, <Dm>, #<imm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 1 0 1 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011111xxxxxxxxxxx0101xxx1xxxx
new OpcodeARM(Index.thumb2_vshl__imm, "vshl.i", "111011111xxxxxxxxxxx0101xxx1xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.383 VSHL (register)
+ // Encoding T1 / A1 Advanced SIMD
// vshl<c>.i<size> <Qd>, <Qm>, <Qn> vshl<c>.i<size> <Dd>, <Dm>, <Dn>
- // 1 1 1 U_1_12_12 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111x11110xxxxxxxxxxx0100xxx0xxxx
new OpcodeARM(Index.thumb2_vshl__reg, "vshl", "111x11110xxxxxxxxxxx0100xxx0xxxx"),
- // NEW - Encoding T2 / A2 Advanced SIMD
// A8.6.384 VSHLL
+ // Encoding T2 / A2 Advanced SIMD
// vshll<c>.<type><size> <Qd>, <Dm>, #<imm> (<imm> == <size>)
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 1 1 0 0 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx001100x0xxxx
new OpcodeARM(Index.thumb2_vshll__max, "vshll", "111111111x11xx10xxxx001100x0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.385 VSHR
+ // Encoding T1 / A1 Advanced SIMD
// vshr<c>.<type><size> <Qd>, <Qm>, #<imm> vshr<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 0 0 0 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0000xxx1xxxx
new OpcodeARM(Index.thumb2_vshr, "vshr", "111x11111xxxxxxxxxxx0000xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.387 VSLI
+ // Encoding T1 / A1 Advanced SIMD
// vsli<c>.<size> <Qd>, <Qm>, #<imm> vsli<c>.<size> <Dd>, <Dm>, #<imm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 1 0 1 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111111111xxxxxxxxxxx0101xxx1xxxx
new OpcodeARM(Index.thumb2_vsli, "vsli.", "111111111xxxxxxxxxxx0101xxx1xxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.388 VSQRT
+ // Encoding T1 / A1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vsqrt<c>.f64 <Dd>, <Dm> vsqrt<c>.f32 <Sd>, <Sm>
- // 1 1 1 0 1 1 1 0 1 D_1_6_6 1 1 0 0 0 1 Vd_0_15_12 1 0 1 sz_0_8_8 1 1 M_0_5_5 0 Vm_0_3_0
- // 111011101x110001xxxx101x11x0xxxx
new OpcodeARM(Index.thumb2_vsqrt, "vsqrt", "111011101x110001xxxx101x11x0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.389 VSRA
+ // Encoding T1 / A1 Advanced SIMD
// vsra<c>.<type><size> <Qd>, <Qm>, #<imm> vsra<c>.<type><size> <Dd>, <Dm>, #<imm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 0 0 1 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0001xxx1xxxx
new OpcodeARM(Index.thumb2_vsra, "vsra", "111x11111xxxxxxxxxxx0001xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.390 VSRI
+ // Encoding T1 / A1 Advanced SIMD
// vsri<c>.<size> <Qd>, <Qm>, #<imm> vsri<c>.<size> <Dd>, <Dm>, #<imm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 imm6_1_5_0 Vd_0_15_12 0 1 0 0 L_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111111111xxxxxxxxxxx0100xxx1xxxx
new OpcodeARM(Index.thumb2_vsri, "vsri.", "111111111xxxxxxxxxxx0100xxx1xxxx"),
-
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.400 VSTR
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vstr<c> <Dd>, [<Rn>{, #+/-<imm>}]
- // 1 1 1 0 1 1 0 1 U_1_7_7 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 1 0 1 1 imm8_0_7_0
- // 11101101xx00xxxxxxxx1011xxxxxxxx
- // must precede thumb2_vstm_1 in search table
+ // must precede thumb2_vstm_1 in table
new OpcodeARM(Index.thumb2_vstr__64, "vstr", "11101101xx00xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding T1 / A1 (cond) VFPv2, VFPv3, Advanced SIMD
// A8.6.399 VSTM
+ // Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
// vstm{mode}<c> <Rn>{!}, <list> <list> is consecutive 64-bit registers
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 0 Rn_1_3_0 Vd_0_15_12 1 0 1 1 imm8_0_7_0
- // 1110110xxxx0xxxxxxxx1011xxxxxxxx
- // must follow thumb2_vstr_1 in search table
+ // must follow thumb2_vstr_1 in table
new OpcodeARM(Index.thumb2_vstm__64, "vstm", "1110110xxxx0xxxxxxxx1011xxxxxxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3
// A8.6.400 VSTR
+ // Encoding T2 / A2 VFPv2, VFPv3
// vstr<c> <Sd>, [<Rn>{, #+/-<imm>}]
- // 1 1 1 0 1 1 0 1 U_1_7_7 D_1_6_6 0 0 Rn_1_3_0 Vd_0_15_12 1 0 1 0 imm8_0_7_0
- // 11101101xx00xxxxxxxx1010xxxxxxxx
- // must precede thumb2_vstm_2 in search table
+ // must precede thumb2_vstm_2 in table
new OpcodeARM(Index.thumb2_vstr__32, "vstr", "11101101xx00xxxxxxxx1010xxxxxxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3
// A8.6.399 VSTM
+ // Encoding T2 / A2 VFPv2, VFPv3
// vstm{mode}<c> <Rn>{!}, <list> <list> is consecutive 32-bit registers
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 0 Rn_1_3_0 Vd_0_15_12 1 0 1 0 imm8_0_7_0
- // 1110110xxxx0xxxxxxxx1010xxxxxxxx
- // must follow thumb2_vstr_1 in search table
+ // must follow thumb2_vstr_1 in table
new OpcodeARM(Index.thumb2_vstm__32, "vstm", "1110110xxxx0xxxxxxxx1010xxxxxxxx"),
-
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.401 VSUB (integer)
+ // Encoding T1 / A1 Advanced SIMD
// vsub<c>.<dt> <Qd>, <Qn>, <Qm> vsub<c>.<dt> <Dd>, <Dn>, <Dm>
- // 1 1 1 1 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111110xxxxxxxxxxx1000xxx0xxxx
new OpcodeARM(Index.thumb2_vsub__int, "vsub", "111111110xxxxxxxxxxx1000xxx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// A8.6.402 VSUB (floating-point)
+ // Encoding T1 / A1 Advanced SIMD (UNDEFINED in integer-only variant)
// vsub<c>.f32 <Qd>, <Qn>, <Qm> vsub<c>.f32 <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 1 sz_1_4_4 Vn_1_3_0 Vd_0_15_12 1 1 0 1 N_0_7_7 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111011110x1xxxxxxxxx1101xxx0xxxx
new OpcodeARM(Index.thumb2_vsub__f32, "vsub", "111011110x1xxxxxxxxx1101xxx0xxxx"),
- // NEW - Encoding T2 / A2 (cond) VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// A8.6.402 VSUB (floating-point)
+ // Encoding T2 / A2 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
// vsub<c>.f64 <Dd>, <Dn>, <Dm> vsub<c>.f32 <Sd>, <Sn>, <Sm>
- // 1 1 1 0 1 1 1 0 0 D_1_6_6 1 1 Vn_1_3_0 Vd_0_15_12 1 0 1 sz_0_8_8 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111011100x11xxxxxxxx101xx1x0xxxx
new OpcodeARM(Index.thumb2_vsub__fp_f, "vsub", "111011100x11xxxxxxxx101xx1x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.403 VSUBHN
+ // Encoding T1 / A1 Advanced SIMD
// vsubhn<c>.<dt> <Dd>, <Qn>, <Qm>
- // 1 1 1 0 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 1 1 0 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111011111xxxxxxxxxxx0110x0x0xxxx
new OpcodeARM(Index.thumb2_vsubhn, "vsubhn", "111011111xxxxxxxxxxx0110x0x0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.404 VSUBL, VSUBW
+ // Encoding T1 / A1 Advanced SIMD
// vsubl<c>.<dt> <Qd>, <Dn>, <Dm> vsubw<c>.<dt> {<Qd>,} <Qn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 1 op_0_8_8 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx001xx0x0xxxx
new OpcodeARM(Index.thumb2_vsubl_vsubw, "vsub", "111x11111xxxxxxxxxxx001xx0x0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.405 VSWP
+ // Encoding T1 / A1 Advanced SIMD
// vswp<c> <Qd>, <Qm> vswp<c> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 0 0 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx00000xx0xxxx
new OpcodeARM(Index.thumb2_vswp, "vswp", "111111111x11xx10xxxx00000xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.407 VTRN
+ // Encoding T1 / A1 Advanced SIMD
// vtrn<c>.<size> <Qd>, <Qm> vtrn<c>.<size> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 0 0 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx00001xx0xxxx
- // must precede thumb2_vaddl_vaddw
- // must precede thumb2_vml__scalar
+ // must precede thumb2_vaddl_vaddw in table
+ // must precede thumb2_vml__scalar in table
new OpcodeARM(Index.thumb2_vtrn, "vtrn", "111111111x11xx10xxxx00001xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.408 VTST
+ // Encoding T1 / A1 Advanced SIMD
// vtst<c>.<size> <Qd>, <Qn>, <Qm> vtst<c>.<size> <Dd>, <Dn>, <Dm>
- // 1 1 1 0 1 1 1 1 0 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 1 0 0 0 N_0_7_7 Q_0_6_6 M_0_5_5 1 Vm_0_3_0
- // 111011110xxxxxxxxxxx1000xxx1xxxx
new OpcodeARM(Index.thumb2_vtst, "vtst", "111011110xxxxxxxxxxx1000xxx1xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.409 VUZP
+ // Encoding T1 / A1 Advanced SIMD
// vuzp<c>.<size> <Qd>, <Qm> vuzp<c>.<size> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 0 1 0 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx00010xx0xxxx
- // must precede thumb2_vaddl_vaddw
- // must precede thumb2_vml__scalar
+ // must precede thumb2_vaddl_vaddw in table
+ // must precede thumb2_vml__scalar in table
new OpcodeARM(Index.thumb2_vuzp, "vuzp", "111111111x11xx10xxxx00010xx0xxxx"),
- // NEW - Encoding T1 / A1 Advanced SIMD
// A8.6.410 VZIP
+ // Encoding T1 / A1 Advanced SIMD
// vzip<c>.<size> <Qd>, <Qm> vzip<c>.<size> <Dd>, <Dm>
- // 1 1 1 1 1 1 1 1 1 D_1_6_6 1 1 size_1_3_2 1 0 Vd_0_15_12 0 0 0 1 1 Q_0_6_6 M_0_5_5 0 Vm_0_3_0
- // 111111111x11xx10xxxx00011xx0xxxx
- // must precede thumb2_vaddl_vaddw
- // must precede thumb2_vml__scalar
+ // must precede thumb2_vaddl_vaddw in table
+ // must precede thumb2_vml__scalar in table
new OpcodeARM(Index.thumb2_vzip, "vzip", "111111111x11xx10xxxx00011xx0xxxx"),
- // NEW - Encoding T1 / A1 (Q) Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar)
+ // Encoding T1 / A1 Advanced SIMD (F = 1 UNDEFINED in integer-only variants)
// v<op><c>.<dt> <Qd>, <Qn>, <Dm[x]> v<op><c>.<dt> <Dd>, <Dn>, <Dm[x]>
- // 1 1 1 Q_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 0 F_0_8_8 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
// v<op>l<c>.<dt> <Qd>, <Dn>, <Dm[x]>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 op_0_10_10 1 0 N_0_7_7 1 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx0xxxx1x0xxxx
- // must follow thumb2_vtrn
- // must follow thumb2_vuzp
- // must follow thumb2_vzip
+ // must follow thumb2_vtrn in table
+ // must follow thumb2_vuzp in table
+ // must follow thumb2_vzip in table
new OpcodeARM(Index.thumb2_vml__scalar, "vml", "111x11111xxxxxxxxxxx0xxxx1x0xxxx"),
- // NEW - Encoding T1 / A1 (U) Advanced SIMD
// A8.6.274 VADDL, VADDW
+ // Encoding T1 / A1 Advanced SIMD
// vaddl<c>.<dt> <Qd>, <Dn>, <Dm> vaddw<c>.<dt> <Qd>, <Qn>, <Dm>
- // 1 1 1 U_1_12_12 1 1 1 1 1 D_1_6_6 size_1_5_4 Vn_1_3_0 Vd_0_15_12 0 0 0 op_0_8_8 N_0_7_7 0 M_0_5_5 0 Vm_0_3_0
- // 111x11111xxxxxxxxxxx000xx0x0xxxx
- // must follow thumb2_vceq__imm0
- // must follow thumb2_vcge__imm0
- // must follow thumb2_vcgt__imm0
- // must follow thumb2_vcle
- // must follow thumb2_vtrn
- // must follow thumb2_vuzp
- // must follow thumb2_vzip
+ // must follow thumb2_vceq__imm0 in table
+ // must follow thumb2_vcge__imm0 in table
+ // must follow thumb2_vcgt__imm0 in table
+ // must follow thumb2_vcle in table
+ // must follow thumb2_vtrn in table
+ // must follow thumb2_vuzp in table
+ // must follow thumb2_vzip in table
new OpcodeARM(Index.thumb2_vaddl_vaddw, "vadd", "111x11111xxxxxxxxxxx000xx0x0xxxx"),
-
// Coprocessor Data Processing instructions
- // must follow VFP data processing instructions in search table
+ // must follow VFP data processing instructions in table
// (VMLA, VMLS, VNMLA, VNMLS, VNMUL, VMUL, VDIV, VMOV, VABS, VNEG
// VSQRT, VCVTB, VCVIT, VCMP, VCMPE, VCVT, VCVTR)
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
// A8.6.28 CDP, CDP2
+ // Encoding T1 / A1 ARMv6T2, ARMv7
// cdp<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- // 1 1 1 0 1 1 1 0 opc1_1_7_4 CRn_1_3_0 CRd_0_15_12 coproc_0_11_8 opc2_0_7_5 0 CRm_0_3_0
- // 11101110xxxxxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.thumb2_cdp, "cdp", "11101110xxxxxxxxxxxxxxxxxxx0xxxx"),
- // NEW - Encoding T2 /A2 ARMv6T2, ARMv7
// A8.6.28 CDP, CDP2
+ // Encoding T2 /A2 ARMv6T2, ARMv7
// cdp2<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- // 1 1 1 1 1 1 1 0 opc1_1_7_4 CRn_1_3_0 CRd_0_15_12 coproc_0_11_8 opc2_0_7_5 0 CRm_0_3_0
- // 11111110xxxxxxxxxxxxxxxxxxx0xxxx
new OpcodeARM(Index.thumb2_cdp2, "cdp2", "11111110xxxxxxxxxxxxxxxxxxx0xxxx"),
- // must follow VMOV 64-bit transfer between ARM core and extension registers
+ // must follow VMOV 64-bit transfer between ARM core and extension registers in table
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
// A8.6.92 MCR, MCR2
+ // Encoding T1 / A1 ARMv6T2, ARMv7
// mcr<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // 1 1 1 0 1 1 1 0 opc1_1_7_5 0 CRn_1_3_0 Rt_0_15_12 coproc_0_11_8 opc2_0_7_5 1 CRm_0_3_0
- // 11101110xxx0xxxxxxxxxxxxxxx1xxxx
- // NEW - Encoding T2 / A2 ARMv6T2, ARMv7
// A8.6.92 MCR, MCR2
+ // Encoding T2 / A2 ARMv6T2, ARMv7
// mcr2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // 1 1 1 1 1 1 1 0 opc1_1_7_5 0 CRn_1_3_0 Rt_0_15_12 coproc_0_11_8 opc2_0_7_5 1 CRm_0_3_0
- // 11111110xxx0xxxxxxxxxxxxxxx1xxxx
- new OpcodeARM(Index.thumb2_mcr, "mcr", "111x1110xxx0xxxxxxxxxxxxxxx1xxxx"),
-
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
- // A8.6.93 MCRR, MCRR2
- // mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- // 1 1 1 0 1 1 0 0 0 1 0 0 Rt2_1_3_0 Rt_0_15_12 coproc_0_11_8 opc1_0_7_4 CRm_0_3_0
- // 111011000100xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T2 / A2 ARMv6T2, ARMv7
- // A8.6.93 MCRR, MCRR2
- // mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- // 1 1 1 1 1 1 0 0 0 1 0 0 Rt2_1_3_0 Rt_0_15_12 coproc_0_11_8 opc1_0_7_4 CRm_0_3_0
- // 111111000100xxxxxxxxxxxxxxxxxxxx
- // must precede thumb2_stc
- new OpcodeARM(Index.thumb2_mcrr, "mcrr", "111x11000100xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
- // A8.6.188 STC, STC2
- // stc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> stc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 0 Rn_1_3_0 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
- // 1110110xxxx0xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T2 / A2 ARMv6T2, ARMv7
- // A8.6.188 STC, STC2
- // stc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> stc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // 1 1 1 1 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 0 Rn_1_3_0 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
- // 1111110xxxx0xxxxxxxxxxxxxxxxxxxx
- // must follow thumb2_mcrr
- // must follow thumb2_mcrr2
- // must follow thumb2_vstm__32
- new OpcodeARM(Index.thumb2_stc, "stc", "111x110xxxx0xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
- // A8.6.100 MRC, MRC2
- // mrc<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // 1 1 1 0 1 1 1 0 opc1_1_7_5 1 CRn_1_3_0 Rt_0_15_12 coproc_0_11_8 opc2_0_7_5 1 CRm_0_3_0
- // 11101110xxx1xxxxxxxxxxxxxxx1xxxx
- // NEW - Encoding T2 / A2 ARMv6T2, ARMv7
- // A8.6.100 MRC, MRC2
- // mrc2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
- // 1 1 1 1 1 1 1 0 opc1_1_7_5 1 CRn_1_3_0 Rt_0_15_12 coproc_0_11_8 opc2_0_7_5 1 CRm_0_3_0
- // 11111110xxx1xxxxxxxxxxxxxxx1xxxx
- new OpcodeARM(Index.thumb2_mrc, "mrc", "111x1110xxx1xxxxxxxxxxxxxxx1xxxx"),
-
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
- // A8.6.101 MRRC, MRRC2
- // mrrc<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
- // 1 1 1 0 1 1 0 0 0 1 0 1 Rt2_1_3_0 Rt_0_15_12 coproc_0_11_8 opc1_0_7_4 CRm_0_3_0
- // 111011000101xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T2 / A2 ARMv6T2, ARMv7
- // A8.6.101 MRRC, MRRC2
- // mrrc2<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
- // 1 1 1 1 1 1 0 0 0 1 0 1 Rt2_1_3_0 Rt_0_15_12 coproc_0_11_8 opc1_0_7_4 CRm_0_3_0
- // 111111000101xxxxxxxxxxxxxxxxxxxx
- // must precede thumb2_ldc in search table
- // must precede thumb2_ldc2 in search table
- new OpcodeARM(Index.thumb2_mrrc, "mrrc", "111x11000101xxxxxxxxxxxxxxxxxxxx"),
-
- // must follow thumb_mrrc in search table
- // NEW - Encoding T1 / A1 (cond) ARMv6T2, ARMv7
- // A8.6.51 LDC, LDC2 (immediate)
- // ldc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> ldc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 1 Rn_1_3_0 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
- // 1110110xxxx1xxxxxxxxxxxxxxxxxxxx
- // NEW - Encoding T1 /A1 (cond) ARMv6T2, ARMv7
- // A8.6.52 LDC, LDC2 (literal)
- // ldc{l}<c> <coproc>,<CRd>,<label> ldc{l}<c> <coproc>,<CRd>,[pc,#-0] Special case ldc{l}<c> <coproc>,<CRd>,[pc],<option>
- // 1 1 1 0 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 1 1 1 1 1 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
- // 1110110xxxx11111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 / A2 ARMv6T2, ARMv7
- // A8.6.52 LDC, LDC2 (literal)
- // ldc2{l}<c> <coproc>,<CRd>,<label> ldc2{l}<c> <coproc>,<CRd>,[pc,#-0] Special case ldc2{l}<c> <coproc>,<CRd>,[pc],<option>
- // 1 1 1 1 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 1 1 1 1 1 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
- // 1111110xxxx11111xxxxxxxxxxxxxxxx
- // NEW - Encoding T2 / A1 ARMv6T2, ARMv7
- // A8.6.51 LDC, LDC2 (immediate)
- // ldc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm> ldc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
- // 1 1 1 1 1 1 0 P_1_8_8 U_1_7_7 D_1_6_6 W_1_5_5 1 Rn_1_3_0 CRd_0_15_12 coproc_0_11_8 imm8_0_7_0
- // 1111110xxxx1xxxxxxxxxxxxxxxxxxxx
//
- // must follow thumb_mrrc2 in search table
- new OpcodeARM(Index.thumb2_ldc, "ldc", "111x110xxxx1xxxxxxxxxxxxxxxxxxxx"),
-
- // NEW - Encoding T1 ARMv6T2, ARMv7
+ new OpcodeARM(Index.thumb2_mcr, "mcr", "111x1110xxx0xxxxxxxxxxxxxxx1xxxx"),
+ // A8.6.93 MCRR, MCRR2
+ // Encoding T1 / A1 ARMv6T2, ARMv7
+ // mcrr<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ // A8.6.93 MCRR, MCRR2
+ // Encoding T2 / A2 ARMv6T2, ARMv7
+ // mcrr2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ // must precede thumb2_stc in table
+ //
+ new OpcodeARM(Index.thumb2_mcrr, "mcrr", "111x11000100xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.188 STC, STC2
+ // Encoding T1 / A1 ARMv6T2, ARMv7
+ // stc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // stc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // A8.6.188 STC, STC2
+ // Encoding T2 / A2 ARMv6T2, ARMv7
+ // stc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} stc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // stc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ //
+ // must follow thumb2_mcrr in table
+ // must follow thumb2_mcrr2 in table
+ // must follow thumb2_vstm__32 in table
+ new OpcodeARM(Index.thumb2_stc, "stc", "111x110xxxx0xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.100 MRC, MRC2
+ // Encoding T1 / A1 ARMv6T2, ARMv7
+ // mrc<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
+ // A8.6.100 MRC, MRC2
+ // Encoding T2 / A2 ARMv6T2, ARMv7
+ // mrc2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}
+ //
+ new OpcodeARM(Index.thumb2_mrc, "mrc", "111x1110xxx1xxxxxxxxxxxxxxx1xxxx"),
+ // A8.6.101 MRRC, MRRC2
+ // Encoding T1 / A1 ARMv6T2, ARMv7
+ // mrrc<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
+ // A8.6.101 MRRC, MRRC2
+ // Encoding T2 / A2 ARMv6T2, ARMv7
+ // mrrc2<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>
+ //
+ // must precede thumb2_ldc in table
+ new OpcodeARM(Index.thumb2_mrrc, "mrrc", "111x11000101xxxxxxxxxxxxxxxxxxxx"),
+ // A8.6.51 LDC, LDC2 (immediate)
+ // Encoding T1 / A1 ARMv6T2, ARMv7
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // ldc{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ // A8.6.52 LDC, LDC2 (literal)
+ // Encoding T1 /A1 (cond) ARMv6T2, ARMv7
+ // ldc{l}<c> <coproc>,<CRd>,<label> ldc{l}<c> <coproc>,<CRd>,[pc,#-0]
+ // Special case ldc{l}<c> <coproc>,<CRd>,[pc],<option>
+ // A8.6.52 LDC, LDC2 (literal)
+ // Encoding T2 / A2 ARMv6T2, ARMv7
+ // ldc2{l}<c> <coproc>,<CRd>,<label> ldc2{l}<c> <coproc>,<CRd>,[pc,#-0]
+ // Special case ldc2{l}<c> <coproc>,<CRd>,[pc],<option>
+ // A8.6.51 LDC, LDC2 (immediate)
+ // Encoding T2 / A1 ARMv6T2, ARMv7
+ // ldc2{l}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!} ldc2{l}<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>
+ // ldc2{l}<c> <coproc>,<CRd>,[<Rn>],<option>
+ //
+ // must follow thumb_mrrc in table
+ new OpcodeARM(Index.thumb2_ldc, "ldc", "111x110xxxx1xxxxxxxxxxxxxxxxxxxx"),
// B6.1.8 RFE
+ // Encoding T1 ARMv6T2, ARMv7
// rfedb<c> <Rn>{!} Outside or last in IT block
- // 1 1 1 0 1 0 0 0 0 0 W_1_5_5 1 Rn_1_3_0 (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
- // 1110100000x1xxxx(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
- // NEW - Encoding T2 ARMv6T2, ARMv7
+ // Unpredictable if (1) is 0 or (0) is 1: 1110100000x1xxxx(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
// B6.1.8 RFE
+ // Encoding T2 ARMv6T2, ARMv7
// rfe{ia}<c> <Rn>{!} Outside or last in IT block
- // 1 1 1 0 1 0 0 1 1 0 W_1_5_5 1 Rn_1_3_0 (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
- // 1110100000x1xxxx(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
- // 1110100110x1xxxx(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
+ // Unpredictable if (1) is 0 or (0) is 1: 1110100110x1xxxx(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)(0)
+ //
new OpcodeARM(Index.thumb2_rfe, "rfe", "1110100xx0x1xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding T1 ARMv6T2, ARMv7
// B6.1.10 SRS
+ // Encoding T1 ARMv6T2, ARMv7
// srsdb<c> sp{!},#<mode>
- // 1 1 1 0 1 0 0 0 0 0 W_1_5_5 0 (1)(1)(0) (1) (1) (1)(0)(0)(0)(0)(0)(0)(0)(0)(0) mode_0_4_0
- // 1110100000x0(1)(1)(0)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)xxxxx
-// see thumb2_srs
- // NEW - Encoding T2 ARMv6T2, ARMv7
+ // Unpredictable if (1) is 0 or (0) is 1: 1110100000x0(1)(1)(0)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)xxxxx
// B6.1.10 SRS
+ // Encoding T2 ARMv6T2, ARMv7
// srs{ia}<c> sp{!},#<mode>
- // 1 1 1 0 1 0 0 1 1 0 W_1_5_5 0 (1) (1) (0) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0) mode_0_4_0
- // 1110100110x0(1)(1)(0)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)xxxxx
+ // Unpredictable if (1) is 0 or (0) is 1: 1110100110x0(1)(1)(0)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)xxxxx
+ //
new OpcodeARM(Index.thumb2_srs, "srs", "1110100xx0x0xxxxxxxxxxxxxxxxxxxx"),
- // NEW - Encoding T1 ARMv6T2, ARMv7
// B6.1.13 SUBS PC, LR and related instructions
+ // Encoding T1 ARMv6T2, ARMv7
// subs<c> pc,lr,#<imm8> Outside or last in IT block
- // 1 1 1 1 0 0 1 1 1 1 0 1 (1)(1)(1) (0) 1 0 (0) 0 (1)(1)(1)(1) imm8_0_7_0
- // 111100111101(1)(1)(1)(0)10(0)0(1)(1)(1)(1)xxxxxxxx
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111101(1)(1)(1)(0)10(0)0(1)(1)(1)(1)xxxxxxxx
new OpcodeARM(Index.thumb2_subs, "subs", "111100111101xxxx10x0xxxxxxxxxxxx"),
};
+ // Reference manual citations (e.g., "A9.4.1") refer to sections in the ARM Architecture
+ // Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
public static final OpcodeARM thumbEE_opcode_table[] = {
- // NEW - Encoding T1 ThumbEE
// A9.4.1 LDR (register)
+ // Encoding T1 ThumbEE
// ldr<c> <Rt>,[<Rn>,<Rm>, lsl #2]
// 0 1 0 1 1 0 0 Rm Rn Rt
- // 0101100xxxxxxxxx
new OpcodeARM(Index.thumbEE_ldr_1, "ldr", "0101100xxxxxxxxx"),
- // NEW - Encoding T1 ThumbEE
// A9.4.2 LDRH (register)
+ // Encoding T1 ThumbEE
// ldrh<c> <Rt>,[<Rn>,<Rm>, lsl #1]
// 0 1 0 1 1 0 1 Rm Rn Rt
- // 0101101xxxxxxxxx
new OpcodeARM(Index.thumbEE_ldrh, "ldrh", "0101101xxxxxxxxx"),
- // NEW - Encoding T1 ThumbEE
// A9.4.3 LDRSH (register)
+ // Encoding T1 ThumbEE
// ldrsh<c> <Rt>,[<Rn>,<Rm>, lsl #1]
// 0 1 0 1 1 1 1 Rm Rn Rt
- // 0101111xxxxxxxxx
new OpcodeARM(Index.thumbEE_ldrsh, "ldrsh", "0101111xxxxxxxxx"),
- // NEW - Encoding T1 ThumbEE
// A9.4.4 STR (register)
+ // Encoding T1 ThumbEE
// str<c> <Rt>,[<Rn>,<Rm>, lsl #2]
// 0 1 0 1 0 0 0 Rm Rn Rt
- // 0101000xxxxxxxxx
new OpcodeARM(Index.thumbEE_str_1, "str", "0101000xxxxxxxxx"),
- // NEW - Encoding T1 ThumbEE
// A9.4.5 STRH (register)
+ // Encoding T1 ThumbEE
// strh<c> <Rt>,[<Rn>,<Rm>, lsl #1]
// 0 1 0 1 0 0 1 Rm Rn Rt
- // 0101001xxxxxxxxx
new OpcodeARM(Index.thumbEE_strh, "strh", "0101001xxxxxxxxx"),
- // NEW - Encoding E1 ThumbEE
// A9.5.1 CHKA
+ // Encoding E1 ThumbEE
// chka<c> <Rn>,<Rm>
// 1 1 0 0 1 0 1 0 N Rm Rn
- // 11001010xxxxxxxx
new OpcodeARM(Index.thumbEE_chka, "chka", "11001010xxxxxxxx"),
- // NEW - Encoding E1 ThumbEE
// A9.5.2 HB, HBL
+ // Encoding E1 ThumbEE
// hb{l}<c> #<HandlerID>
// 1 1 0 0 0 0 1 L handler
- // 1100001xxxxxxxxx
new OpcodeARM(Index.thumbEE_hb, "hb", "1100001xxxxxxxxx"),
- // NEW - Encoding E1 ThumbEE
// A9.5.3 HBLP
+ // Encoding E1 ThumbEE
// hblp<c> #<imm>, #<HandlerID>
// 1 1 0 0 0 1 imm5 handler
- // 110001xxxxxxxxxx
new OpcodeARM(Index.thumbEE_hblp, "hblp", "110001xxxxxxxxxx"),
- // NEW - Encoding E1 ThumbEE
// A9.5.4 HBP
+ // Encoding E1 ThumbEE
// hbp<c> #<imm>, #<HandlerID>
// 1 1 0 0 0 0 0 0 imm3 handler
- // 11000000xxxxxxxx
new OpcodeARM(Index.thumbEE_hbp, "hbp", "11000000xxxxxxxx"),
- // NEW - Encoding E1 ThumbEE
// A9.5.5 LDR (immediate)
+ // Encoding E1 ThumbEE
// ldr<c> <Rt>,[R9{, #<imm>}]
// 1 1 0 0 1 1 0 imm6 Rt
- // 1100110xxxxxxxxx
new OpcodeARM(Index.thumbEE_ldr_2, "ldr", "1100110xxxxxxxxx"),
- // NEW - Encoding E2 ThumbEE
// A9.5.5 LDR (immediate)
+ // Encoding E2 ThumbEE
// ldr<c> <Rt>,[R10{, #<imm>}]
// 1 1 0 0 1 0 1 1 imm5 Rt
- // 11001011xxxxxxxx
new OpcodeARM(Index.thumbEE_ldr_3, "ldr", "11001011xxxxxxxx"),
- // NEW - Encoding E3 ThumbEE
// A9.5.5 LDR (immediate)
+ // Encoding E3 ThumbEE
// ldr<c> <Rt>,[<Rn>{, #-<imm>}]
// 1 1 0 0 1 0 0 imm3 Rn Rt
- // 1100100xxxxxxxxx
new OpcodeARM(Index.thumbEE_ldr_4, "ldr", "1100100xxxxxxxxx"),
- // NEW - Encoding E1 ThumbEE
// A9.5.6 STR (immediate)
+ // Encoding E1 ThumbEE
// str<c> <Rt>, [R9, #<imm>]
// 1 1 0 0 1 1 1 imm6 Rt
- // 1100111xxxxxxxxx
new OpcodeARM(Index.thumbEE_str_2, "str", "1100111xxxxxxxxx"),
};
+ // Reference manual citations (e.g., "A9.3.1") refer to sections in the ARM Architecture
+ // Reference Manual ARMv7-A and ARMv7-R Edition, Errata markup
public static final OpcodeARM thumbEE_thumb2_opcode_table[] = {
- // NEW - Encoding T1 ThumbEE
// A9.3.1 ENTERX, LEAVEX
+ // Encoding T1 ThumbEE
// enterx Not permitted in IT block. leavex Not permitted in IT block.
- // 1 1 1 1 0 0 1 1 1 0 1 1 (1)(1)(1) (1) 1 0 (0) 0 (1)(1)(1)(1) 0 0 0 J_0_4_4 (1)(1)(1)(1)
- // 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)000x(1)(1)(1)(1)
+ // Unpredictable if (1) is 0 or (0) is 1: 111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)000x(1)(1)(1)(1)
new OpcodeARM(Index.thumb2_enterx_leavex, "enterx", "111100111011xxxx10x0xxxx000xxxxx"),
};
diff --git a/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestDisassemblerARM.java b/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestDisassemblerARM.java
index d9142f4..a37976a 100644
--- a/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestDisassemblerARM.java
+++ b/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestDisassemblerARM.java
@@ -66,7 +66,7 @@
sDisassembler = new DisassemblerARM(null);
}
-
+
@Before
public void setUp() throws Exception {
}
@@ -74,13 +74,13 @@
@After
public void tearDown() throws Exception {
}
-
+
/**
* Test for non-VFP, 32-bit ARM v4*, v5T*, v6*, v7 instructions.
*/
@Test
public void testArmInstructions() {
-
+
System.out.println("\n===================== ARMv5 ========================\n");
String[] insts = {
"E7 F1 23 F4", "undefined",
@@ -225,7 +225,7 @@
"F5 7F F0 47", "dsb nsh",
"F5 7F F0 4A", "dsb ishst",
"F5 7F F0 4B", "dsb ish",
- "F5 7F F0 4D", "dsb #13",
+ "F5 7F F0 4D", "dsb #13",
"F5 7F F0 4E", "dsb st",
"F5 7F F0 4F", "dsb sy",
"02 2A 50 71", "eoreq r5,r10,#0x71",
@@ -1272,7 +1272,7 @@
@Test
public void testArmVFPInstructions() {
-
+
System.out.println("\n====================== ARM VFP ======================\n");
String[] insts = {
"F2 49 57 BA", "vaba.s8 d21,d25,d26",
@@ -2210,7 +2210,9 @@
"F3 C9 6A AA", "vmlsl.u8 q11,d25,d26",
"F3 D9 6A AA", "vmlsl.u16 q11,d25,d26",
"F3 E9 6A AA", "vmlsl.u32 q11,d25,d26",
- "0C 46 5B 3A", "vmoveq d26,r5,r6",
+ "F2 6A 51 BA", "vmov d21,d26",
+ "F2 6E 61 FE", "vmov q11,q15",
+ "0C 46 5B 3A", "vmoveq d26,r5,r6",
"EC 56 5B 3A", "vmov r5,r6,d26",
"0C 56 5A 1D", "vmoveq r5,r6,s26,s27",
"0E 1C 5A 90", "vmoveq r5,s25",
@@ -2233,7 +2235,7 @@
"0E 4B 5B B0", "vmoveq.8 d27[1],r5",
"EE 0B 5B F0", "vmov.16 d27[1],r5",
"EE 2B 5B 90", "vmov.32 d27[1],r5",
- "EE B7 BA 00", "vmov.f32 s22,#0x70", // originally "vmov.f32 s22,#1.0"
+ "EE B7 BA 00", "vmov.f32 s22,#0x70", // originally "vmov.f32 s22,#1.0"
"EE F0 AA 4D", "vmov.f32 s21,s26",
"0E F7 6B 00", "vmoveq.f64 d22,#0x70", // originally "vmov.f64 d22,#1.0"
"0E F0 5B 6A", "vmoveq.f64 d21,d26",
@@ -3300,7 +3302,7 @@
*/
@Test
public void testArmConditionCode() {
-
+
System.out.println("\n================ ARM Condition Code ================\n");
String[] insts = {
"00 A1 00 02", "adceq r0,r1,r2",
@@ -3327,7 +3329,7 @@
*/
@Test
public void testArmAddrMode1() {
-
+
System.out.println("\n================== ARM Addr Mode 1 ==================\n");
String[] insts = {
"E2 81 00 11", "add r0,r1,#0x11",
@@ -3351,7 +3353,7 @@
*/
@Test
public void testArmAddrMode2() {
-
+
System.out.println("\n================== ARM Addr Mode 2 ==================\n");
String[] insts = {
"E5 91 00 11", "ldr r0,[r1,#0x11]",
@@ -3406,7 +3408,7 @@
*/
@Test
public void testArmAddrMode3() {
-
+
System.out.println("\n================== ARM Addr Mode 3 ==================\n");
String[] insts = {
"E1 C1 01 B0", "strh r0,[r1,#0x10]",
@@ -3431,7 +3433,7 @@
*/
@Test
public void testArmAddrMode4() {
-
+
System.out.println("\n================== ARM Addr Mode 4 ==================\n");
String[] insts = {
"E8 90 00 06", "ldm r0,{r1,r2}",
@@ -3447,7 +3449,7 @@
*/
@Test
public void testArmAddrMode5() {
-
+
System.out.println("\n================== ARM Addr Mode 5 ==================\n");
String[] insts = {
"ED 92 10 04", "ldc p0,c1,[r2,#0x10]",
@@ -3466,7 +3468,7 @@
*/
@Test
public void testArmBranches() {
-
+
armOptions.put(IDisassemblerOptions.MNEMONICS_SHOW_ADDRESS, true);
armOptions.put(IDisassemblerOptions.MNEMONICS_SHOW_BYTES, true);
System.out.println("\n=================== ARM Branches ====================\n");
@@ -3493,14 +3495,14 @@
public void testArmBufferUnderflow() {
System.out.println("\n============= ARM CodeBufferUnderflow ===============\n");
catchCodeBufferUnderflowException(0x0, "ea ff", armOptions);
- }
+ }
/**
* Test for Thumb instructions.
*/
@Test
public void testThumbInstructions() {
-
+
System.out.println("\n======================= Thumb =======================\n");
String[] insts = {
"41 75", "adcs r5,r6",
@@ -3617,7 +3619,7 @@
*/
@Test
public void testThumbBranches() {
-
+
thumbOptions.put(IDisassemblerOptions.MNEMONICS_SHOW_ADDRESS, true);
thumbOptions.put(IDisassemblerOptions.MNEMONICS_SHOW_BYTES, true);
System.out.println("\n=================== Thumb Branches ==================\n");
@@ -3642,7 +3644,7 @@
public void testThumbBufferUnderflow() {
System.out.println("\n============ Thumb CodeBufferUnderflow ==============\n");
catchCodeBufferUnderflowException(0x0, "f7", thumbOptions);
- }
+ }
/**
@@ -3672,7 +3674,7 @@
for (Map.Entry<String, Object> entry : armOptions.entrySet())
options.put(entry.getKey(), entry.getValue());
options.put(DisassemblerARM.IDisassemblerOptionsARM.VERSION_MODE, InstructionParserARM.ARMv6K);
- disassembleInstArray(insts, options);
+ disassembleInstArray(insts, options);
}
/**
@@ -3680,7 +3682,7 @@
@Test
public void test32BitArmV6T2Instructions() {
System.out.println("\n================== ARMv6T2 Hint Instructions ==================\n");
-
+
String[] insts = {
"F5 7F F0 1F", "invalid opcode", // clrex
"E3 20 F0 FD", "nop", // dbg #13
@@ -3701,7 +3703,7 @@
for (Map.Entry<String, Object> entry : armOptions.entrySet())
options.put(entry.getKey(), entry.getValue());
options.put(DisassemblerARM.IDisassemblerOptionsARM.VERSION_MODE, InstructionParserARM.ARMv6T2);
- disassembleInstArray(insts, options);
+ disassembleInstArray(insts, options);
}
/**
@@ -3710,18 +3712,18 @@
public void test32BitArmV5Instructions() {
System.out.println("\n================== ARMv5 Instructions (Invalid) ==================\n");
-
+
String[] insts = {
"F5 7F F0 1F", "invalid opcode", // clrex
"E3 20 F0 FD", "invalid opcode", // dbg #13
"03 20 F0 FD", "invalid opcode", // dbgeq #13
- "E3 20 F0 00", "invalid opcode", // nop
+ "E3 20 F0 00", "invalid opcode", // nop
"03 20 F0 00", "invalid opcode", // nopeq
- "E3 20 F0 04", "invalid opcode", // sev
+ "E3 20 F0 04", "invalid opcode", // sev
"03 20 F0 04", "invalid opcode", // seveq
- "E3 20 F0 02", "invalid opcode", // wfe
+ "E3 20 F0 02", "invalid opcode", // wfe
"03 20 F0 02", "invalid opcode", // wfeeq
- "E3 20 F0 03", "invalid opcode", // wfi
+ "E3 20 F0 03", "invalid opcode", // wfi
"03 20 F0 03", "invalid opcode", // wfieq
"E3 20 F0 01", "invalid opcode", // yield
"03 20 F0 01", "invalid opcode", // yieldeq
@@ -3731,15 +3733,15 @@
for (Map.Entry<String, Object> entry : armOptions.entrySet())
options.put(entry.getKey(), entry.getValue());
options.put(DisassemblerARM.IDisassemblerOptionsARM.VERSION_MODE, InstructionParserARM.ARMv5);
- disassembleInstArray(insts, options);
+ disassembleInstArray(insts, options);
}
-
+
/**
* Test for non-VFP, 32-bit THumb2 v6*, v7 instructions.
*/
@Test
public void test32BitThumb2Instructions() {
-
+
System.out.println("\n===================== Thumb2 ========================\n");
String[] insts = {
/// "E7 F1 23 F4", "undefined",
@@ -3976,6 +3978,8 @@
"EB B2 0F 16", "cmp.w r2,r6,lsr #32", // 1110 1011 1011 xxxx .xxx 1111 xxxx xxxx // A8.6.36 T3
"EB B5 7F F9", "cmp.w r5,r9,ror #31", // 1110 1011 1011 xxxx .xxx 1111 xxxx xxxx // A8.6.36 T3
"EB B5 0F 38", "cmp.w r5,r8,rrx", // 1110 1011 1011 xxxx .xxx 1111 xxxx xxxx // A8.6.36 T3
+ "F3 AF 81 00", "cps #0",
+ "F3 AF 81 1F", "cps #31",
"F3 AF 86 A0", "cpsid af", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // B6.1.1 T2
"F3 AF 87 FF", "cpsid aif,#31", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // B6.1.1 T2
"F3 AF 87 61", "cpsid if,#1", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // B6.1.1 T2
@@ -3983,7 +3987,7 @@
"F3 AF 85 FF", "cpsie aif,#31", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // B6.1.1 T2
"F3 AF 85 61", "cpsie if,#1", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // B6.1.1 T2
"F3 AF 80 F0", "dbg #0", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
- "F3 AF 80 FD", "dbg #13", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
+ "F3 AF 80 FD", "dbg #13", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
"F3 BF 8F 50", "dmb #0", // 1111 0011 1011 :::: 10.0 :::: 0101 xxxx // A8.6.41 T1
"F3 BF 8F 52", "dmb oshst", // 1111 0011 1011 :::: 10.0 :::: 0101 xxxx // A8.6.41 T1
"F3 BF 8F 53", "dmb osh", // 1111 0011 1011 :::: 10.0 :::: 0101 xxxx // A8.6.41 T1
@@ -4340,7 +4344,7 @@
"FA 89 F5 BA", "qdsub r5,r10,r9", // 1111 1010 1000 xxxx 1111 xxxx 1011 xxxx // A8.6.129 T1
"FA E9 F5 1A", "qsax r5,r9,r10", // 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx // A8.6.130 T1
"FA 89 F5 AA", "qsub r5,r10,r9", // 1111 1010 1000 xxxx 1111 xxxx 101A xxxx // A8.6.131 T1
- "FA D9 F5 1A", "qsub16 r5,r9,r10", // 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx // A8.6.132 T1
+ "FA D9 F5 1A", "qsub16 r5,r9,r10", // 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx // A8.6.132 T1
"FA C9 F5 1A", "qsub8 r5,r9,r10", // 1111 1010 1100 xxxx 1111 xxxx 0001 xxxx // A8.6.133 T1
"FA 99 F5 A9", "rbit r5,r9", // 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx // A8.6.134 T1
"FA 99 F5 89", "rev.w r5,r9", // 1111 1010 1001 xxxx 1111 xxxx 1000 xxxx // A8.6.135 T1
@@ -4481,16 +4485,16 @@
"E8 0D C0 13", "srsdb sp,#0x13", // 1110 1000 00x0 ::.: ::.. .... ...x xxxx // B6.1.10 T1
"E9 AD C0 13", "srsia sp!,#0x13", // 1110 1001 10x0 ::.: ::.. .... ...x xxxx // B6.1.10 T2
"E9 8D C0 13", "srsia sp,#0x13", // 1110 1001 10x0 ::.: ::.. .... ...x xxxx // B6.1.10 T2
- "F3 0A 05 1C", "ssat r5,#29,r10", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
- "F3 2A 05 5C", "ssat r5,#29,r10,asr #1", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
- "F3 2A 75 9C", "ssat r5,#29,r10,asr #30", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
- "F3 0A 05 5C", "ssat r5,#29,r10,lsl #1", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
+ "F3 0A 05 1C", "ssat r5,#29,r10", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
+ "F3 2A 05 5C", "ssat r5,#29,r10,asr #1", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
+ "F3 2A 75 9C", "ssat r5,#29,r10,asr #30", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
+ "F3 0A 05 5C", "ssat r5,#29,r10,lsl #1", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
"F3 0A 75 DC", "ssat r5,#29,r10,lsl #31", // 1111 0.11 00x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.183 T1
"F3 2A 05 0C", "ssat16 r5,#13,r10", // 1111 0.11 0010 xxxx 0000 xxxx 00.. xxxx // A8.6.184 T1
"FA E9 F5 0A", "ssax r5,r9,r10", // 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx // A8.6.185 T1
"FA D9 F5 0A", "ssub16 r5,r9,r10", // 1111 1010 1101 xxxx 1111 xxxx 0000 xxxx // A8.6.186 T1
"FA C9 F5 0A", "ssub8 r5,r9,r10", // 1111 1010 1100 xxxx 1111 xxxx 0000 xxxx // A8.6.187 T1
- "ED 0A B9 21", "stc p9,c11,[r10,#-0x84]", // 1110 110x xxx0 xxxx xxxx xxxx xxxx xxxx // A8.6.188 T1
+ "ED 0A B9 21", "stc p9,c11,[r10,#-0x84]", // 1110 110x xxx0 xxxx xxxx xxxx xxxx xxxx // A8.6.188 T1
"ED 2A B9 21", "stc p9,c11,[r10,#-0x84]!", // 1110 110x xxx0 xxxx xxxx xxxx xxxx xxxx // A8.6.188 T1
"ED 8A B9 21", "stc p9,c11,[r10,#0x84]", // 1110 110x xxx0 xxxx xxxx xxxx xxxx xxxx // A8.6.188 T1
"ED AA B9 21", "stc p9,c11,[r10,#0x84]!", // 1110 110x xxx0 xxxx xxxx xxxx xxxx xxxx // A8.6.188 T1
@@ -4729,9 +4733,9 @@
"FB 79 F5 0A", "usad8 r5,r9,r10", // 1111 1011 0111 xxxx 1111 xxxx 0000 xxxx // A8.6.253 T1
"FB 79 85 0A", "usada8 r5,r9,r10,r8", // 1111 1011 0111 xxxx xxxx xxxx 0000 xxxx // A8.6.253 T1
"F3 8A 05 1C", "usat r5,#28,r10", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
- "F3 AA 05 5C", "usat r5,#28,r10,asr #1", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
- "F3 AA 75 9C", "usat r5,#28,r10,asr #30", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
- "F3 8A 05 5C", "usat r5,#28,r10,lsl #1", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
+ "F3 AA 05 5C", "usat r5,#28,r10,asr #1", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
+ "F3 AA 75 9C", "usat r5,#28,r10,asr #30", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
+ "F3 8A 05 5C", "usat r5,#28,r10,lsl #1", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
"F3 8A 75 DC", "usat r5,#28,r10,lsl #31", // 1111 0.11 10x0 xxxx 0xxx xxxx xx.x xxxx // A8.6.255 T1
"F3 AA 05 0C", "usat16 r5,#12,r10", // 1111 0.11 1010 xxxx 0000 xxxx 00.. xxxx // A8.6.256 T1
"FA E9 F5 4A", "usax r5,r9,r10", // 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx // A8.6.257 T1
@@ -4766,12 +4770,12 @@
"F3 AF 80 01", "yield.w", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.413
};
- disassembleInstArray(insts, thumbOptions);
+ disassembleInstArray(insts, thumbOptions);
}
@Test
public void test32BitThumbVFPInstructions() {
-
+
System.out.println("\n====================== ARM VFP ======================\n");
String[] insts = {
"EF 49 57 BA", "vaba.s8 d21,d25,d26",
@@ -5709,6 +5713,8 @@
"FF C9 6A AA", "vmlsl.u8 q11,d25,d26",
"FF D9 6A AA", "vmlsl.u16 q11,d25,d26",
"FF E9 6A AA", "vmlsl.u32 q11,d25,d26",
+ "EF 6A 51 BA", "vmov d21,d26",
+ "EF 6E 61 FE", "vmov q11,q15",
"EC 46 5B 3A", "vmov d26,r5,r6",
"EC 56 5B 3A", "vmov r5,r6,d26",
"EC 56 5A 1D", "vmov r5,r6,s26,s27",
@@ -6794,14 +6800,14 @@
disassembleInstArray(insts, thumbOptions);
}
-
+
/**
* Test for Thumb 32-bit Imm12
* see reference manual algorithm for ThumbExpandImm
*/
@Test
public void testThumb2ExpandImm12() {
-
+
System.out.println("\n================== Thumb2 Expand Imm12 Mode ==================\n");
// A6.3.2 Modified Immediate constants in Thumb 32-bit instructions
@@ -6839,7 +6845,7 @@
*/
@Test
public void testThumb2ShifterOperand() {
-
+
System.out.println("\n================== Thumb2 Shifter Operand ==================\n");
String[] insts = {
"EB 09 05 0A", "add.w r5,r9,r10",
@@ -6847,7 +6853,7 @@
"EB 07 03 48", "add.w r3,r7,r8,lsl #1",
"EB 06 02 17", "add.w r2,r6,r7,lsr #32",
"EB 09 75 F8", "add.w r5,r9,r8,ror #31",
- "EB 08 05 39", "add.w r5,r8,r9,rrx",
+ "EB 08 05 39", "add.w r5,r8,r9,rrx",
};
disassembleInstArray(insts, thumbOptions);
}
@@ -6863,7 +6869,7 @@
String[] insts = {
"F3 BF 8F 2F", "invalid opcode", // 1111 0011 1011 :::: 10.0 :::: 0010 :::: // A8.6.30 T1
"F3 AF 80 F0", "nop.w", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
- "F3 AF 80 FD", "nop.w", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
+ "F3 AF 80 FD", "nop.w", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
"F3 BF 8F 50", "invalid opcode", // 1111 0011 1011 :::: 10.0 :::: 0101 xxxx // A8.6.41 T1
"F3 BF 8F 52", "invalid opcode", // 1111 0011 1011 :::: 10.0 :::: 0101 xxxx // A8.6.41 T1
"F3 BF 8F 53", "invalid opcode", // 1111 0011 1011 :::: 10.0 :::: 0101 xxxx // A8.6.41 T1
@@ -6904,7 +6910,7 @@
public void testThumb2V4TInstructions() {
System.out.println("\n================== Thumb2 V4T Instructions ==================\n");
-
+
String[] insts = {
// "Fx xx xx 0x", "bl 0x________", // 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx // A8.6.23 T1
// ARM "0B FF FF FE", "bleq 0x00000000",
@@ -6916,7 +6922,7 @@
// ARM "01 2F FF 39", "blxeq r9",
"F3 BF 8F 2F", "invalid opcode", // 1111 0011 1011 :::: 10.0 :::: 0010 :::: // A8.6.30 T1
"F3 AF 80 F0", "invalid opcode", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
- "F3 AF 80 FD", "invalid opcode", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
+ "F3 AF 80 FD", "invalid opcode", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.40 T1
"F3 AF 80 04", "invalid opcode", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.158 T1
"F3 AF 80 02", "invalid opcode", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.411 T1
"F3 AF 80 03", "invalid opcode", // 1111 0011 1010 :::: 10.0 .xxx xxxx xxxx // A8.6.412 T1
@@ -6927,7 +6933,7 @@
for (Map.Entry<String, Object> entry : thumbOptions.entrySet())
options.put(entry.getKey(), entry.getValue());
options.put(DisassemblerARM.IDisassemblerOptionsARM.VERSION_MODE, InstructionParserARM.ARMv4T);
- disassembleInstArray(insts, options);
+ disassembleInstArray(insts, options);
}
/**
diff --git a/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestOpcodeARM.java b/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestOpcodeARM.java
index 1cac631..888b550 100644
--- a/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestOpcodeARM.java
+++ b/org.eclipse.cdt.debug.edc.tests/src/org/eclipse/cdt/debug/edc/tests/TestOpcodeARM.java
@@ -654,8 +654,7 @@
this.new OpcodeTest(OpcodeARM.Index.thumb2_vmax_vmin__fp, 0xEF000F00), // ____ ____ _xxx xxxx xxxx ____ xxx_ xxxx
this.new OpcodeTest(OpcodeARM.Index.thumb2_vrecps, 0xEF000F10), // ____ ____ _x_x xxxx xxxx ____ xxx_ xxxx
this.new OpcodeTest(OpcodeARM.Index.thumb2_vbic__reg, 0xEF100110), // ____ ____ _x__ xxxx xxxx ____ xxx_ xxxx
- this.new OpcodeTest(OpcodeARM.Index.thumb2_vmov__reg, 0xEF200110), // ____ ____ _x__ xxxx xxxx ____ xxx_ xxxx
- this.new OpcodeTest(OpcodeARM.Index.thumb2_vorr__reg, 0xEF200110), // ____ ____ _x__ xxxx xxxx ____ xxx_ xxxx
+ this.new OpcodeTest(OpcodeARM.Index.thumb2_vmov_vorr, 0xEF200110), // ____ ____ _x__ xxxx xxxx ____ xxx_ xxxx
this.new OpcodeTest(OpcodeARM.Index.thumb2_vsub__f32, 0xEF200D00), // ____ ____ _x_x xxxx xxxx ____ xxx_ xxxx
this.new OpcodeTest(OpcodeARM.Index.thumb2_vrsqrts, 0xEF200F10), // ____ ____ _x_x xxxx xxxx ____ xxx_ xxxx
this.new OpcodeTest(OpcodeARM.Index.thumb2_vorn, 0xEF300110), // ____ ____ _x__ xxxx xxxx ____ xxx_ xxxx
