| /** |
| * ******************************************************************************* |
| * Copyright (c) 2019 Robert Bosch GmbH and others. |
| * |
| * This program and the accompanying materials are made |
| * available under the terms of the Eclipse Public License 2.0 |
| * which is available at https://www.eclipse.org/legal/epl-2.0/ |
| * |
| * SPDX-License-Identifier: EPL-2.0 |
| * |
| * Contributors: |
| * Robert Bosch GmbH - initial API and implementation |
| * ******************************************************************************* |
| */ |
| |
| package templates.m2m.hw |
| |
| import com.google.inject.Inject |
| import org.eclipse.app4mc.amalthea.model.Cache |
| import org.eclipse.app4mc.amalthea.model.HwStructure |
| import org.eclipse.app4mc.amalthea.model.Memory |
| import org.eclipse.app4mc.amalthea.model.ProcessingUnit |
| import templates.AbstractAmaltheaInchronTransformer |
| import com.google.inject.Singleton |
| |
| @Singleton |
| class HWStructure_MicroControllerTransformer extends AbstractAmaltheaInchronTransformer { |
| |
| @Inject MemoryTransformer memoryTransformer |
| |
| @Inject CacheTransformer cacheTransformer |
| |
| @Inject ProcessingUnitTransformer processingUnitTransformer |
| |
| @Inject FrequencyDomainTransformer frequencyDomainTransformer |
| |
| def create inchronModelFactory.createCpu createCpu(HwStructure amltHWMicroController) { |
| |
| it.name = amltHWMicroController.name |
| it.cpuModel = "generic" |
| |
| amltHWMicroController.modules.forEach [ amltHwModule | |
| if (amltHwModule instanceof Memory) { |
| it.memories.add(memoryTransformer.createMemory(amltHwModule)) |
| |
| } else if (amltHwModule instanceof Cache) { |
| it.memories.add(cacheTransformer.createCache(amltHwModule)) |
| } |
| ] |
| |
| // creating default memory regions |
| var inchronRamRegion = inchronModelFactory.createMemoryRegion |
| inchronRamRegion.name = "ram" |
| inchronRamRegion.base = 16777216 |
| inchronRamRegion.sections = "data:bss:stack:heap" |
| inchronRamRegion.pages = 1 |
| inchronRamRegion.flags = 290 |
| |
| var inchronRomRegion = inchronModelFactory.createMemoryRegion |
| inchronRomRegion.name = "rom" |
| inchronRomRegion.base = 33554432 |
| inchronRomRegion.sections = "text" |
| inchronRomRegion.pages = 1 |
| inchronRomRegion.flags = 275 |
| |
| it.memoryRegions.add(inchronRamRegion) |
| it.memoryRegions.add(inchronRomRegion) |
| |
| // Creation of Cores |
| val amltModules = amltHWMicroController.modules |
| |
| amltModules.forEach [ amltHwModule | |
| if (amltHwModule instanceof ProcessingUnit) { |
| it.cores.add(processingUnitTransformer.createCpuCore(amltHwModule)) |
| it.clock = frequencyDomainTransformer.createClock(amltHwModule?.frequencyDomain) |
| } |
| ] |
| |
| } |
| } |