| /******************************************************************** |
| * |
| * Standard register and bit definitions for the Texas Instruments |
| * MSP430 microcontroller. |
| * |
| * This file supports assembler and C development for |
| * MSP430x22x4 devices. |
| * |
| * Texas Instruments, Version 1.4 |
| * |
| * Rev. 1.0, Setup |
| * Rev. 1.1, Updated names for USCI |
| * Rev. 1.2, Added missing definitions in OA and ADC10 |
| * Rev. 1.3 Removed bit definitions for ADC10AEx as this are in conflict with ADC10AEx Register |
| * Removed not existing SWCTL register definition |
| * Rev. 1.4, added definitions for Interrupt Vectors xxIV |
| * |
| ********************************************************************/ |
| |
| #ifndef __msp430x22x4 |
| #define __msp430x22x4 |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| |
| /*----------------------------------------------------------------------------*/ |
| /* PERIPHERAL FILE MAP */ |
| /*----------------------------------------------------------------------------*/ |
| |
| /* External references resolved by a device-specific linker command file */ |
| #define SFR_8BIT(address) extern volatile unsigned char address |
| #define SFR_16BIT(address) extern volatile unsigned int address |
| |
| |
| /************************************************************ |
| * STANDARD BITS |
| ************************************************************/ |
| |
| #define BIT0 (0x0001) |
| #define BIT1 (0x0002) |
| #define BIT2 (0x0004) |
| #define BIT3 (0x0008) |
| #define BIT4 (0x0010) |
| #define BIT5 (0x0020) |
| #define BIT6 (0x0040) |
| #define BIT7 (0x0080) |
| #define BIT8 (0x0100) |
| #define BIT9 (0x0200) |
| #define BITA (0x0400) |
| #define BITB (0x0800) |
| #define BITC (0x1000) |
| #define BITD (0x2000) |
| #define BITE (0x4000) |
| #define BITF (0x8000) |
| |
| /************************************************************ |
| * STATUS REGISTER BITS |
| ************************************************************/ |
| |
| #define C (0x0001) |
| #define Z (0x0002) |
| #define N (0x0004) |
| #define V (0x0100) |
| #define GIE (0x0008) |
| #define CPUOFF (0x0010) |
| #define OSCOFF (0x0020) |
| #define SCG0 (0x0040) |
| #define SCG1 (0x0080) |
| |
| /* Low Power Modes coded with Bits 4-7 in SR */ |
| |
| #ifdef __ASM_HEADER__ /* Begin #defines for assembler */ |
| #define LPM0 (CPUOFF) |
| #define LPM1 (SCG0+CPUOFF) |
| #define LPM2 (SCG1+CPUOFF) |
| #define LPM3 (SCG1+SCG0+CPUOFF) |
| #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) |
| /* End #defines for assembler */ |
| |
| #else /* Begin #defines for C */ |
| #define LPM0_bits (CPUOFF) |
| #define LPM1_bits (SCG0+CPUOFF) |
| #define LPM2_bits (SCG1+CPUOFF) |
| #define LPM3_bits (SCG1+SCG0+CPUOFF) |
| #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) |
| |
| #include <In430.h> |
| |
| #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ |
| #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ |
| #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ |
| #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ |
| #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ |
| #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ |
| #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ |
| #define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ |
| #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ |
| #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ |
| #endif /* End #defines for C */ |
| |
| /************************************************************ |
| * PERIPHERAL FILE MAP |
| ************************************************************/ |
| |
| /************************************************************ |
| * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS |
| ************************************************************/ |
| |
| SFR_8BIT(IE1); /* Interrupt Enable 1 */ |
| #define WDTIE (0x01) /* Watchdog Interrupt Enable */ |
| #define OFIE (0x02) /* Osc. Fault Interrupt Enable */ |
| #define NMIIE (0x10) /* NMI Interrupt Enable */ |
| #define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */ |
| |
| SFR_8BIT(IFG1); /* Interrupt Flag 1 */ |
| #define WDTIFG (0x01) /* Watchdog Interrupt Flag */ |
| #define OFIFG (0x02) /* Osc. Fault Interrupt Flag */ |
| #define PORIFG (0x04) /* Power On Interrupt Flag */ |
| #define RSTIFG (0x08) /* Reset Interrupt Flag */ |
| #define NMIIFG (0x10) /* NMI Interrupt Flag */ |
| |
| SFR_8BIT(IE2); /* Interrupt Enable 2 */ |
| #define UC0IE IE2 |
| #define UCA0RXIE (0x01) |
| #define UCA0TXIE (0x02) |
| #define UCB0RXIE (0x04) |
| #define UCB0TXIE (0x08) |
| |
| SFR_8BIT(IFG2); /* Interrupt Flag 2 */ |
| #define UC0IFG IFG2 |
| #define UCA0RXIFG (0x01) |
| #define UCA0TXIFG (0x02) |
| #define UCB0RXIFG (0x04) |
| #define UCB0TXIFG (0x08) |
| |
| /************************************************************ |
| * ADC10 |
| ************************************************************/ |
| #define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */ |
| |
| SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */ |
| SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */ |
| SFR_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */ |
| SFR_8BIT(ADC10AE1); /* ADC10 Analog Enable 1 */ |
| |
| SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */ |
| SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */ |
| SFR_16BIT(ADC10MEM); /* ADC10 Memory */ |
| SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address */ |
| |
| /* ADC10CTL0 */ |
| #define ADC10SC (0x001) /* ADC10 Start Conversion */ |
| #define ENC (0x002) /* ADC10 Enable Conversion */ |
| #define ADC10IFG (0x004) /* ADC10 Interrupt Flag */ |
| #define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */ |
| #define ADC10ON (0x010) /* ADC10 On/Enable */ |
| #define REFON (0x020) /* ADC10 Reference on */ |
| #define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */ |
| #define MSC (0x080) /* ADC10 Multiple SampleConversion */ |
| #define REFBURST (0x100) /* ADC10 Reference Burst Mode */ |
| #define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */ |
| #define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */ |
| #define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select 0 */ |
| #define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select 1 */ |
| #define SREF0 (0x2000) /* ADC10 Reference Select 0 */ |
| #define SREF1 (0x4000) /* ADC10 Reference Select 1 */ |
| #define SREF3 (0x8000) /* ADC10 Reference Select 2 */ |
| #define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */ |
| #define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */ |
| #define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */ |
| #define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */ |
| |
| #define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */ |
| #define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */ |
| #define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */ |
| #define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */ |
| #define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */ |
| #define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */ |
| #define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ |
| #define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ |
| |
| /* ADC10CTL1 */ |
| #define ADC10BUSY (0x0001) /* ADC10CTL1 */ |
| #define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */ |
| #define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */ |
| #define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select 0 */ |
| #define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select 1 */ |
| #define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select 0 */ |
| #define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select 1 */ |
| #define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select 2 */ |
| #define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */ |
| #define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */ |
| #define SHS0 (0x0400) /* ADC10 Sample/Hold Source 0 */ |
| #define SHS1 (0x0800) /* ADC10 Sample/Hold Source 1 */ |
| #define INCH0 (0x1000) /* ADC10 Input Channel Select 0 */ |
| #define INCH1 (0x2000) /* ADC10 Input Channel Select 1 */ |
| #define INCH2 (0x4000) /* ADC10 Input Channel Select 2 */ |
| #define INCH3 (0x8000) /* ADC10 Input Channel Select 3 */ |
| |
| #define CONSEQ_0 (0*2u) /* Single channel single conversion */ |
| #define CONSEQ_1 (1*2u) /* Sequence of channels */ |
| #define CONSEQ_2 (2*2u) /* Repeat single channel */ |
| #define CONSEQ_3 (3*2u) /* Repeat sequence of channels */ |
| |
| #define ADC10SSEL_0 (0*8u) /* ADC10OSC */ |
| #define ADC10SSEL_1 (1*8u) /* ACLK */ |
| #define ADC10SSEL_2 (2*8u) /* MCLK */ |
| #define ADC10SSEL_3 (3*8u) /* SMCLK */ |
| |
| #define ADC10DIV_0 (0*0x20u) |
| #define ADC10DIV_1 (1*0x20u) |
| #define ADC10DIV_2 (2*0x20u) |
| #define ADC10DIV_3 (3*0x20u) |
| #define ADC10DIV_4 (4*0x20u) |
| #define ADC10DIV_5 (5*0x20u) |
| #define ADC10DIV_6 (6*0x20u) |
| #define ADC10DIV_7 (7*0x20u) |
| |
| #define SHS_0 (0*0x400u) /* ADC10SC */ |
| #define SHS_1 (1*0x400u) /* TA3 OUT1 */ |
| #define SHS_2 (2*0x400u) /* TA3 OUT0 */ |
| #define SHS_3 (3*0x400u) /* TA3 OUT2 */ |
| |
| #define INCH_0 (0*0x1000u) |
| #define INCH_1 (1*0x1000u) |
| #define INCH_2 (2*0x1000u) |
| #define INCH_3 (3*0x1000u) |
| #define INCH_4 (4*0x1000u) |
| #define INCH_5 (5*0x1000u) |
| #define INCH_6 (6*0x1000u) |
| #define INCH_7 (7*0x1000u) |
| #define INCH_8 (8*0x1000u) |
| #define INCH_9 (9*0x1000u) |
| #define INCH_10 (10*0x1000u) |
| #define INCH_11 (11*0x1000u) |
| #define INCH_12 (12*0x1000u) /* Selects Channel 11 */ |
| #define INCH_13 (13*0x1000u) /* Selects Channel 11 */ |
| #define INCH_14 (14*0x1000u) /* Selects Channel 11 */ |
| #define INCH_15 (15*0x1000u) /* Selects Channel 11 */ |
| |
| /* ADC10DTC0 */ |
| #define ADC10FETCH (0x001) |
| #define ADC10B1 (0x002) |
| #define ADC10CT (0x004) |
| #define ADC10TB (0x008) |
| #define ADC10DISABLE (0x000) /* ADC10DTC1 */ |
| |
| /************************************************************ |
| * Basic Clock Module |
| ************************************************************/ |
| #define __MSP430_HAS_BC2__ /* Definition to show that Module is available */ |
| |
| SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */ |
| SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */ |
| SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */ |
| SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */ |
| |
| #define MOD0 (0x01) /* Modulation Bit 0 */ |
| #define MOD1 (0x02) /* Modulation Bit 1 */ |
| #define MOD2 (0x04) /* Modulation Bit 2 */ |
| #define MOD3 (0x08) /* Modulation Bit 3 */ |
| #define MOD4 (0x10) /* Modulation Bit 4 */ |
| #define DCO0 (0x20) /* DCO Select Bit 0 */ |
| #define DCO1 (0x40) /* DCO Select Bit 1 */ |
| #define DCO2 (0x80) /* DCO Select Bit 2 */ |
| |
| #define RSEL0 (0x01) /* Range Select Bit 0 */ |
| #define RSEL1 (0x02) /* Range Select Bit 1 */ |
| #define RSEL2 (0x04) /* Range Select Bit 2 */ |
| #define RSEL3 (0x08) /* Range Select Bit 3 */ |
| #define DIVA0 (0x10) /* ACLK Divider 0 */ |
| #define DIVA1 (0x20) /* ACLK Divider 1 */ |
| #define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ |
| #define XT2OFF (0x80) /* Enable XT2CLK */ |
| |
| #define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ |
| #define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ |
| #define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ |
| #define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ |
| |
| #define DCOR (0x01) /* Enable External Resistor : 1 */ |
| #define DIVS0 (0x02) /* SMCLK Divider 0 */ |
| #define DIVS1 (0x04) /* SMCLK Divider 1 */ |
| #define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ |
| #define DIVM0 (0x10) /* MCLK Divider 0 */ |
| #define DIVM1 (0x20) /* MCLK Divider 1 */ |
| #define SELM0 (0x40) /* MCLK Source Select 0 */ |
| #define SELM1 (0x80) /* MCLK Source Select 1 */ |
| |
| #define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ |
| #define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ |
| #define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ |
| #define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ |
| |
| #define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ |
| #define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ |
| #define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ |
| #define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ |
| |
| #define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ |
| #define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ |
| #define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ |
| #define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ |
| |
| #define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */ |
| #define XT2OF (0x02) /* High frequency oscillator 2 fault flag */ |
| #define XCAP0 (0x04) /* XIN/XOUT Cap 0 */ |
| #define XCAP1 (0x08) /* XIN/XOUT Cap 1 */ |
| #define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */ |
| #define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */ |
| #define XT2S0 (0x40) /* Mode 0 for XT2 */ |
| #define XT2S1 (0x80) /* Mode 1 for XT2 */ |
| |
| #define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */ |
| #define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */ |
| #define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */ |
| #define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */ |
| |
| #define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ |
| #define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */ |
| #define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */ |
| #define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */ |
| |
| #define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */ |
| #define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */ |
| #define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */ |
| #define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */ |
| |
| /************************************************************* |
| * Flash Memory |
| *************************************************************/ |
| #define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */ |
| |
| SFR_16BIT(FCTL1); /* FLASH Control 1 */ |
| SFR_16BIT(FCTL2); /* FLASH Control 2 */ |
| SFR_16BIT(FCTL3); /* FLASH Control 3 */ |
| |
| #define FRKEY (0x9600) /* Flash key returned by read */ |
| #define FWKEY (0xA500) /* Flash key for write */ |
| #define FXKEY (0x3300) /* for use with XOR instruction */ |
| |
| #define ERASE (0x0002) /* Enable bit for Flash segment erase */ |
| #define MERAS (0x0004) /* Enable bit for Flash mass erase */ |
| #define EEI (0x0008) /* Enable Erase Interrupts */ |
| #define EEIEX (0x0010) /* Enable Emergency Interrupt Exit */ |
| #define WRT (0x0040) /* Enable bit for Flash write */ |
| #define BLKWRT (0x0080) /* Enable bit for Flash segment write */ |
| #define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ |
| |
| #define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ |
| #define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ |
| #ifndef FN2 |
| #define FN2 (0x0004) |
| #endif |
| #ifndef FN3 |
| #define FN3 (0x0008) |
| #endif |
| #ifndef FN4 |
| #define FN4 (0x0010) |
| #endif |
| #define FN5 (0x0020) |
| #define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ |
| #define FSSEL1 (0x0080) /* Flash clock select 1 */ |
| |
| #define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ |
| #define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ |
| #define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ |
| #define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ |
| |
| #define BUSY (0x0001) /* Flash busy: 1 */ |
| #define KEYV (0x0002) /* Flash Key violation flag */ |
| #define ACCVIFG (0x0004) /* Flash Access violation flag */ |
| #define WAIT (0x0008) /* Wait flag for segment write */ |
| #define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ |
| #define EMEX (0x0020) /* Flash Emergency Exit */ |
| #define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ |
| #define FAIL (0x0080) /* Last Program or Erase failed */ |
| |
| /************************************************************ |
| * Operational Amplifier |
| ************************************************************/ |
| #define __MSP430_HAS_OA_2__ /* Definition to show that Module is available */ |
| |
| SFR_8BIT(OA0CTL0); /* OA0 Control register 0 */ |
| SFR_8BIT(OA0CTL1); /* OA0 Control register 1 */ |
| SFR_8BIT(OA1CTL0); /* OA1 Control register 0 */ |
| SFR_8BIT(OA1CTL1); /* OA1 Control register 1 */ |
| |
| #define OAADC0 (0x01) /* OAx output to ADC12 input channel select 0 */ |
| #define OAADC1 (0x02) /* OAx output to ADC12 input channel select 1 */ |
| #define OAPM0 (0x04) /* OAx Power mode select 0 */ |
| #define OAPM1 (0x08) /* OAx Power mode select 1 */ |
| #define OAP0 (0x10) /* OAx Non-inverting input select 0 */ |
| #define OAP1 (0x20) /* OAx Non-inverting input select 1 */ |
| #define OAN0 (0x40) /* OAx Inverting input select 0 */ |
| #define OAN1 (0x80) /* OAx Inverting input select 1 */ |
| |
| #define OAPM_0 (0x00) /* OAx Power mode select: off */ |
| #define OAPM_1 (0x04) /* OAx Power mode select: slow */ |
| #define OAPM_2 (0x08) /* OAx Power mode select: meduim */ |
| #define OAPM_3 (0x0C) /* OAx Power mode select: fast */ |
| #define OAP_0 (0x00) /* OAx Non-inverting input select 00 */ |
| #define OAP_1 (0x10) /* OAx Non-inverting input select 01 */ |
| #define OAP_2 (0x20) /* OAx Non-inverting input select 10 */ |
| #define OAP_3 (0x30) /* OAx Non-inverting input select 11 */ |
| #define OAN_0 (0x00) /* OAx Inverting input select 00 */ |
| #define OAN_1 (0x40) /* OAx Inverting input select 01 */ |
| #define OAN_2 (0x80) /* OAx Inverting input select 10 */ |
| #define OAN_3 (0xC0) /* OAx Inverting input select 11 */ |
| |
| #define OARRIP (0x01) /* OAx Rail-to-Rail Input off */ |
| #define OANEXT (0x02) /* OAx Inverting input external */ |
| //#define OACAL (0x02) /* OAx Offset Calibration */ |
| #define OAFC0 (0x04) /* OAx Function control 0 */ |
| #define OAFC1 (0x08) /* OAx Function control 1 */ |
| #define OAFC2 (0x10) /* OAx Function control 2 */ |
| #define OAFBR0 (0x20) /* OAx Feedback resistor select 0 */ |
| #define OAFBR1 (0x40) /* OAx Feedback resistor select 1 */ |
| #define OAFBR2 (0x80) /* OAx Feedback resistor select 2 */ |
| |
| #define OAFC_0 (0x00) /* OAx Function: Gen. Purpose */ |
| #define OAFC_1 (0x04) /* OAx Function: Unity gain buffer */ |
| #define OAFC_2 (0x08) /* OAx Function: Reserved */ |
| #define OAFC_3 (0x0C) /* OAx Function: Comparator */ |
| #define OAFC_4 (0x10) /* OAx Function: Non-inverting PGA */ |
| #define OAFC_5 (0x14) /* OAx Function: Cascaded non-inverting PGA */ |
| #define OAFC_6 (0x18) /* OAx Function: Inverting PGA */ |
| #define OAFC_7 (0x1C) /* OAx Function: Differential amplifier */ |
| #define OAFBR_0 (0x00) /* OAx Feedback resistor: Tap 0 */ |
| #define OAFBR_1 (0x20) /* OAx Feedback resistor: Tap 1 */ |
| #define OAFBR_2 (0x40) /* OAx Feedback resistor: Tap 2 */ |
| #define OAFBR_3 (0x60) /* OAx Feedback resistor: Tap 3 */ |
| #define OAFBR_4 (0x80) /* OAx Feedback resistor: Tap 4 */ |
| #define OAFBR_5 (0xA0) /* OAx Feedback resistor: Tap 5 */ |
| #define OAFBR_6 (0xC0) /* OAx Feedback resistor: Tap 6 */ |
| #define OAFBR_7 (0xE0) /* OAx Feedback resistor: Tap 7 */ |
| |
| /************************************************************ |
| * DIGITAL I/O Port1/2 Pull up / Pull down Resistors |
| ************************************************************/ |
| #define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ |
| #define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ |
| |
| SFR_8BIT(P1IN); /* Port 1 Input */ |
| SFR_8BIT(P1OUT); /* Port 1 Output */ |
| SFR_8BIT(P1DIR); /* Port 1 Direction */ |
| SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */ |
| SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */ |
| SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */ |
| SFR_8BIT(P1SEL); /* Port 1 Selection */ |
| SFR_8BIT(P1REN); /* Port 1 Resistor Enable */ |
| |
| SFR_8BIT(P2IN); /* Port 2 Input */ |
| SFR_8BIT(P2OUT); /* Port 2 Output */ |
| SFR_8BIT(P2DIR); /* Port 2 Direction */ |
| SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */ |
| SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */ |
| SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */ |
| SFR_8BIT(P2SEL); /* Port 2 Selection */ |
| SFR_8BIT(P2REN); /* Port 2 Resistor Enable */ |
| |
| /************************************************************ |
| * DIGITAL I/O Port3/4 Pull up / Pull down Resistors |
| ************************************************************/ |
| #define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ |
| #define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ |
| |
| SFR_8BIT(P3IN); /* Port 3 Input */ |
| SFR_8BIT(P3OUT); /* Port 3 Output */ |
| SFR_8BIT(P3DIR); /* Port 3 Direction */ |
| SFR_8BIT(P3SEL); /* Port 3 Selection */ |
| SFR_8BIT(P3REN); /* Port 3 Resistor Enable */ |
| |
| SFR_8BIT(P4IN); /* Port 4 Input */ |
| SFR_8BIT(P4OUT); /* Port 4 Output */ |
| SFR_8BIT(P4DIR); /* Port 4 Direction */ |
| SFR_8BIT(P4SEL); /* Port 4 Selection */ |
| SFR_8BIT(P4REN); /* Port 4 Resistor Enable */ |
| |
| /************************************************************ |
| * Timer A3 |
| ************************************************************/ |
| #define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ |
| |
| SFR_16BIT(TAIV); /* Timer A Interrupt Vector Word */ |
| SFR_16BIT(TACTL); /* Timer A Control */ |
| SFR_16BIT(TACCTL0); /* Timer A Capture/Compare Control 0 */ |
| SFR_16BIT(TACCTL1); /* Timer A Capture/Compare Control 1 */ |
| SFR_16BIT(TACCTL2); /* Timer A Capture/Compare Control 2 */ |
| SFR_16BIT(TAR); /* Timer A */ |
| SFR_16BIT(TACCR0); /* Timer A Capture/Compare 0 */ |
| SFR_16BIT(TACCR1); /* Timer A Capture/Compare 1 */ |
| SFR_16BIT(TACCR2); /* Timer A Capture/Compare 2 */ |
| |
| /* Alternate register names */ |
| #define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ |
| #define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ |
| #define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ |
| #define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ |
| #define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ |
| #define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ |
| #define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ |
| #define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ |
| #define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ |
| #define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ |
| #define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ |
| #define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ |
| |
| #define TASSEL1 (0x0200) /* Timer A clock source select 0 */ |
| #define TASSEL0 (0x0100) /* Timer A clock source select 1 */ |
| #define ID1 (0x0080) /* Timer A clock input divider 1 */ |
| #define ID0 (0x0040) /* Timer A clock input divider 0 */ |
| #define MC1 (0x0020) /* Timer A mode control 1 */ |
| #define MC0 (0x0010) /* Timer A mode control 0 */ |
| #define TACLR (0x0004) /* Timer A counter clear */ |
| #define TAIE (0x0002) /* Timer A counter interrupt enable */ |
| #define TAIFG (0x0001) /* Timer A counter interrupt flag */ |
| |
| #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ |
| #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ |
| #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */ |
| #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ |
| #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ |
| #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ |
| #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ |
| #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ |
| #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ |
| #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ |
| #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ |
| #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ |
| |
| #define CM1 (0x8000) /* Capture mode 1 */ |
| #define CM0 (0x4000) /* Capture mode 0 */ |
| #define CCIS1 (0x2000) /* Capture input select 1 */ |
| #define CCIS0 (0x1000) /* Capture input select 0 */ |
| #define SCS (0x0800) /* Capture sychronize */ |
| #define SCCI (0x0400) /* Latched capture signal (read) */ |
| #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ |
| #define OUTMOD2 (0x0080) /* Output mode 2 */ |
| #define OUTMOD1 (0x0040) /* Output mode 1 */ |
| #define OUTMOD0 (0x0020) /* Output mode 0 */ |
| #define CCIE (0x0010) /* Capture/compare interrupt enable */ |
| #define CCI (0x0008) /* Capture input signal (read) */ |
| #define OUT (0x0004) /* PWM Output signal if output mode 0 */ |
| #define COV (0x0002) /* Capture/compare overflow flag */ |
| #define CCIFG (0x0001) /* Capture/compare interrupt flag */ |
| |
| #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ |
| #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ |
| #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ |
| #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ |
| #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ |
| #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ |
| #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ |
| #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ |
| #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ |
| #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ |
| #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ |
| #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ |
| #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ |
| #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ |
| #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ |
| #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ |
| |
| /* TA3IV Definitions */ |
| #define TAIV_NONE (0x0000) /* No Interrupt pending */ |
| #define TAIV_TACCR1 (0x0002) /* TACCR1_CCIFG */ |
| #define TAIV_TACCR2 (0x0004) /* TACCR2_CCIFG */ |
| #define TAIV_6 (0x0006) /* Reserved */ |
| #define TAIV_8 (0x0008) /* Reserved */ |
| #define TAIV_TAIFG (0x000A) /* TAIFG */ |
| |
| /************************************************************ |
| * Timer B3 |
| ************************************************************/ |
| #define __MSP430_HAS_TB3__ /* Definition to show that Module is available */ |
| |
| SFR_16BIT(TBIV); /* Timer B Interrupt Vector Word */ |
| SFR_16BIT(TBCTL); /* Timer B Control */ |
| SFR_16BIT(TBCCTL0); /* Timer B Capture/Compare Control 0 */ |
| SFR_16BIT(TBCCTL1); /* Timer B Capture/Compare Control 1 */ |
| SFR_16BIT(TBCCTL2); /* Timer B Capture/Compare Control 2 */ |
| SFR_16BIT(TBR); /* Timer B */ |
| SFR_16BIT(TBCCR0); /* Timer B Capture/Compare 0 */ |
| SFR_16BIT(TBCCR1); /* Timer B Capture/Compare 1 */ |
| SFR_16BIT(TBCCR2); /* Timer B Capture/Compare 2 */ |
| |
| #define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */ |
| #define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */ |
| #define CNTL1 (0x1000) /* Counter lenght 1 */ |
| #define CNTL0 (0x0800) /* Counter lenght 0 */ |
| #define TBSSEL1 (0x0200) /* Clock source 1 */ |
| #define TBSSEL0 (0x0100) /* Clock source 0 */ |
| #define TBCLR (0x0004) /* Timer B counter clear */ |
| #define TBIE (0x0002) /* Timer B interrupt enable */ |
| #define TBIFG (0x0001) /* Timer B interrupt flag */ |
| |
| #define SHR1 (0x4000) /* Timer B Compare latch load group 1 */ |
| #define SHR0 (0x2000) /* Timer B Compare latch load group 0 */ |
| |
| #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */ |
| #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ |
| #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ |
| #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ |
| #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ |
| #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ |
| #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ |
| #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ |
| #define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */ |
| #define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ |
| #define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ |
| #define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */ |
| #define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */ |
| #define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ |
| #define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ |
| #define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */ |
| |
| /* Additional Timer B Control Register bits are defined in Timer A */ |
| |
| #define CLLD1 (0x0400) /* Compare latch load source 1 */ |
| #define CLLD0 (0x0200) /* Compare latch load source 0 */ |
| |
| #define SLSHR1 (0x0400) /* Compare latch load source 1 */ |
| #define SLSHR0 (0x0200) /* Compare latch load source 0 */ |
| |
| #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ |
| #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ |
| #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ |
| #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ |
| |
| #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ |
| #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ |
| #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ |
| #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ |
| |
| /* TB3IV Definitions */ |
| #define TBIV_NONE (0x0000) /* No Interrupt pending */ |
| #define TBIV_TBCCR1 (0x0002) /* TBCCR1_CCIFG */ |
| #define TBIV_TBCCR2 (0x0004) /* TBCCR2_CCIFG */ |
| #define TBIV_3 (0x0006) /* Reserved */ |
| #define TBIV_4 (0x0008) /* Reserved */ |
| #define TBIV_5 (0x000A) /* Reserved */ |
| #define TBIV_6 (0x000C) /* Reserved */ |
| #define TBIV_TBIFG (0x000E) /* TBIFG */ |
| |
| /************************************************************ |
| * USCI |
| ************************************************************/ |
| #define __MSP430_HAS_USCI__ /* Definition to show that Module is available */ |
| |
| SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */ |
| SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */ |
| SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */ |
| SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */ |
| SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */ |
| SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */ |
| SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */ |
| SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */ |
| SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */ |
| SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */ |
| SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */ |
| |
| |
| |
| SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */ |
| SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */ |
| SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */ |
| SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */ |
| SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */ |
| SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */ |
| SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */ |
| SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */ |
| SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */ |
| SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */ |
| |
| // UART-Mode Bits |
| #define UCPEN (0x80) /* Async. Mode: Parity enable */ |
| #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ |
| #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ |
| #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ |
| #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ |
| #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ |
| #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ |
| #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ |
| |
| // SPI-Mode Bits |
| #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ |
| #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ |
| #define UCMST (0x08) /* Sync. Mode: Master Select */ |
| |
| // I2C-Mode Bits |
| #define UCA10 (0x80) /* 10-bit Address Mode */ |
| #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ |
| #define UCMM (0x20) /* Multi-Master Environment */ |
| //#define res (0x10) /* reserved */ |
| #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ |
| #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ |
| #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ |
| #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ |
| |
| // UART-Mode Bits |
| #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ |
| #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ |
| #define UCRXEIE (0x20) /* RX Error interrupt enable */ |
| #define UCBRKIE (0x10) /* Break interrupt enable */ |
| #define UCDORM (0x08) /* Dormant (Sleep) Mode */ |
| #define UCTXADDR (0x04) /* Send next Data as Address */ |
| #define UCTXBRK (0x02) /* Send next Data as Break */ |
| #define UCSWRST (0x01) /* USCI Software Reset */ |
| |
| // SPI-Mode Bits |
| //#define res (0x20) /* reserved */ |
| //#define res (0x10) /* reserved */ |
| //#define res (0x08) /* reserved */ |
| //#define res (0x04) /* reserved */ |
| //#define res (0x02) /* reserved */ |
| |
| // I2C-Mode Bits |
| //#define res (0x20) /* reserved */ |
| #define UCTR (0x10) /* Transmit/Receive Select/Flag */ |
| #define UCTXNACK (0x08) /* Transmit NACK */ |
| #define UCTXSTP (0x04) /* Transmit STOP */ |
| #define UCTXSTT (0x02) /* Transmit START */ |
| #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ |
| #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ |
| #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ |
| #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ |
| |
| #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ |
| #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ |
| #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ |
| #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ |
| #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ |
| #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ |
| #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ |
| #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ |
| |
| #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ |
| #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ |
| #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ |
| #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ |
| #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ |
| #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ |
| #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ |
| #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ |
| #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ |
| #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ |
| #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ |
| #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ |
| #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ |
| #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ |
| #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ |
| #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ |
| |
| #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ |
| #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ |
| #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ |
| #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ |
| #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ |
| #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ |
| #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ |
| #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ |
| |
| #define UCLISTEN (0x80) /* USCI Listen mode */ |
| #define UCFE (0x40) /* USCI Frame Error Flag */ |
| #define UCOE (0x20) /* USCI Overrun Error Flag */ |
| #define UCPE (0x10) /* USCI Parity Error Flag */ |
| #define UCBRK (0x08) /* USCI Break received */ |
| #define UCRXERR (0x04) /* USCI RX Error Flag */ |
| #define UCADDR (0x02) /* USCI Address received Flag */ |
| #define UCBUSY (0x01) /* USCI Busy Flag */ |
| #define UCIDLE (0x02) /* USCI Idle line detected Flag */ |
| |
| //#define res (0x80) /* reserved */ |
| //#define res (0x40) /* reserved */ |
| //#define res (0x20) /* reserved */ |
| //#define res (0x10) /* reserved */ |
| #define UCNACKIE (0x08) /* NACK Condition interrupt enable */ |
| #define UCSTPIE (0x04) /* STOP Condition interrupt enable */ |
| #define UCSTTIE (0x02) /* START Condition interrupt enable */ |
| #define UCALIE (0x01) /* Arbitration Lost interrupt enable */ |
| |
| #define UCSCLLOW (0x40) /* SCL low */ |
| #define UCGC (0x20) /* General Call address received Flag */ |
| #define UCBBUSY (0x10) /* Bus Busy Flag */ |
| #define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */ |
| #define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */ |
| #define UCSTTIFG (0x02) /* START Condition interrupt Flag */ |
| #define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */ |
| |
| #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ |
| #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ |
| #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ |
| #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ |
| #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ |
| #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ |
| #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ |
| #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ |
| |
| #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ |
| #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ |
| #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ |
| #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ |
| #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ |
| #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ |
| #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ |
| #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ |
| |
| //#define res (0x80) /* reserved */ |
| //#define res (0x40) /* reserved */ |
| #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ |
| #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ |
| #define UCSTOE (0x08) /* Sync-Field Timeout error */ |
| #define UCBTOE (0x04) /* Break Timeout error */ |
| //#define res (0x02) /* reserved */ |
| #define UCABDEN (0x01) /* Auto Baud Rate detect enable */ |
| |
| #define UCGCEN (0x8000) /* I2C General Call enable */ |
| #define UCOA9 (0x0200) /* I2C Own Address 9 */ |
| #define UCOA8 (0x0100) /* I2C Own Address 8 */ |
| #define UCOA7 (0x0080) /* I2C Own Address 7 */ |
| #define UCOA6 (0x0040) /* I2C Own Address 6 */ |
| #define UCOA5 (0x0020) /* I2C Own Address 5 */ |
| #define UCOA4 (0x0010) /* I2C Own Address 4 */ |
| #define UCOA3 (0x0008) /* I2C Own Address 3 */ |
| #define UCOA2 (0x0004) /* I2C Own Address 2 */ |
| #define UCOA1 (0x0002) /* I2C Own Address 1 */ |
| #define UCOA0 (0x0001) /* I2C Own Address 0 */ |
| |
| #define UCSA9 (0x0200) /* I2C Slave Address 9 */ |
| #define UCSA8 (0x0100) /* I2C Slave Address 8 */ |
| #define UCSA7 (0x0080) /* I2C Slave Address 7 */ |
| #define UCSA6 (0x0040) /* I2C Slave Address 6 */ |
| #define UCSA5 (0x0020) /* I2C Slave Address 5 */ |
| #define UCSA4 (0x0010) /* I2C Slave Address 4 */ |
| #define UCSA3 (0x0008) /* I2C Slave Address 3 */ |
| #define UCSA2 (0x0004) /* I2C Slave Address 2 */ |
| #define UCSA1 (0x0002) /* I2C Slave Address 1 */ |
| #define UCSA0 (0x0001) /* I2C Slave Address 0 */ |
| |
| /************************************************************ |
| * WATCHDOG TIMER |
| ************************************************************/ |
| #define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ |
| |
| SFR_16BIT(WDTCTL); /* Watchdog Timer Control */ |
| /* The bit names have been prefixed with "WDT" */ |
| #define WDTIS0 (0x0001) |
| #define WDTIS1 (0x0002) |
| #define WDTSSEL (0x0004) |
| #define WDTCNTCL (0x0008) |
| #define WDTTMSEL (0x0010) |
| #define WDTNMI (0x0020) |
| #define WDTNMIES (0x0040) |
| #define WDTHOLD (0x0080) |
| |
| #define WDTPW (0x5A00) |
| |
| /* WDT-interval times [1ms] coded with Bits 0-2 */ |
| /* WDT is clocked by fSMCLK (assumed 1MHz) */ |
| #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ |
| #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ |
| #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ |
| #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ |
| /* WDT is clocked by fACLK (assumed 32KHz) */ |
| #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ |
| #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ |
| #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ |
| #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ |
| /* Watchdog mode -> reset after expired time */ |
| /* WDT is clocked by fSMCLK (assumed 1MHz) */ |
| #define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ |
| #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ |
| #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ |
| #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ |
| /* WDT is clocked by fACLK (assumed 32KHz) */ |
| #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ |
| #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ |
| #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ |
| #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ |
| |
| /* INTERRUPT CONTROL */ |
| /* These two bits are defined in the Special Function Registers */ |
| /* #define WDTIE 0x01 */ |
| /* #define WDTIFG 0x01 */ |
| |
| /************************************************************ |
| * Calibration Data in Info Mem |
| ************************************************************/ |
| |
| #ifndef __DisableCalData |
| |
| SFR_8BIT(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */ |
| SFR_8BIT(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */ |
| SFR_8BIT(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */ |
| SFR_8BIT(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */ |
| SFR_8BIT(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */ |
| SFR_8BIT(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */ |
| SFR_8BIT(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */ |
| SFR_8BIT(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */ |
| |
| #endif /* #ifndef __DisableCalData */ |
| |
| /************************************************************ |
| * Interrupt Vectors (offset from 0xFFE0) |
| ************************************************************/ |
| |
| #define VECTOR_NAME(name) name##_ptr |
| #define EMIT_PRAGMA(x) _Pragma(#x) |
| #define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name |
| #define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section)) |
| #define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \ |
| PLACE_VECTOR(VECTOR_NAME(func), offset) |
| |
| #define PORT1_VECTOR (2 * 1u) /* 0xFFE4 Port 1 */ |
| /*#define PORT1_ISR(func) ISR_VECTOR(func, ".int02") */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */ |
| #define PORT2_VECTOR (3 * 1u) /* 0xFFE6 Port 2 */ |
| /*#define PORT2_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */ |
| #define ADC10_VECTOR (5 * 1u) /* 0xFFEA ADC10 */ |
| /*#define ADC10_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA ADC10 */ /* CCE V2 Style */ |
| #define USCIAB0TX_VECTOR (6 * 1u) /* 0xFFEC USCI A0/B0 Transmit */ |
| /*#define USCIAB0TX_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC USCI A0/B0 Transmit */ /* CCE V2 Style */ |
| #define USCIAB0RX_VECTOR (7 * 1u) /* 0xFFEE USCI A0/B0 Receive */ |
| /*#define USCIAB0RX_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE USCI A0/B0 Receive */ /* CCE V2 Style */ |
| #define TIMERA1_VECTOR (8 * 1u) /* 0xFFF0 Timer A CC1-2, TA */ |
| /*#define TIMERA1_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 Timer A CC1-2, TA */ /* CCE V2 Style */ |
| #define TIMERA0_VECTOR (9 * 1u) /* 0xFFF2 Timer A CC0 */ |
| /*#define TIMERA0_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Timer A CC0 */ /* CCE V2 Style */ |
| #define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */ |
| /*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */ |
| #define TIMERB1_VECTOR (12 * 1u) /* 0xFFF8 Timer B CC1-2, TB */ |
| /*#define TIMERB1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer B CC1-2, TB */ /* CCE V2 Style */ |
| #define TIMERB0_VECTOR (13 * 1u) /* 0xFFFA Timer B CC0 */ |
| /*#define TIMERB0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer B CC0 */ /* CCE V2 Style */ |
| #define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */ |
| /*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */ |
| #define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */ |
| /*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */ |
| |
| /************************************************************ |
| * End of Modules |
| ************************************************************/ |
| |
| #ifdef __cplusplus |
| } |
| #endif /* extern "C" */ |
| |
| #endif /* #ifndef __msp430x22x4 */ |
| |
